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1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2009 by Michael Sevakis
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#ifndef SDMA_IMX31_H
22#define SDMA_IMX31_H
23
24/* Much of the code in here is based upon the Linux BSP provided by Freescale
25 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. */
26
27/* Peripheral and transfer type - used to select the proper SDMA channel
28 * script to execute. */
29enum SDMA_PERIPHERAL_TYPE
30{
31 __SDMA_PER_FIRST = -1,
32 SDMA_PER_MEMORY,
33 SDMA_PER_DSP,
34 SDMA_PER_FIRI,
35 SDMA_PER_UART,
36 SDMA_PER_UART_SP, /* Shared */
37 SDMA_PER_ATA,
38 SDMA_PER_CSPI,
39 SDMA_PER_EXT,
40 SDMA_PER_SSI,
41 SDMA_PER_SSI_SP, /* Shared */
42 SDMA_PER_MMC,
43 SDMA_PER_SDHC,
44 SDMA_PER_CSPI_SP, /* Shared */
45 SDMA_PER_MSHC,
46 SDMA_PER_MSHC_SP, /* Shared */
47 SDMA_PER_CCM,
48 SDMA_PER_ASRC,
49 SDMA_PER_ESAI,
50 SDMA_PER_SIM,
51 SDMA_PER_SPDIF,
52 SDMA_PER_IPU_MEMORY,
53};
54
55enum SDMA_TRANSFER_TYPE
56{
57 __SDMA_TRAN_FIRST = -1,
58 SDMA_TRAN_INT_2_INT,
59 SDMA_TRAN_EMI_2_INT,
60 SDMA_TRAN_EMI_2_EMI,
61 SDMA_TRAN_INT_2_EMI,
62
63 SDMA_TRAN_INT_2_DSP,
64 SDMA_TRAN_DSP_2_INT,
65 SDMA_TRAN_DSP_2_DSP,
66 SDMA_TRAN_DSP_2_PER,
67 SDMA_TRAN_PER_2_DSP,
68 SDMA_TRAN_EMI_2_DSP,
69 SDMA_TRAN_DSP_2_EMI,
70 SDMA_TRAN_DSP_2_EMI_LOOP,
71 SDMA_TRAN_EMI_2_DSP_LOOP,
72
73 SDMA_TRAN_PER_2_INT,
74 SDMA_TRAN_PER_2_EMI,
75 SDMA_TRAN_INT_2_PER,
76 SDMA_TRAN_EMI_2_PER,
77};
78
79/* 2.3 - Smart Direct Memory Access (SDMA) Events, Table 2-5 */
80/* These are indexes into the SDMA_CHNENBL register array (each a bitmask
81 * determining which channels are triggered by requests). */
82enum SDMA_REQUEST_TYPE
83{
84 SDMA_REQ_EXT0 = 0, /* Extern DMA request from MCU1_0 */
85 SDMA_REQ_CCM = 1, /* DVFS/DPTC event (ccm_dvfs_sdma_int) */
86 SDMA_REQ_ATA_TX_END = 2, /* ata_txfer_end_alarm (event_id) */
87 SDMA_REQ_ATA_TX = 3, /* ata_tx_fifo_alarm (event_id2) */
88 SDMA_REQ_ATA_RX = 4, /* ata_rcv_fifo_alarm (event_id2) */
89 SDMA_REQ_SIM = 5, /* */
90 SDMA_REQ_CSPI2_RX = 6, /* DMA Rx request */
91 SDMA_REQ_CSPI2_TX = 7, /* DMA Tx request */
92 SDMA_REQ_CSPI1_RX = 8, /* DMA Rx request of CSPI */
93 SDMA_REQ_UART3_RX = 8, /* DMA Rx request RxFIFO of UART3 */
94 SDMA_REQ_CSPI1_TX = 9, /* DMA Tx request of CSPI */
95 SDMA_REQ_UART3_TX = 9, /* DMA Tx request TxFIFO of UART3 */
96 SDMA_REQ_CSPI3_RX = 10, /* RxFIFO or CSPI3 Rx request */
97 SDMA_REQ_UART5_RX = 10, /* RxFIFO or CSPI3 Rx request */
98 SDMA_REQ_CSPI3_TX = 11, /* TxFIFO or CSPI3 Tx request */
99 SDMA_REQ_UART5_TX = 11, /* TxFIFO or CSPI3 Tx request */
100 SDMA_REQ_UART4_RX = 12, /* RxFIFO */
101 SDMA_REQ_UART4_TX = 13, /* TxFIFO */
102 SDMA_REQ_EXT2 = 14, /* External DMA request from MCU1_2 or from
103 MBX (Graphic accelerator) */
104 SDMA_REQ_EXT1 = 15, /* External request from MCU1_1 */
105 SDMA_REQ_FIRI_RX = 16, /* DMA request of FIR's receiver FIFO
106 controlled by the pgp_firi signal
107 from the IOMUXC PGP register */
108 SDMA_REQ_UART2_RX = 16, /* RxFIFO of UART2 */
109 SDMA_REQ_FIRI_TX = 17, /* DMA request of FIR's transmitter
110 FIFO controled by the pgp_firi signal
111 the IOMUXC PGP register */
112 SDMA_REQ_UART2_TX = 17, /* TxFIFO of UART2 */
113 SDMA_REQ_UART1_RX = 18, /* RxFIFO */
114 SDMA_REQ_UART1_TX = 19, /* TxFIFO */
115 SDMA_REQ_MMC1 = 20, /* MMC DMA request */
116 SDMA_REQ_SDHC1 = 20, /* SDHC1 DMA request */
117 SDMA_REQ_MSHC1 = 20, /* MSHC1 DMA request */
118 SDMA_REQ_MMC2 = 21, /* MMC DMA request */
119 SDMA_REQ_SDHC2 = 21, /* SDHC2 DMA request */
120 SDMA_REQ_MSHC2 = 21, /* MSHC2 DMA request */
121 SDMA_REQ_SSI2_RX2 = 22, /* SSI #2 receive 2 DMA request (SRX1_2) */
122 SDMA_REQ_SSI2_TX2 = 23, /* SSI #2 transmit 2 DMA request (STX1_2) */
123 SDMA_REQ_SSI2_RX1 = 24, /* SSI #2 receive 1 DMA request (SRX0_2) */
124 SDMA_REQ_SSI2_TX1 = 25, /* SSI #2 transmit 1 DMA request (STX0_2) */
125 SDMA_REQ_SSI1_RX2 = 26, /* SSI #1 receive 2 DMA request (SRX1_1) */
126 SDMA_REQ_SSI1_TX2 = 27, /* SSI #1 transmit 2 DMA request (STX1_1) */
127 SDMA_REQ_SSI1_RX1 = 28, /* SSI #1 receive 1 DMA request (SRX1_0) */
128 SDMA_REQ_SSI1_TX1 = 29, /* SSI #1 transmit 1 DMA request (STX1_0) */
129 SDMA_REQ_NFC = 30, /* NAND-flash controller */
130 SDMA_REQ_IPU = 31, /* IPU source (defaults to IPU at reset) */
131 SDMA_REQ_ECT = 31, /* ECT source */
132};
133
134/* Addresses for peripheral DMA transfers */
135enum SDMA_PER_ADDR
136{
137 SDMA_PER_ADDR_SDRAM = SDRAM_BASE_ADDR, /* memory */
138 SDMA_PER_ADDR_CCM = CCM_BASE_ADDR+0x00, /* CCMR */
139 /* ATA */
140 SDMA_PER_ADDR_ATA_TX = ATA_DMA_BASE_ADDR+0x18,
141 SDMA_PER_ADDR_ATA_RX = ATA_DMA_BASE_ADDR,
142#if 0
143 SDMA_PER_ADDR_ATA_TX16 =
144 SDMA_PER_ADDR_ATA_RX16 =
145#endif
146#if 0
147 SDMA_PER_ADDR_SIM =
148#endif
149 /* CSPI2 */
150 SDMA_PER_ADDR_CSPI2_RX = CSPI2_BASE_ADDR+0x00, /* RXDATA2 */
151 SDMA_PER_ADDR_CSPI2_TX = CSPI2_BASE_ADDR+0x04, /* TXDATA2 */
152 /* CSPI1 */
153 SDMA_PER_ADDR_CSPI1_RX = CSPI1_BASE_ADDR+0x00, /* RXDATA1 */
154 SDMA_PER_ADDR_CSPI1_TX = CSPI1_BASE_ADDR+0x04, /* TXDATA1 */
155 /* UART3 */
156 SDMA_PER_ADDR_UART3_RX = UART3_BASE_ADDR+0x00, /* URXD3 */
157 SDMA_PER_ADDR_UART3_TX = UART3_BASE_ADDR+0x40, /* UTXD3 */
158 /* CSPI3 */
159 SDMA_PER_ADDR_CSPI3_RX = CSPI3_BASE_ADDR+0x00, /* RXDATA3 */
160 SDMA_PER_ADDR_CSPI3_TX = CSPI3_BASE_ADDR+0x04, /* TXDATA3 */
161 /* UART5 */
162 SDMA_PER_ADDR_UART5_RX = UART5_BASE_ADDR+0x00, /* URXD5 */
163 SDMA_PER_ADDR_UART5_TX = UART5_BASE_ADDR+0x40, /* UTXD5 */
164 /* UART4 */
165 SDMA_PER_ADDR_UART4_RX = UART4_BASE_ADDR+0x00, /* URXD4 */
166 SDMA_PER_ADDR_UART4_TX = UART4_BASE_ADDR+0x40, /* UTXD4 */
167 /* FIRI */
168 SDMA_PER_ADDR_FIRI_RX = FIRI_BASE_ADDR+0x18, /* Receiver FIFO */
169 SDMA_PER_ADDR_FIRI_TX = FIRI_BASE_ADDR+0x14, /* Transmitter FIFO */
170 /* UART2 */
171 SDMA_PER_ADDR_UART2_RX = UART2_BASE_ADDR+0x00, /* URXD2 */
172 SDMA_PER_ADDR_UART2_TX = UART2_BASE_ADDR+0x40, /* UTXD2 */
173 /* UART1 */
174 SDMA_PER_ADDR_UART1_RX = UART1_BASE_ADDR+0x00, /* URXD1 */
175 SDMA_PER_ADDR_UART1_TX = UART1_BASE_ADDR+0x40, /* UTXD1 */
176 SDMA_PER_ADDR_MMC_SDHC1 = MMC_SDHC1_BASE_ADDR+0x38, /* BUFFER_ACCESS */
177 SDMA_PER_ADDR_MMC_SDHC2 = MMC_SDHC2_BASE_ADDR+0x38, /* BUFFER_ACCESS */
178#if 0
179 SDMA_PER_ADDR_MSHC1 =
180 SDMA_PER_ADDR_MSHC2 =
181#endif
182 /* SSI2 */
183 SDMA_PER_ADDR_SSI2_RX2 = SSI2_BASE_ADDR+0x0C, /* SRX1_2 */
184 SDMA_PER_ADDR_SSI2_TX2 = SSI2_BASE_ADDR+0x04, /* STX1_2 */
185 SDMA_PER_ADDR_SSI2_RX1 = SSI2_BASE_ADDR+0x08, /* SRX0_2 */
186 SDMA_PER_ADDR_SSI2_TX1 = SSI2_BASE_ADDR+0x00, /* STX0_2 */
187 /* SSI1 */
188 SDMA_PER_ADDR_SSI1_RX2 = SSI1_BASE_ADDR+0x0C, /* SRX1_1 */
189 SDMA_PER_ADDR_SSI1_TX2 = SSI1_BASE_ADDR+0x04, /* STX1_1 */
190 SDMA_PER_ADDR_SSI1_RX1 = SSI1_BASE_ADDR+0x08, /* SRX0_1 */
191 SDMA_PER_ADDR_SSI1_TX1 = SSI1_BASE_ADDR+0x00, /* STX0_1 */
192#if 0
193 SDMA_PER_ADDR_NFC =
194 SDMA_PER_ADDR_IPU =
195 SDMA_PER_ADDR_ECT =
196#endif
197};
198
199/* DMA driver defines */
200#define SDMA_SDHC_MMC_WML 16
201#define SDMA_SDHC_SD_WML 64
202#define SDMA_SSI_TXFIFO_WML 4 /* Four samples written per channel activation */
203#define SDMA_SSI_RXFIFO_WML 6 /* Six samples read per channel activation */
204#define SDMA_FIRI_WML 16
205
206#define SDMA_ATA_WML 32 /* DMA watermark level in bytes */
207#define SDMA_ATA_BD_NR (512/3/4) /* Number of BDs per channel */
208
209#include "sdma_struct.h"
210
211void sdma_init(void);
212void sdma_read_words(unsigned long *buf, unsigned long start, int count);
213void sdma_write_words(const unsigned long *buf, unsigned long start, int count);
214void sdma_channel_set_priority(unsigned int channel, unsigned int priority);
215void sdma_channel_start(unsigned int channel);
216void sdma_channel_run(unsigned int channel);
217void sdma_channel_pause(unsigned int channel);
218void sdma_channel_stop(unsigned int channel);
219void sdma_channel_wait_nonblocking(unsigned int channel);
220bool sdma_channel_init(unsigned int channel,
221 struct channel_descriptor *cd_p,
222 struct buffer_descriptor *base_bd_p);
223void sdma_channel_close(unsigned int channel);
224
225#endif /* SDMA_IMX31_H */
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-05 13:17:06 +0000