3 files changed, 2 insertions, 5 deletions

diff --git a/firmware/target/arm/imx31/gigabeat-s/adc-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/adc-gigabeat-s.c
index 52293228f8..f7bc0ed37c 100644
--- a/firmware/target/arm/imx31/gigabeat-s/adc-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/adc-gigabeat-s.c
@@ -71,7 +71,7 @@ unsigned short adc_read(int channel)
 
         /* Read all 8 channels that are converted - two channels in each
          * word. */
-        mc13783_read_regset(reg_array, channels[input_select], 4);
+        mc13783_read_regs(reg_array, channels[input_select], 4);
 
         last_adc_read[input_select] = current_tick;
     }
diff --git a/firmware/target/arm/imx31/gigabeat-s/backlight-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/backlight-gigabeat-s.c
index ab14a3c025..95f894bbce 100644
--- a/firmware/target/arm/imx31/gigabeat-s/backlight-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/backlight-gigabeat-s.c
@@ -143,7 +143,7 @@ void _backlight_on(void)
         data[1] |= backlight_pwm_bits;
 
         /* Write regs within 30us of each other (requires single xfer) */
-        mc13783_write_regset(regs, data, 2);
+        mc13783_write_regs(regs, data, 2);
     }
 }
 
diff --git a/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h b/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h
index 2356e23252..4876736a2b 100644
--- a/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h
+++ b/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h
@@ -75,9 +75,6 @@
 /* Define mask of which reference circuits are employed for DPTC */
 #define DPTC_DRCE_MASK (CCM_PMCR0_DRCE1 | CCM_PMCR0_DRCE3)
 
-/* When panicing, this working point is used */
-#define DPTC_PANIC_WP
-
 /* Due to a hardware bug in chip revisions < 2.0, when switching between
  * Serial and MCU PLLs, DVFS forces the target PLL to go into reset and
  * relock, only post divider frequency scaling is possible.