diff options
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/spi-imx31.c')
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/spi-imx31.c | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c index 815ffca21a..98604d1eef 100644 --- a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c | |||
@@ -220,6 +220,15 @@ static bool spi_set_context(struct spi_node *node, | |||
220 | return true; | 220 | return true; |
221 | } | 221 | } |
222 | 222 | ||
223 | static void spi_reset(struct cspi_map * const base) | ||
224 | { | ||
225 | /* Reset */ | ||
226 | base->conreg &= ~CSPI_CONREG_EN; | ||
227 | base->conreg |= CSPI_CONREG_EN; | ||
228 | base->intreg = 0; | ||
229 | base->statreg = CSPI_STATREG_TC | CSPI_STATREG_BO; | ||
230 | } | ||
231 | |||
223 | /* Initialize each of the used SPI descriptors */ | 232 | /* Initialize each of the used SPI descriptors */ |
224 | void spi_init(void) | 233 | void spi_init(void) |
225 | { | 234 | { |
@@ -259,13 +268,9 @@ void spi_enable_module(struct spi_node *node) | |||
259 | 268 | ||
260 | /* Enable clock-gating register */ | 269 | /* Enable clock-gating register */ |
261 | imx31_clkctl_module_clock_gating(desc->cg, CGM_ON_ALL); | 270 | imx31_clkctl_module_clock_gating(desc->cg, CGM_ON_ALL); |
262 | |||
263 | /* Reset */ | 271 | /* Reset */ |
264 | base->conreg &= ~CSPI_CONREG_EN; | 272 | spi_reset(base); |
265 | base->conreg |= CSPI_CONREG_EN; | 273 | desc->last = NULL; |
266 | base->intreg = 0; | ||
267 | base->statreg = CSPI_STATREG_TC | CSPI_STATREG_BO; | ||
268 | |||
269 | /* Enable interrupt at controller level */ | 274 | /* Enable interrupt at controller level */ |
270 | avic_enable_int(desc->ints, IRQ, 6, desc->handler); | 275 | avic_enable_int(desc->ints, IRQ, 6, desc->handler); |
271 | } | 276 | } |
@@ -333,8 +338,9 @@ int spi_transfer(struct spi_node *node, struct spi_transfer *trans) | |||
333 | 338 | ||
334 | if (wakeup_wait(&desc->w, HZ) != OBJ_WAIT_SUCCEEDED) | 339 | if (wakeup_wait(&desc->w, HZ) != OBJ_WAIT_SUCCEEDED) |
335 | { | 340 | { |
336 | base->intreg = 0; | 341 | base->intreg = 0; /* Stop SPI ints */ |
337 | base->conreg &= ~CSPI_CONREG_XCH; | 342 | spi_reset(base); /* Reset module (esp. to empty FIFOs) */ |
343 | desc->last = NULL; /* Force reconfigure */ | ||
338 | retval = false; | 344 | retval = false; |
339 | } | 345 | } |
340 | } | 346 | } |