diff options
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c')
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c | 96 |
1 files changed, 3 insertions, 93 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c index 65571a4ee2..1c21415752 100644 --- a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c | |||
@@ -23,7 +23,7 @@ | |||
23 | #include "kernel.h" | 23 | #include "kernel.h" |
24 | #include "audio.h" | 24 | #include "audio.h" |
25 | #include "sound.h" | 25 | #include "sound.h" |
26 | #include "ccm-imx31.h" | 26 | //#include "ccm-imx31.h" |
27 | #include "sdma-imx31.h" | 27 | #include "sdma-imx31.h" |
28 | #include "mmu-imx31.h" | 28 | #include "mmu-imx31.h" |
29 | #include "pcm-internal.h" | 29 | #include "pcm-internal.h" |
@@ -149,101 +149,11 @@ void pcm_dma_apply_settings(void) | |||
149 | 149 | ||
150 | void pcm_play_dma_init(void) | 150 | void pcm_play_dma_init(void) |
151 | { | 151 | { |
152 | /* Init channel information */ | 152 | /* Init DMA channel information */ |
153 | sdma_channel_init(DMA_PLAY_CH_NUM, &dma_play_cd, &dma_play_bd); | 153 | sdma_channel_init(DMA_PLAY_CH_NUM, &dma_play_cd, &dma_play_bd); |
154 | sdma_channel_set_priority(DMA_PLAY_CH_NUM, DMA_PLAY_CH_PRIORITY); | 154 | sdma_channel_set_priority(DMA_PLAY_CH_NUM, DMA_PLAY_CH_PRIORITY); |
155 | 155 | ||
156 | ccm_module_clock_gating(CG_SSI1, CGM_ON_RUN_WAIT); | 156 | /* Init audio interfaces */ |
157 | ccm_module_clock_gating(CG_SSI2, CGM_ON_RUN_WAIT); | ||
158 | |||
159 | /* Reset & disable SSIs */ | ||
160 | SSI_SCR1 &= ~SSI_SCR_SSIEN; | ||
161 | SSI_SCR2 &= ~SSI_SCR_SSIEN; | ||
162 | |||
163 | SSI_SIER1 = 0; | ||
164 | SSI_SIER2 = 0; | ||
165 | |||
166 | /* Set up audio mux */ | ||
167 | |||
168 | /* Port 2 (internally connected to SSI2) | ||
169 | * All clocking is output sourced from port 4 */ | ||
170 | AUDMUX_PTCR2 = AUDMUX_PTCR_TFS_DIR | AUDMUX_PTCR_TFSEL_PORT4 | | ||
171 | AUDMUX_PTCR_TCLKDIR | AUDMUX_PTCR_TCSEL_PORT4 | | ||
172 | AUDMUX_PTCR_SYN; | ||
173 | |||
174 | /* Receive data from port 4 */ | ||
175 | AUDMUX_PDCR2 = AUDMUX_PDCR_RXDSEL_PORT4; | ||
176 | /* All clock lines are inputs sourced from the master mode codec and | ||
177 | * sent back to SSI2 through port 2 */ | ||
178 | AUDMUX_PTCR4 = AUDMUX_PTCR_SYN; | ||
179 | |||
180 | /* Receive data from port 2 */ | ||
181 | AUDMUX_PDCR4 = AUDMUX_PDCR_RXDSEL_PORT2; | ||
182 | |||
183 | /* PORT1 (internally connected to SSI1) routes clocking to PORT5 to | ||
184 | * provide MCLK to the codec */ | ||
185 | /* TX clocks are inputs taken from SSI2 */ | ||
186 | /* RX clocks are outputs taken from PORT4 */ | ||
187 | AUDMUX_PTCR1 = AUDMUX_PTCR_RFS_DIR | AUDMUX_PTCR_RFSSEL_PORT4 | | ||
188 | AUDMUX_PTCR_RCLKDIR | AUDMUX_PTCR_RCSEL_PORT4; | ||
189 | /* RX data taken from PORT4 */ | ||
190 | AUDMUX_PDCR1 = AUDMUX_PDCR_RXDSEL_PORT4; | ||
191 | |||
192 | /* PORT5 outputs TCLK sourced from PORT1 (SSI1) */ | ||
193 | AUDMUX_PTCR5 = AUDMUX_PTCR_TCLKDIR | AUDMUX_PTCR_TCSEL_PORT1; | ||
194 | AUDMUX_PDCR5 = 0; | ||
195 | |||
196 | /* Setup SSIs */ | ||
197 | |||
198 | /* SSI2 - SoC software interface for all I2S data out */ | ||
199 | SSI_SCR2 = SSI_SCR_SYN | SSI_SCR_I2S_MODE_SLAVE; | ||
200 | SSI_STCR2 = SSI_STCR_TXBIT0 | SSI_STCR_TSCKP | SSI_STCR_TFSI | | ||
201 | SSI_STCR_TEFS | SSI_STCR_TFEN0; | ||
202 | |||
203 | /* 16 bits per word, 2 words per frame */ | ||
204 | SSI_STCCR2 = SSI_STRCCR_WL16 | ((2-1) << SSI_STRCCR_DC_POS) | | ||
205 | ((4-1) << SSI_STRCCR_PM_POS); | ||
206 | |||
207 | /* Transmit low watermark */ | ||
208 | SSI_SFCSR2 = (SSI_SFCSR2 & ~SSI_SFCSR_TFWM0) | | ||
209 | ((8-SDMA_SSI_TXFIFO_WML) << SSI_SFCSR_TFWM0_POS); | ||
210 | SSI_STMSK2 = 0; | ||
211 | |||
212 | /* SSI1 - provides MCLK to codec. Receives data from codec. */ | ||
213 | SSI_STCR1 = SSI_STCR_TXDIR; | ||
214 | |||
215 | /* f(INT_BIT_CLK) = | ||
216 | * f(SYS_CLK) / [(DIV2 + 1)*(7*PSR + 1)*(PM + 1)*2] = | ||
217 | * 677737600 / [(1 + 1)*(7*0 + 1)*(0 + 1)*2] = | ||
218 | * 677737600 / 4 = 169344000 Hz | ||
219 | * | ||
220 | * 45.4.2.2 DIV2, PSR, and PM Bit Description states: | ||
221 | * Bits DIV2, PSR, and PM should not be all set to zero at the same | ||
222 | * time. | ||
223 | * | ||
224 | * The hardware seems to force a divide by 4 even if all bits are | ||
225 | * zero but comply by setting DIV2 and the others to zero. | ||
226 | */ | ||
227 | SSI_STCCR1 = SSI_STRCCR_DIV2 | ((1-1) << SSI_STRCCR_PM_POS); | ||
228 | |||
229 | /* SSI1 - receive - asynchronous clocks */ | ||
230 | SSI_SCR1 = SSI_SCR_I2S_MODE_SLAVE; | ||
231 | |||
232 | SSI_SRCR1 = SSI_SRCR_RXBIT0 | SSI_SRCR_RSCKP | SSI_SRCR_RFSI | | ||
233 | SSI_SRCR_REFS; | ||
234 | |||
235 | /* 16 bits per word, 2 words per frame */ | ||
236 | SSI_SRCCR1 = SSI_STRCCR_WL16 | ((2-1) << SSI_STRCCR_DC_POS) | | ||
237 | ((4-1) << SSI_STRCCR_PM_POS); | ||
238 | |||
239 | /* Receive high watermark */ | ||
240 | SSI_SFCSR1 = (SSI_SFCSR1 & ~SSI_SFCSR_RFWM0) | | ||
241 | (SDMA_SSI_RXFIFO_WML << SSI_SFCSR_RFWM0_POS); | ||
242 | SSI_SRMSK1 = 0; | ||
243 | |||
244 | /* Enable SSI1 (codec clock) */ | ||
245 | SSI_SCR1 |= SSI_SCR_SSIEN; | ||
246 | |||
247 | audiohw_init(); | 157 | audiohw_init(); |
248 | } | 158 | } |
249 | 159 | ||