diff options
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c')
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c index a2f3d779eb..01e9b8b721 100644 --- a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c | |||
@@ -38,11 +38,11 @@ static __attribute__((interrupt("IRQ"))) void EPIT1_HANDLER(void) | |||
38 | 38 | ||
39 | void tick_start(unsigned int interval_in_ms) | 39 | void tick_start(unsigned int interval_in_ms) |
40 | { | 40 | { |
41 | imx31_clkctl_module_clock_gating(CG_EPIT1, CGM_ON_ALL); /* EPIT1 module | 41 | ccm_module_clock_gating(CG_EPIT1, CGM_ON_RUN_WAIT); /* EPIT1 module |
42 | clock ON - before writing | 42 | clock ON - before writing |
43 | regs! */ | 43 | regs! */ |
44 | EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable the counter */ | 44 | EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable the counter */ |
45 | CLKCTL_WIMR0 &= ~WIM_IPI_INT_EPIT1; /* Clear wakeup mask */ | 45 | CCM_WIMR0 &= ~CCM_WIMR0_IPI_INT_EPIT1; /* Clear wakeup mask */ |
46 | 46 | ||
47 | /* mcu_main_clk = 528MHz = 27MHz * 2 * ((9 + 7/9) / 1) | 47 | /* mcu_main_clk = 528MHz = 27MHz * 2 * ((9 + 7/9) / 1) |
48 | * CLKSRC = ipg_clk = 528MHz / 4 / 2 = 66MHz, | 48 | * CLKSRC = ipg_clk = 528MHz / 4 / 2 = 66MHz, |
@@ -53,13 +53,14 @@ void tick_start(unsigned int interval_in_ms) | |||
53 | * Compare interrupt enabled, | 53 | * Compare interrupt enabled, |
54 | * Count from load value */ | 54 | * Count from load value */ |
55 | EPITCR1 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW | | 55 | EPITCR1 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW | |
56 | EPITCR_PRESCALER(2640-1) | EPITCR_RLD | EPITCR_OCIEN | | 56 | (2640-1) << EPITCR_PRESCALER_POS | EPITCR_RLD | EPITCR_OCIEN | |
57 | EPITCR_ENMOD; | 57 | EPITCR_ENMOD; |
58 | 58 | ||
59 | EPITLR1 = interval_in_ms*25; /* Count down from interval */ | 59 | EPITLR1 = interval_in_ms*25; /* Count down from interval */ |
60 | EPITCMPR1 = 0; /* Event when counter reaches 0 */ | 60 | EPITCMPR1 = 0; /* Event when counter reaches 0 */ |
61 | EPITSR1 = EPITSR_OCIF; /* Clear any pending interrupt */ | 61 | EPITSR1 = EPITSR_OCIF; /* Clear any pending interrupt */ |
62 | avic_enable_int(EPIT1, IRQ, 7, EPIT1_HANDLER); | 62 | avic_enable_int(INT_EPIT1, INT_TYPE_IRQ, INT_PRIO_DEFAULT, |
63 | EPIT1_HANDLER); | ||
63 | EPITCR1 |= EPITCR_EN; /* Enable the counter */ | 64 | EPITCR1 |= EPITCR_EN; /* Enable the counter */ |
64 | } | 65 | } |
65 | 66 | ||
@@ -73,9 +74,9 @@ void kernel_device_init(void) | |||
73 | #ifdef BOOTLOADER | 74 | #ifdef BOOTLOADER |
74 | void tick_stop(void) | 75 | void tick_stop(void) |
75 | { | 76 | { |
76 | avic_disable_int(EPIT1); /* Disable insterrupt */ | 77 | avic_disable_int(INT_EPIT1); /* Disable insterrupt */ |
77 | EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable counter */ | 78 | EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable counter */ |
78 | EPITSR1 = EPITSR_OCIF; /* Clear pending */ | 79 | EPITSR1 = EPITSR_OCIF; /* Clear pending */ |
79 | imx31_clkctl_module_clock_gating(CG_EPIT1, CGM_OFF); /* Turn off module clock */ | 80 | ccm_module_clock_gating(CG_EPIT1, CGM_OFF); /* Turn off module clock */ |
80 | } | 81 | } |
81 | #endif | 82 | #endif |