diff options
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h')
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h | 114 |
1 files changed, 0 insertions, 114 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h deleted file mode 100644 index e1057a9618..0000000000 --- a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h +++ /dev/null | |||
@@ -1,114 +0,0 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (c) 2008 Michael Sevakis | ||
11 | * | ||
12 | * Clock control functions for IMX31 processor | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef _CCM_IMX31_H_ | ||
24 | #define _CCM_IMX31_H_ | ||
25 | |||
26 | enum IMX31_CG_LIST | ||
27 | { | ||
28 | /* CGR0 */ | ||
29 | CG_SD_MMC1 = 0, | ||
30 | CG_SD_MMC2, | ||
31 | CG_GPT, | ||
32 | CG_EPIT1, | ||
33 | CG_EPIT2, | ||
34 | CG_IIM, | ||
35 | CG_ATA, | ||
36 | CG_SDMA, | ||
37 | CG_CSPI3, | ||
38 | CG_RNG, | ||
39 | CG_UART1, | ||
40 | CG_UART2, | ||
41 | CG_SSI1, | ||
42 | CG_I2C1, | ||
43 | CG_I2C2, | ||
44 | CG_I2C3, | ||
45 | /* CGR1 */ | ||
46 | CG_HANTRO, | ||
47 | CG_MEMSTICK1, | ||
48 | CG_MEMSTICK2, | ||
49 | CG_CSI, | ||
50 | CG_RTC, | ||
51 | CG_WDOG, | ||
52 | CG_PWM, | ||
53 | CG_SIM, | ||
54 | CG_ECT, | ||
55 | CG_USBOTG, | ||
56 | CG_KPP, | ||
57 | CG_IPU, | ||
58 | CG_UART3, | ||
59 | CG_UART4, | ||
60 | CG_UART5, | ||
61 | CG_1_WIRE, | ||
62 | /* CGR2 */ | ||
63 | CG_SSI2, | ||
64 | CG_CSPI1, | ||
65 | CG_CSPI2, | ||
66 | CG_GACC, | ||
67 | CG_EMI, | ||
68 | CG_RTIC, | ||
69 | CG_FIR, | ||
70 | CG_NUM_CLOCKS | ||
71 | }; | ||
72 | |||
73 | enum IMX31_CG_MODES | ||
74 | { | ||
75 | CGM_OFF = 0x0, /* Always off */ | ||
76 | CGM_ON_RUN = 0x1, /* On in run mode, off in wait and doze */ | ||
77 | CGM_ON_RUN_WAIT = 0x2, /* On in run and wait modes, off in doze */ | ||
78 | CGM_ON_ALL = 0x3, /* Always on */ | ||
79 | }; | ||
80 | |||
81 | #define CG_MASK 0x3 /* bitmask */ | ||
82 | |||
83 | /* Enable or disable module clocks independently - module must _not_ be | ||
84 | * active! */ | ||
85 | void ccm_module_clock_gating(enum IMX31_CG_LIST cg, | ||
86 | enum IMX31_CG_MODES mode); | ||
87 | |||
88 | enum IMX31_PLLS | ||
89 | { | ||
90 | PLL_MCU = 0, | ||
91 | PLL_USB, | ||
92 | PLL_SERIAL, | ||
93 | NUM_PLLS, | ||
94 | }; | ||
95 | |||
96 | #define CONFIG_CLK32_FREQ 32768 | ||
97 | #define CONFIG_HCLK_FREQ 27000000 | ||
98 | |||
99 | /* Get the PLL reference clock frequency in HZ */ | ||
100 | unsigned int ccm_get_pll_ref_clk(void); | ||
101 | |||
102 | /* Return PLL frequency in HZ */ | ||
103 | unsigned int ccm_get_pll(enum IMX31_PLLS pll); | ||
104 | |||
105 | /* Return ipg_clk in HZ */ | ||
106 | unsigned int ccm_get_ipg_clk(void); | ||
107 | |||
108 | /* Return ahb_clk in HZ */ | ||
109 | unsigned int ccm_get_ahb_clk(void); | ||
110 | |||
111 | /* Return the ATA frequency in HZ */ | ||
112 | unsigned int ccm_get_ata_clk(void); | ||
113 | |||
114 | #endif /* _CCM_IMX31_H_ */ | ||