diff options
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/adc-imx31.c')
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/adc-imx31.c | 30 |
1 files changed, 27 insertions, 3 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c b/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c index 85ef15b9b4..3c66c42adc 100644 --- a/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c | |||
@@ -84,6 +84,30 @@ unsigned short adc_read(int channel) | |||
84 | return (channel & 4) ? MC13783_ADD2r(data) : MC13783_ADD1r(data); | 84 | return (channel & 4) ? MC13783_ADD2r(data) : MC13783_ADD1r(data); |
85 | } | 85 | } |
86 | 86 | ||
87 | bool adc_enable_channel(int channel, bool enable) | ||
88 | { | ||
89 | uint32_t bit, mask; | ||
90 | |||
91 | switch (channel) | ||
92 | { | ||
93 | case ADC_CHARGER_CURRENT: | ||
94 | mask = MC13783_CHRGICON; | ||
95 | break; | ||
96 | |||
97 | case ADC_BATTERY_TEMP: | ||
98 | mask = MC13783_RTHEN; | ||
99 | break; | ||
100 | |||
101 | default: | ||
102 | return false; | ||
103 | } | ||
104 | |||
105 | bit = enable ? mask : 0; | ||
106 | |||
107 | return mc13783_write_masked(MC13783_ADC0, bit, mask) | ||
108 | != MC13783_DATA_ERROR; | ||
109 | } | ||
110 | |||
87 | /* Called by mc13783 interrupt thread when conversion is complete */ | 111 | /* Called by mc13783 interrupt thread when conversion is complete */ |
88 | void adc_done(void) | 112 | void adc_done(void) |
89 | { | 113 | { |
@@ -98,9 +122,9 @@ void adc_init(void) | |||
98 | /* Init so first reads get data */ | 122 | /* Init so first reads get data */ |
99 | last_adc_read[0] = last_adc_read[1] = current_tick-1; | 123 | last_adc_read[0] = last_adc_read[1] = current_tick-1; |
100 | 124 | ||
101 | /* Enable increment-by-read, thermistor, charge current */ | 125 | /* Enable increment-by-read, turn off extra conversions. */ |
102 | mc13783_write(MC13783_ADC0, MC13783_ADINC2 | MC13783_ADINC1 | | 126 | mc13783_write(MC13783_ADC0, MC13783_ADINC2 | MC13783_ADINC1); |
103 | MC13783_RTHEN | MC13783_CHRGICON); | 127 | |
104 | /* Enable ADC, set multi-channel mode */ | 128 | /* Enable ADC, set multi-channel mode */ |
105 | mc13783_write(MC13783_ADC1, MC13783_ADEN); | 129 | mc13783_write(MC13783_ADC1, MC13783_ADEN); |
106 | 130 | ||