diff options
Diffstat (limited to 'firmware/target/arm/imx233')
-rw-r--r-- | firmware/target/arm/imx233/clkctrl-imx233.c | 24 | ||||
-rw-r--r-- | firmware/target/arm/imx233/clkctrl-imx233.h | 16 | ||||
-rw-r--r-- | firmware/target/arm/imx233/dma-imx233.c | 133 | ||||
-rw-r--r-- | firmware/target/arm/imx233/dma-imx233.h | 161 | ||||
-rw-r--r-- | firmware/target/arm/imx233/mmc-imx233.c | 100 | ||||
-rw-r--r-- | firmware/target/arm/imx233/pinctrl-imx233.h | 16 | ||||
-rw-r--r-- | firmware/target/arm/imx233/sd-imx233.c | 14 | ||||
-rw-r--r-- | firmware/target/arm/imx233/ssp-imx233.c | 307 | ||||
-rw-r--r-- | firmware/target/arm/imx233/ssp-imx233.h | 162 | ||||
-rw-r--r-- | firmware/target/arm/imx233/system-imx233.c | 12 | ||||
-rw-r--r-- | firmware/target/arm/imx233/system-target.h | 4 | ||||
-rw-r--r-- | firmware/target/arm/imx233/usb-imx233.c | 76 |
12 files changed, 1025 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/clkctrl-imx233.c b/firmware/target/arm/imx233/clkctrl-imx233.c index 0b46a0e8db..7701b84c41 100644 --- a/firmware/target/arm/imx233/clkctrl-imx233.c +++ b/firmware/target/arm/imx233/clkctrl-imx233.c | |||
@@ -37,6 +37,7 @@ void imx233_enable_clock(enum imx233_clock_t clk, bool enable) | |||
37 | switch(clk) | 37 | switch(clk) |
38 | { | 38 | { |
39 | case CLK_PIX: REG = &HW_CLKCTRL_PIX; break; | 39 | case CLK_PIX: REG = &HW_CLKCTRL_PIX; break; |
40 | case CLK_SSP: REG = &HW_CLKCTRL_SSP; break; | ||
40 | default: return; | 41 | default: return; |
41 | } | 42 | } |
42 | 43 | ||
@@ -63,8 +64,30 @@ void imx233_set_clock_divisor(enum imx233_clock_t clk, int div) | |||
63 | __REG_SET(HW_CLKCTRL_PIX) = div; | 64 | __REG_SET(HW_CLKCTRL_PIX) = div; |
64 | while(HW_CLKCTRL_PIX & __CLK_BUSY); | 65 | while(HW_CLKCTRL_PIX & __CLK_BUSY); |
65 | break; | 66 | break; |
67 | case CLK_SSP: | ||
68 | __REG_CLR(HW_CLKCTRL_SSP) = (1 << 9) - 1; | ||
69 | __REG_SET(HW_CLKCTRL_SSP) = div; | ||
70 | while(HW_CLKCTRL_SSP & __CLK_BUSY); | ||
71 | break; | ||
72 | default: return; | ||
73 | } | ||
74 | } | ||
75 | |||
76 | void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv) | ||
77 | { | ||
78 | /* NOTE: HW_CLKCTRL_FRAC only support byte access ! */ | ||
79 | volatile uint8_t *REG; | ||
80 | switch(clk) | ||
81 | { | ||
82 | case CLK_PIX: REG = &HW_CLKCTRL_FRAC_PIX; break; | ||
83 | case CLK_IO: REG = &HW_CLKCTRL_FRAC_IO; break; | ||
66 | default: return; | 84 | default: return; |
67 | } | 85 | } |
86 | |||
87 | if(fracdiv != 0) | ||
88 | *REG = fracdiv; | ||
89 | else | ||
90 | *REG = HW_CLKCTRL_FRAC_XX__CLKGATEXX;; | ||
68 | } | 91 | } |
69 | 92 | ||
70 | void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass) | 93 | void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass) |
@@ -73,6 +96,7 @@ void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass) | |||
73 | switch(clk) | 96 | switch(clk) |
74 | { | 97 | { |
75 | case CLK_PIX: msk = HW_CLKCTRL_CLKSEQ__BYPASS_PIX; break; | 98 | case CLK_PIX: msk = HW_CLKCTRL_CLKSEQ__BYPASS_PIX; break; |
99 | case CLK_SSP: msk = HW_CLKCTRL_CLKSEQ__BYPASS_SSP; break; | ||
76 | default: return; | 100 | default: return; |
77 | } | 101 | } |
78 | 102 | ||
diff --git a/firmware/target/arm/imx233/clkctrl-imx233.h b/firmware/target/arm/imx233/clkctrl-imx233.h index ffc15c1043..1533b52cce 100644 --- a/firmware/target/arm/imx233/clkctrl-imx233.h +++ b/firmware/target/arm/imx233/clkctrl-imx233.h | |||
@@ -31,9 +31,20 @@ | |||
31 | #define HW_CLKCTRL_XTAL__TIMROT_CLK32K_GATE (1 << 26) | 31 | #define HW_CLKCTRL_XTAL__TIMROT_CLK32K_GATE (1 << 26) |
32 | 32 | ||
33 | #define HW_CLKCTRL_PIX (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x60)) | 33 | #define HW_CLKCTRL_PIX (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x60)) |
34 | #define HW_CLKCTRL_SSP (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x70)) | ||
34 | 35 | ||
35 | #define HW_CLKCTRL_CLKSEQ (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x110)) | 36 | #define HW_CLKCTRL_CLKSEQ (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x110)) |
36 | #define HW_CLKCTRL_CLKSEQ__BYPASS_PIX (1 << 1) | 37 | #define HW_CLKCTRL_CLKSEQ__BYPASS_PIX (1 << 1) |
38 | #define HW_CLKCTRL_CLKSEQ__BYPASS_SSP (1 << 5) | ||
39 | |||
40 | #define HW_CLKCTRL_FRAC (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xf0)) | ||
41 | #define HW_CLKCTRL_FRAC_CPU (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf0)) | ||
42 | #define HW_CLKCTRL_FRAC_EMI (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf1)) | ||
43 | #define HW_CLKCTRL_FRAC_PIX (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf2)) | ||
44 | #define HW_CLKCTRL_FRAC_IO (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf3)) | ||
45 | #define HW_CLKCTRL_FRAC_XX__XXDIV_BM 0x3f | ||
46 | #define HW_CLKCTRL_FRAC_XX__XX_STABLE (1 << 6) | ||
47 | #define HW_CLKCTRL_FRAC_XX__CLKGATEXX (1 << 7) | ||
37 | 48 | ||
38 | #define HW_CLKCTRL_RESET (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x120)) | 49 | #define HW_CLKCTRL_RESET (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x120)) |
39 | #define HW_CLKCTRL_RESET_CHIP 0x2 | 50 | #define HW_CLKCTRL_RESET_CHIP 0x2 |
@@ -42,11 +53,16 @@ | |||
42 | enum imx233_clock_t | 53 | enum imx233_clock_t |
43 | { | 54 | { |
44 | CLK_PIX, | 55 | CLK_PIX, |
56 | CLK_SSP, | ||
57 | CLK_IO, | ||
45 | }; | 58 | }; |
46 | 59 | ||
47 | void imx233_enable_timrot_xtal_clk32k(bool enable); | 60 | void imx233_enable_timrot_xtal_clk32k(bool enable); |
61 | /* only use it for non-fractional clocks (ie not for IO) */ | ||
48 | void imx233_enable_clock(enum imx233_clock_t clk, bool enable); | 62 | void imx233_enable_clock(enum imx233_clock_t clk, bool enable); |
49 | void imx233_set_clock_divisor(enum imx233_clock_t clk, int div); | 63 | void imx233_set_clock_divisor(enum imx233_clock_t clk, int div); |
64 | /* call with fracdiv=0 to disable it */ | ||
65 | void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv); | ||
50 | void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass); | 66 | void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass); |
51 | 67 | ||
52 | #endif /* CLKCTRL_IMX233_H */ | 68 | #endif /* CLKCTRL_IMX233_H */ |
diff --git a/firmware/target/arm/imx233/dma-imx233.c b/firmware/target/arm/imx233/dma-imx233.c new file mode 100644 index 0000000000..d75c334aeb --- /dev/null +++ b/firmware/target/arm/imx233/dma-imx233.c | |||
@@ -0,0 +1,133 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2011 by amaury Pouly | ||
11 | * | ||
12 | * Based on Rockbox iriver bootloader by Linus Nielsen Feltzing | ||
13 | * and the ipodlinux bootloader by Daniel Palffy and Bernard Leach | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #include "config.h" | ||
25 | #include "system.h" | ||
26 | #include "dma-imx233.h" | ||
27 | |||
28 | void imx233_dma_init(void) | ||
29 | { | ||
30 | /* Enable APHB and APBX */ | ||
31 | __REG_CLR(HW_APBH_CTRL0) = __BLOCK_CLKGATE | __BLOCK_SFTRST; | ||
32 | __REG_CLR(HW_APBX_CTRL0) = __BLOCK_CLKGATE | __BLOCK_SFTRST; | ||
33 | } | ||
34 | |||
35 | void imx233_dma_reset_channel(unsigned chan) | ||
36 | { | ||
37 | if(APB_IS_APBX_CHANNEL(chan)) | ||
38 | __REG_SET(HW_APBX_CHANNEL_CTRL) = | ||
39 | HW_APBX_CHANNEL_CTRL__RESET_CHANNEL(APB_GET_DMA_CHANNEL(chan)); | ||
40 | else | ||
41 | __REG_SET(HW_APBH_CTRL0) = | ||
42 | HW_APBH_CTRL0__RESET_CHANNEL(APB_GET_DMA_CHANNEL(chan)); | ||
43 | } | ||
44 | |||
45 | void imx233_dma_clkgate_channel(unsigned chan, bool enable_clock) | ||
46 | { | ||
47 | if(APB_IS_APBX_CHANNEL(chan)) | ||
48 | return; | ||
49 | if(enable_clock) | ||
50 | __REG_CLR(HW_APBH_CTRL0) = | ||
51 | HW_APBH_CTRL0__CLKGATE_CHANNEL(APB_GET_DMA_CHANNEL(chan)); | ||
52 | else | ||
53 | __REG_SET(HW_APBH_CTRL0) = | ||
54 | HW_APBH_CTRL0__CLKGATE_CHANNEL(APB_GET_DMA_CHANNEL(chan)); | ||
55 | } | ||
56 | |||
57 | void imx233_dma_enable_channel_interrupt(unsigned chan, bool enable) | ||
58 | { | ||
59 | volatile uint32_t *ptr; | ||
60 | uint32_t bm; | ||
61 | if(APB_IS_APBX_CHANNEL(chan)) | ||
62 | { | ||
63 | ptr = &HW_APBX_CTRL1; | ||
64 | bm = HW_APBX_CTRL1__CHx_CMDCMPLT_IRQ_EN(APB_GET_DMA_CHANNEL(chan)); | ||
65 | } | ||
66 | else | ||
67 | { | ||
68 | ptr = &HW_APBH_CTRL1;; | ||
69 | bm = HW_APBH_CTRL1__CHx_CMDCMPLT_IRQ_EN(APB_GET_DMA_CHANNEL(chan)); | ||
70 | } | ||
71 | |||
72 | if(enable) | ||
73 | { | ||
74 | __REG_SET(*ptr) = bm; | ||
75 | imx233_dma_clear_channel_interrupt(chan); | ||
76 | } | ||
77 | else | ||
78 | __REG_CLR(*ptr) = bm; | ||
79 | } | ||
80 | |||
81 | void imx233_dma_clear_channel_interrupt(unsigned chan) | ||
82 | { | ||
83 | if(APB_IS_APBX_CHANNEL(chan)) | ||
84 | { | ||
85 | __REG_CLR(HW_APBX_CTRL1) = | ||
86 | HW_APBX_CTRL1__CHx_CMDCMPLT_IRQ(APB_GET_DMA_CHANNEL(chan)); | ||
87 | __REG_CLR(HW_APBX_CTRL2) = | ||
88 | HW_APBX_CTRL2__CHx_ERROR_IRQ(APB_GET_DMA_CHANNEL(chan)); | ||
89 | } | ||
90 | else | ||
91 | { | ||
92 | __REG_CLR(HW_APBH_CTRL1) = | ||
93 | HW_APBH_CTRL1__CHx_CMDCMPLT_IRQ(APB_GET_DMA_CHANNEL(chan)); | ||
94 | __REG_CLR(HW_APBH_CTRL2) = | ||
95 | HW_APBH_CTRL2__CHx_ERROR_IRQ(APB_GET_DMA_CHANNEL(chan)); | ||
96 | } | ||
97 | } | ||
98 | |||
99 | bool imx233_dma_is_channel_error_irq(unsigned chan) | ||
100 | { | ||
101 | if(APB_IS_APBX_CHANNEL(chan)) | ||
102 | return !!(HW_APBX_CTRL2 & | ||
103 | HW_APBX_CTRL2__CHx_ERROR_IRQ(APB_GET_DMA_CHANNEL(chan))); | ||
104 | else | ||
105 | return !!(HW_APBH_CTRL2 & | ||
106 | HW_APBH_CTRL2__CHx_ERROR_IRQ(APB_GET_DMA_CHANNEL(chan))); | ||
107 | } | ||
108 | |||
109 | void imx233_dma_start_command(unsigned chan, struct apb_dma_command_t *cmd) | ||
110 | { | ||
111 | if(APB_IS_APBX_CHANNEL(chan)) | ||
112 | { | ||
113 | HW_APBX_CHx_NXTCMDAR(APB_GET_DMA_CHANNEL(chan)) = (uint32_t)cmd; | ||
114 | HW_APBX_CHx_SEMA(APB_GET_DMA_CHANNEL(chan)) = 1; | ||
115 | } | ||
116 | else | ||
117 | { | ||
118 | HW_APBH_CHx_NXTCMDAR(APB_GET_DMA_CHANNEL(chan)) = (uint32_t)cmd; | ||
119 | HW_APBH_CHx_SEMA(APB_GET_DMA_CHANNEL(chan)) = 1; | ||
120 | } | ||
121 | } | ||
122 | |||
123 | void imx233_dma_wait_completion(unsigned chan) | ||
124 | { | ||
125 | volatile uint32_t *sema; | ||
126 | if(APB_IS_APBX_CHANNEL(chan)) | ||
127 | sema = &HW_APBX_CHx_SEMA(APB_GET_DMA_CHANNEL(chan)); | ||
128 | else | ||
129 | sema = &HW_APBH_CHx_SEMA(APB_GET_DMA_CHANNEL(chan)); | ||
130 | |||
131 | while(*sema & HW_APB_CHx_SEMA__PHORE_BM) | ||
132 | ; | ||
133 | } | ||
diff --git a/firmware/target/arm/imx233/dma-imx233.h b/firmware/target/arm/imx233/dma-imx233.h new file mode 100644 index 0000000000..ce13aba89f --- /dev/null +++ b/firmware/target/arm/imx233/dma-imx233.h | |||
@@ -0,0 +1,161 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2011 by amaury Pouly | ||
11 | * | ||
12 | * Based on Rockbox iriver bootloader by Linus Nielsen Feltzing | ||
13 | * and the ipodlinux bootloader by Daniel Palffy and Bernard Leach | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __DMA_IMX233_H__ | ||
25 | #define __DMA_IMX233_H__ | ||
26 | |||
27 | #include "cpu.h" | ||
28 | #include "system.h" | ||
29 | #include "system-target.h" | ||
30 | |||
31 | /******** | ||
32 | * APHB * | ||
33 | ********/ | ||
34 | |||
35 | #define HW_APBH_BASE 0x80004000 | ||
36 | |||
37 | /* APHB channels */ | ||
38 | #define HW_APBH_SSP(ssp) ssp | ||
39 | |||
40 | #define HW_APBH_CTRL0 (*(volatile uint32_t *)(HW_APBH_BASE + 0x0)) | ||
41 | #define HW_APBH_CTRL0__FREEZE_CHANNEL(i) (1 << (i)) | ||
42 | #define HW_APBH_CTRL0__CLKGATE_CHANNEL(i) (1 << ((i) + 8)) | ||
43 | #define HW_APBH_CTRL0__RESET_CHANNEL(i) (1 << ((i) + 16)) | ||
44 | #define HW_APBH_CTRL0__APB_BURST4_EN (1 << 28) | ||
45 | #define HW_APBH_CTRL0__APB_BURST8_EN (1 << 29) | ||
46 | |||
47 | #define HW_APBH_CTRL1 (*(volatile uint32_t *)(HW_APBH_BASE + 0x10)) | ||
48 | #define HW_APBH_CTRL1__CHx_CMDCMPLT_IRQ(i) (1 << (i)) | ||
49 | #define HW_APBH_CTRL1__CHx_CMDCMPLT_IRQ_EN(i) (1 << ((i) + 16)) | ||
50 | |||
51 | #define HW_APBH_CTRL2 (*(volatile uint32_t *)(HW_APBH_BASE + 0x20)) | ||
52 | #define HW_APBH_CTRL2__CHx_ERROR_IRQ(i) (1 << (i)) | ||
53 | #define HW_APBH_CTRL2__CHx_ERROR_STATUS(i) (1 << ((i) + 16)) | ||
54 | |||
55 | #define HW_APBH_CHx_CURCMDAR(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x40 + 0x70 * (i))) | ||
56 | |||
57 | #define HW_APBH_CHx_NXTCMDAR(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x50 + 0x70 * (i))) | ||
58 | |||
59 | #define HW_APBH_CHx_CMD(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x60 + 0x70 * (i))) | ||
60 | |||
61 | #define HW_APBH_CHx_BAR(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x70 + 0x70 * (i))) | ||
62 | |||
63 | #define HW_APBH_CHx_SEMA(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x80 + 0x70 * (i))) | ||
64 | |||
65 | #define HW_APBH_CHx_DEBUG1(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x90 + 0x70 * (i))) | ||
66 | |||
67 | #define HW_APBH_CHx_DEBUG2(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0xa0 + 0x70 * (i))) | ||
68 | |||
69 | /******** | ||
70 | * APHX * | ||
71 | ********/ | ||
72 | |||
73 | /* APHX channels */ | ||
74 | #define HW_APBX_AUDIO_ADC 0 | ||
75 | #define HW_APBX_AUDIO_DAC 1 | ||
76 | |||
77 | #define HW_APBX_BASE 0x80024000 | ||
78 | |||
79 | #define HW_APBX_CTRL0 (*(volatile uint32_t *)(HW_APBX_BASE + 0x0)) | ||
80 | |||
81 | #define HW_APBX_CTRL1 (*(volatile uint32_t *)(HW_APBX_BASE + 0x10)) | ||
82 | #define HW_APBX_CTRL1__CHx_CMDCMPLT_IRQ(i) (1 << (i)) | ||
83 | #define HW_APBX_CTRL1__CHx_CMDCMPLT_IRQ_EN(i) (1 << ((i) + 16)) | ||
84 | |||
85 | #define HW_APBX_CTRL2 (*(volatile uint32_t *)(HW_APBX_BASE + 0x20)) | ||
86 | #define HW_APBX_CTRL2__CHx_ERROR_IRQ(i) (1 << (i)) | ||
87 | #define HW_APBX_CTRL2__CHx_ERROR_STATUS(i) (1 << ((i) + 16)) | ||
88 | |||
89 | #define HW_APBX_CHANNEL_CTRL (*(volatile uint32_t *)(HW_APBX_BASE + 0x30)) | ||
90 | #define HW_APBX_CHANNEL_CTRL__FREEZE_CHANNEL(i) (1 << (i)) | ||
91 | #define HW_APBX_CHANNEL_CTRL__RESET_CHANNEL(i) (1 << ((i) + 16)) | ||
92 | |||
93 | #define HW_APBX_CHx_CURCMDAR(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x100 + (i) * 0x70)) | ||
94 | |||
95 | #define HW_APBX_CHx_NXTCMDAR(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x110 + (i) * 0x70)) | ||
96 | |||
97 | #define HW_APBX_CHx_CMD(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x120 + (i) * 0x70)) | ||
98 | |||
99 | #define HW_APBX_CHx_BAR(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x130 + (i) * 0x70)) | ||
100 | |||
101 | #define HW_APBX_CHx_SEMA(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x140 + (i) * 0x70)) | ||
102 | |||
103 | #define HW_APBX_CHx_DEBUG1(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x150 + (i) * 0x70)) | ||
104 | |||
105 | #define HW_APBX_CHx_DEBUG2(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x160 + (i) * 0x70)) | ||
106 | |||
107 | /********** | ||
108 | * COMMON * | ||
109 | **********/ | ||
110 | |||
111 | struct apb_dma_command_t | ||
112 | { | ||
113 | struct apb_dma_command_t *next; | ||
114 | uint32_t cmd; | ||
115 | void *buffer; | ||
116 | /* PIO words follow */ | ||
117 | }; | ||
118 | |||
119 | #define APBH_DMA_CHANNEL(i) i | ||
120 | #define APBX_DMA_CHANNEL(i) ((i) | 0x10) | ||
121 | #define APB_IS_APBX_CHANNEL(x) ((x) & 0x10) | ||
122 | #define APB_GET_DMA_CHANNEL(x) ((x) & 0xf) | ||
123 | |||
124 | #define APB_SSP(ssp) APBH_DMA_CHANNEL(HW_APBH_SSP(ssp)) | ||
125 | #define APB_AUDIO_ADC APBX_DMA_CHANNEL(HW_APBX_AUDIO_ADC) | ||
126 | |||
127 | #define HW_APB_CHx_CMD__COMMAND_BM 0x3 | ||
128 | #define HW_APB_CHx_CMD__COMMAND__NO_XFER 0 | ||
129 | #define HW_APB_CHx_CMD__COMMAND__WRITE 1 | ||
130 | #define HW_APB_CHx_CMD__COMMAND__READ 2 | ||
131 | #define HW_APB_CHx_CMD__COMMAND__SENSE 3 | ||
132 | #define HW_APB_CHx_CMD__CHAIN (1 << 2) | ||
133 | #define HW_APB_CHx_CMD__IRQONCMPLT (1 << 3) | ||
134 | /* those two are only available on APHB */ | ||
135 | #define HW_APBH_CHx_CMD__NANDLOCK (1 << 4) | ||
136 | #define HW_APBH_CHx_CMD__NANDWAIT4READY (1 << 5) | ||
137 | #define HW_APB_CHx_CMD__SEMAPHORE (1 << 6) | ||
138 | #define HW_APB_CHx_CMD__WAIT4ENDCMD (1 << 7) | ||
139 | #define HW_APB_CHx_CMD__HALTONTERMINATE (1 << 8) | ||
140 | #define HW_APB_CHx_CMD__CMDWORDS_BM 0xf000 | ||
141 | #define HW_APB_CHx_CMD__CMDWORDS_BP 12 | ||
142 | #define HW_APB_CHx_CMD__XFER_COUNT_BM 0xffff0000 | ||
143 | #define HW_APB_CHx_CMD__XFER_COUNT_BP 16 | ||
144 | |||
145 | #define HW_APB_CHx_SEMA__PHORE_BM 0xff0000 | ||
146 | #define HW_APB_CHx_SEMA__PHORE_BP 16 | ||
147 | |||
148 | void imx233_dma_init(void); | ||
149 | void imx233_dma_reset_channel(unsigned chan); | ||
150 | /* only apbh channel have clkgate control */ | ||
151 | void imx233_dma_clkgate_channel(unsigned chan, bool enable_clock); | ||
152 | |||
153 | void imx233_dma_enable_channel_interrupt(unsigned chan, bool enable); | ||
154 | /* clear both channel complete and error bits */ | ||
155 | void imx233_dma_clear_channel_interrupt(unsigned chan); | ||
156 | bool imx233_dma_is_channel_error_irq(unsigned chan); | ||
157 | /* assume no command is in progress */ | ||
158 | void imx233_dma_start_command(unsigned chan, struct apb_dma_command_t *cmd); | ||
159 | void imx233_dma_wait_completion(unsigned chan); | ||
160 | |||
161 | #endif // __DMA_IMX233_H__ | ||
diff --git a/firmware/target/arm/imx233/mmc-imx233.c b/firmware/target/arm/imx233/mmc-imx233.c new file mode 100644 index 0000000000..f56ff3725c --- /dev/null +++ b/firmware/target/arm/imx233/mmc-imx233.c | |||
@@ -0,0 +1,100 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2011 by Amaury Pouly | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include "config.h" | ||
22 | #include "system.h" | ||
23 | #include "mmc.h" | ||
24 | #include "sdmmc.h" | ||
25 | #include "ssp-imx233.h" | ||
26 | #include "pinctrl-imx233.h" | ||
27 | #include "button-target.h" | ||
28 | |||
29 | #ifdef SANSA_FUZEPLUS | ||
30 | #define MMC_SSP 2 | ||
31 | #else | ||
32 | #error You need to configure the ssp to use | ||
33 | #endif | ||
34 | |||
35 | int mmc_init(void) | ||
36 | { | ||
37 | imx233_ssp_start(MMC_SSP); | ||
38 | imx233_ssp_softreset(MMC_SSP); | ||
39 | imx233_ssp_set_mode(MMC_SSP, HW_SSP_CTRL1__SSP_MODE__SD_MMC); | ||
40 | #ifdef SANSA_FUZEPLUS | ||
41 | /** Sansa Fuze+ has an internal eMMC 8-bit wide flash, power gate is pin PWM3 */ | ||
42 | imx233_set_pin_function(1, 29, PINCTRL_FUNCTION_GPIO); | ||
43 | imx233_enable_gpio_output(1, 29, true); | ||
44 | imx233_set_gpio_output(1, 29, false); | ||
45 | |||
46 | imx233_ssp_setup_ssp2_sd_mmc_pins(true, 8, PINCTRL_DRIVE_8mA); | ||
47 | #endif | ||
48 | /* SSPCLK @ 120MHz | ||
49 | * gives bitrate of 120 / 100 / 3 = 400kHz */ | ||
50 | imx233_ssp_set_timings(MMC_SSP, 100, 2); | ||
51 | imx233_ssp_set_timeout(MMC_SSP, 0xffff); | ||
52 | imx233_ssp_sd_mmc_power_up_sequence(MMC_SSP); | ||
53 | /* go to idle state */ | ||
54 | int ret = imx233_ssp_sd_mmc_transfer(MMC_SSP, SD_GO_IDLE_STATE, 0, SSP_NO_RESP, NULL, 0, false, NULL); | ||
55 | if(ret != 0) | ||
56 | return -1; | ||
57 | /* send op cond until the card respond with busy bit set; it must complete within 1sec */ | ||
58 | unsigned timeout = current_tick + HZ; | ||
59 | do | ||
60 | { | ||
61 | uint32_t ocr; | ||
62 | ret = imx233_ssp_sd_mmc_transfer(MMC_SSP, 1, 0x40ff8000, SSP_SHORT_RESP, NULL, 0, false, &ocr); | ||
63 | if(ret == 0 && ocr & (1 << 31)) | ||
64 | break; | ||
65 | }while(!TIME_AFTER(current_tick, timeout)); | ||
66 | |||
67 | if(ret != 0) | ||
68 | return -2; | ||
69 | |||
70 | uint32_t cid[4]; | ||
71 | ret = imx233_ssp_sd_mmc_transfer(MMC_SSP, 2, 0, SSP_LONG_RESP, NULL, 0, false, cid); | ||
72 | if(ret != 0) | ||
73 | return -3; | ||
74 | |||
75 | return 0; | ||
76 | } | ||
77 | |||
78 | int mmc_num_drives(int first_drive) | ||
79 | { | ||
80 | (void) first_drive; | ||
81 | return 1; | ||
82 | } | ||
83 | |||
84 | int mmc_read_sectors(IF_MD2(int drive,) unsigned long start, int count, void* buf) | ||
85 | { | ||
86 | IF_MD((void) drive); | ||
87 | (void) start; | ||
88 | (void) count; | ||
89 | (void) buf; | ||
90 | return -1; | ||
91 | } | ||
92 | |||
93 | int mmc_write_sectors(IF_MD2(int drive,) unsigned long start, int count, const void* buf) | ||
94 | { | ||
95 | IF_MD((void) drive); | ||
96 | (void) start; | ||
97 | (void) count; | ||
98 | (void) buf; | ||
99 | return -1; | ||
100 | } | ||
diff --git a/firmware/target/arm/imx233/pinctrl-imx233.h b/firmware/target/arm/imx233/pinctrl-imx233.h index 291b5c8ff7..4e3a9a035e 100644 --- a/firmware/target/arm/imx233/pinctrl-imx233.h +++ b/firmware/target/arm/imx233/pinctrl-imx233.h | |||
@@ -106,4 +106,20 @@ static inline void imx233_set_pin_function(unsigned bank, unsigned pin, unsigned | |||
106 | __REG_SET(HW_PINCTRL_MUXSEL(2 * bank + pin / 16)) = function << (2 * (pin % 16)); | 106 | __REG_SET(HW_PINCTRL_MUXSEL(2 * bank + pin / 16)) = function << (2 * (pin % 16)); |
107 | } | 107 | } |
108 | 108 | ||
109 | static inline void imx233_enable_pin_pullup(unsigned bank, unsigned pin, bool enable) | ||
110 | { | ||
111 | if(enable) | ||
112 | __REG_SET(HW_PINCTRL_PULL(bank)) = 1 << pin; | ||
113 | else | ||
114 | __REG_CLR(HW_PINCTRL_PULL(bank)) = 1 << pin; | ||
115 | } | ||
116 | |||
117 | static inline void imx233_enable_pin_pullup_mask(unsigned bank, uint32_t pin_msk, bool enable) | ||
118 | { | ||
119 | if(enable) | ||
120 | __REG_SET(HW_PINCTRL_PULL(bank)) = pin_msk; | ||
121 | else | ||
122 | __REG_CLR(HW_PINCTRL_PULL(bank)) = pin_msk; | ||
123 | } | ||
124 | |||
109 | #endif /* __PINCTRL_IMX233_H__ */ | 125 | #endif /* __PINCTRL_IMX233_H__ */ |
diff --git a/firmware/target/arm/imx233/sd-imx233.c b/firmware/target/arm/imx233/sd-imx233.c index eec1ce14db..6f30c7a3c6 100644 --- a/firmware/target/arm/imx233/sd-imx233.c +++ b/firmware/target/arm/imx233/sd-imx233.c | |||
@@ -18,7 +18,10 @@ | |||
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | #include "config.h" | ||
22 | #include "system.h" | ||
21 | #include "sd.h" | 23 | #include "sd.h" |
24 | #include "sdmmc.h" | ||
22 | 25 | ||
23 | int sd_init(void) | 26 | int sd_init(void) |
24 | { | 27 | { |
@@ -45,4 +48,15 @@ int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count, | |||
45 | return -1; | 48 | return -1; |
46 | } | 49 | } |
47 | 50 | ||
51 | tCardInfo *card_get_info_target(int card_no) | ||
52 | { | ||
53 | (void)card_no; | ||
54 | return NULL; | ||
55 | } | ||
56 | |||
57 | int sd_num_drives(int first_drive) | ||
58 | { | ||
59 | (void) first_drive; | ||
60 | return 0; | ||
61 | } | ||
48 | 62 | ||
diff --git a/firmware/target/arm/imx233/ssp-imx233.c b/firmware/target/arm/imx233/ssp-imx233.c new file mode 100644 index 0000000000..c6be869ce6 --- /dev/null +++ b/firmware/target/arm/imx233/ssp-imx233.c | |||
@@ -0,0 +1,307 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2011 by amaury Pouly | ||
11 | * | ||
12 | * Based on Rockbox iriver bootloader by Linus Nielsen Feltzing | ||
13 | * and the ipodlinux bootloader by Daniel Palffy and Bernard Leach | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #include "system.h" | ||
25 | #include "kernel.h" | ||
26 | #include "ssp-imx233.h" | ||
27 | #include "clkctrl-imx233.h" | ||
28 | #include "pinctrl-imx233.h" | ||
29 | #include "dma-imx233.h" | ||
30 | |||
31 | /* Used for DMA */ | ||
32 | struct ssp_dma_command_t | ||
33 | { | ||
34 | struct apb_dma_command_t dma; | ||
35 | /* PIO words */ | ||
36 | uint32_t ctrl0; | ||
37 | uint32_t cmd0; | ||
38 | uint32_t cmd1; | ||
39 | }; | ||
40 | |||
41 | static int ssp_in_use = 0; | ||
42 | static struct mutex ssp_mutex[2]; | ||
43 | static struct semaphore ssp_sema[2]; | ||
44 | static struct ssp_dma_command_t ssp_dma_cmd[2]; | ||
45 | |||
46 | void INT_SSP(int ssp) | ||
47 | { | ||
48 | /* reset dma channel on error */ | ||
49 | if(imx233_dma_is_channel_error_irq(APB_SSP(ssp))) | ||
50 | imx233_dma_reset_channel(APB_SSP(ssp)); | ||
51 | /* clear irq flags */ | ||
52 | imx233_dma_clear_channel_interrupt(APB_SSP(ssp)); | ||
53 | semaphore_release(&ssp_sema[ssp - 1]); | ||
54 | } | ||
55 | |||
56 | void INT_SSP1_DMA(void) | ||
57 | { | ||
58 | INT_SSP(1); | ||
59 | } | ||
60 | |||
61 | void INT_SSP2_DMA(void) | ||
62 | { | ||
63 | INT_SSP(2); | ||
64 | } | ||
65 | |||
66 | void INT_SSP1_ERROR(void) | ||
67 | { | ||
68 | panicf("ssp1 error"); | ||
69 | } | ||
70 | |||
71 | void INT_SSP2_ERROR(void) | ||
72 | { | ||
73 | panicf("ssp2 error"); | ||
74 | } | ||
75 | |||
76 | void imx233_ssp_init(void) | ||
77 | { | ||
78 | /* power down */ | ||
79 | __REG_SET(HW_SSP_CTRL0(1)) = __BLOCK_CLKGATE; | ||
80 | __REG_SET(HW_SSP_CTRL0(2)) = __BLOCK_CLKGATE; | ||
81 | |||
82 | ssp_in_use = 0; | ||
83 | semaphore_init(&ssp_sema[0], 1, 0); | ||
84 | semaphore_init(&ssp_sema[1], 1, 0); | ||
85 | mutex_init(&ssp_mutex[0]); | ||
86 | mutex_init(&ssp_mutex[1]); | ||
87 | } | ||
88 | |||
89 | void imx233_ssp_start(int ssp) | ||
90 | { | ||
91 | /* Gate block */ | ||
92 | __REG_CLR(HW_SSP_CTRL0(ssp)) = __BLOCK_CLKGATE; | ||
93 | while(HW_SSP_CTRL0(ssp) & __BLOCK_CLKGATE); | ||
94 | /* Gate dma channel */ | ||
95 | imx233_dma_clkgate_channel(APB_SSP(ssp), true); | ||
96 | /* If first block to start, start SSP clock */ | ||
97 | if(ssp_in_use == 0) | ||
98 | { | ||
99 | /* fracdiv = 18 => clk_io = pll = 480Mhz | ||
100 | * intdiv = 4 => clk_ssp = 120Mhz */ | ||
101 | imx233_set_fractional_divisor(CLK_IO, 18); | ||
102 | imx233_enable_clock(CLK_SSP, false); | ||
103 | imx233_set_clock_divisor(CLK_SSP, 4); | ||
104 | imx233_set_bypass_pll(CLK_SSP, false); /* use IO */ | ||
105 | imx233_enable_clock(CLK_SSP, true); | ||
106 | } | ||
107 | ssp_in_use++; | ||
108 | } | ||
109 | |||
110 | void imx233_ssp_stop(int ssp) | ||
111 | { | ||
112 | /* Gate off */ | ||
113 | __REG_SET(HW_SSP_CTRL0(ssp)) = __BLOCK_CLKGATE; | ||
114 | /* Gate off dma */ | ||
115 | imx233_dma_clkgate_channel(APB_SSP(ssp), false); | ||
116 | /* If last block to stop, stop SSP clock */ | ||
117 | ssp_in_use--; | ||
118 | if(ssp_in_use == 0) | ||
119 | { | ||
120 | imx233_enable_clock(CLK_SSP, false); | ||
121 | imx233_set_fractional_divisor(CLK_IO, 0); | ||
122 | } | ||
123 | } | ||
124 | |||
125 | void imx233_ssp_softreset(int ssp) | ||
126 | { | ||
127 | imx233_reset_block(&HW_SSP_CTRL0(ssp)); | ||
128 | } | ||
129 | |||
130 | void imx233_ssp_set_timings(int ssp, int divide, int rate) | ||
131 | { | ||
132 | __REG_CLR(HW_SSP_TIMING(ssp)) = | ||
133 | HW_SSP_TIMING__CLOCK_DIVIDE_BM | HW_SSP_TIMING__CLOCK_RATE_BM; | ||
134 | __REG_SET(HW_SSP_TIMING(ssp)) = | ||
135 | divide << HW_SSP_TIMING__CLOCK_DIVIDE_BP | rate; | ||
136 | } | ||
137 | |||
138 | void imx233_ssp_set_timeout(int ssp, int timeout) | ||
139 | { | ||
140 | __REG_CLR(HW_SSP_TIMING(ssp)) = HW_SSP_TIMING__CLOCK_TIMEOUT_BM; | ||
141 | __REG_SET(HW_SSP_TIMING(ssp)) = | ||
142 | timeout << HW_SSP_TIMING__CLOCK_TIMEOUT_BP; | ||
143 | } | ||
144 | |||
145 | #if 0 | ||
146 | static void setup_ssp_sd_pins(int ssp) | ||
147 | { | ||
148 | imx233_set_pin_function(1, 29, PINCTRL_FUNCTION_GPIO); | ||
149 | imx233_enable_gpio_output(1, 29, true); | ||
150 | imx233_set_gpio_output(1, 29, false); | ||
151 | |||
152 | if(ssp == 1) | ||
153 | { | ||
154 | /* SSP_SCK: drive 8mA */ | ||
155 | imx233_set_pin_drive_strength(2, 6, PINCTRL_DRIVE_8mA); | ||
156 | /* SSP_{SCK,DATA{3,2,1,0},DETECT,CMD} */ | ||
157 | imx233_set_pin_function(2, 6, PINCTRL_FUNCTION_MAIN); | ||
158 | imx233_set_pin_function(2, 5, PINCTRL_FUNCTION_MAIN); | ||
159 | imx233_set_pin_function(2, 4, PINCTRL_FUNCTION_MAIN); | ||
160 | imx233_set_pin_function(2, 3, PINCTRL_FUNCTION_MAIN); | ||
161 | imx233_set_pin_function(2, 2, PINCTRL_FUNCTION_MAIN); | ||
162 | imx233_set_pin_function(2, 1, PINCTRL_FUNCTION_MAIN); | ||
163 | imx233_set_pin_function(2, 0, PINCTRL_FUNCTION_MAIN); | ||
164 | /* SSP_CMD: pullup */ | ||
165 | imx233_enable_pin_pullup(2, 0, true); | ||
166 | imx233_enable_pin_pullup(2, 2, true); | ||
167 | imx233_enable_pin_pullup(2, 3, true); | ||
168 | imx233_enable_pin_pullup(2, 4, true); | ||
169 | imx233_enable_pin_pullup(2, 5, true); | ||
170 | } | ||
171 | else | ||
172 | { | ||
173 | |||
174 | } | ||
175 | } | ||
176 | #endif | ||
177 | |||
178 | void imx233_ssp_setup_ssp2_sd_mmc_pins(bool enable_pullups, unsigned bus_width, | ||
179 | unsigned drive_strength) | ||
180 | { | ||
181 | /* SSP_{CMD,SCK} */ | ||
182 | imx233_set_pin_drive_strength(0, 20, drive_strength); | ||
183 | imx233_set_pin_drive_strength(0, 24, drive_strength); | ||
184 | imx233_set_pin_function(0, 20, PINCTRL_FUNCTION_ALT2); | ||
185 | imx233_set_pin_function(0, 24, PINCTRL_FUNCTION_ALT2); | ||
186 | imx233_enable_pin_pullup(0, 20, enable_pullups); | ||
187 | /* SSP_DATA{0-7}*/ | ||
188 | imx233_set_pin_drive_strength(0, 0, drive_strength); | ||
189 | imx233_set_pin_function(0, 0, PINCTRL_FUNCTION_ALT2); | ||
190 | imx233_enable_pin_pullup(0, 0, enable_pullups); | ||
191 | |||
192 | if(bus_width >= 4) | ||
193 | { | ||
194 | imx233_set_pin_drive_strength(0, 1, drive_strength); | ||
195 | imx233_set_pin_drive_strength(0, 2, drive_strength); | ||
196 | imx233_set_pin_drive_strength(0, 3, drive_strength); | ||
197 | imx233_set_pin_function(0, 1, PINCTRL_FUNCTION_ALT2); | ||
198 | imx233_set_pin_function(0, 2, PINCTRL_FUNCTION_ALT2); | ||
199 | imx233_set_pin_function(0, 3, PINCTRL_FUNCTION_ALT2); | ||
200 | imx233_enable_pin_pullup(0, 1, enable_pullups); | ||
201 | imx233_enable_pin_pullup(0, 2, enable_pullups); | ||
202 | imx233_enable_pin_pullup(0, 3, enable_pullups); | ||
203 | } | ||
204 | if(bus_width >= 8) | ||
205 | { | ||
206 | imx233_set_pin_drive_strength(0, 4, drive_strength); | ||
207 | imx233_set_pin_drive_strength(0, 5, drive_strength); | ||
208 | imx233_set_pin_drive_strength(0, 6, drive_strength); | ||
209 | imx233_set_pin_drive_strength(0, 7, drive_strength); | ||
210 | imx233_set_pin_function(0, 4, PINCTRL_FUNCTION_ALT2); | ||
211 | imx233_set_pin_function(0, 5, PINCTRL_FUNCTION_ALT2); | ||
212 | imx233_set_pin_function(0, 6, PINCTRL_FUNCTION_ALT2); | ||
213 | imx233_set_pin_function(0, 7, PINCTRL_FUNCTION_ALT2); | ||
214 | imx233_enable_pin_pullup(0, 4, enable_pullups); | ||
215 | imx233_enable_pin_pullup(0, 5, enable_pullups); | ||
216 | imx233_enable_pin_pullup(0, 6, enable_pullups); | ||
217 | imx233_enable_pin_pullup(0, 7, enable_pullups); | ||
218 | } | ||
219 | |||
220 | imx233_enable_gpio_output_mask(0, 0x11000ff, false); | ||
221 | imx233_set_gpio_output_mask(0, 0x11000ff, false); | ||
222 | } | ||
223 | |||
224 | void imx233_ssp_set_mode(int ssp, unsigned mode) | ||
225 | { | ||
226 | switch(mode) | ||
227 | { | ||
228 | case HW_SSP_CTRL1__SSP_MODE__SD_MMC: | ||
229 | /* clear mode and word length */ | ||
230 | __REG_CLR(HW_SSP_CTRL1(ssp)) = | ||
231 | HW_SSP_CTRL1__SSP_MODE_BM | HW_SSP_CTRL1__WORD_LENGTH_BM; | ||
232 | /* set mode, set word length to 8-bit, polarity and enable dma */ | ||
233 | __REG_SET(HW_SSP_CTRL1(ssp)) = mode | | ||
234 | HW_SSP_CTRL1__WORD_LENGTH__EIGHT_BITS << HW_SSP_CTRL1__WORD_LENGTH_BP | | ||
235 | HW_SSP_CTRL1__POLARITY | HW_SSP_CTRL1__DMA_ENABLE; | ||
236 | break; | ||
237 | default: return; | ||
238 | } | ||
239 | } | ||
240 | |||
241 | enum imx233_ssp_error_t imx233_ssp_sd_mmc_transfer(int ssp, uint8_t cmd, uint32_t cmd_arg, | ||
242 | enum imx233_ssp_resp_t resp, void *buffer, int xfer_size, bool read, uint32_t *resp_ptr) | ||
243 | { | ||
244 | mutex_lock(&ssp_mutex[ssp - 1]); | ||
245 | /* Enable all interrupts */ | ||
246 | imx233_enable_interrupt(INT_SRC_SSP_DMA(ssp), true); | ||
247 | imx233_dma_enable_channel_interrupt(APB_SSP(ssp), true); | ||
248 | /* Assume only one block so ignore block_count and block_size */ | ||
249 | ssp_dma_cmd[ssp - 1].cmd0 = cmd | HW_SSP_CMD0__APPEND_8CYC; | ||
250 | ssp_dma_cmd[ssp - 1].cmd1 = cmd_arg; | ||
251 | /* setup all flags and run */ | ||
252 | ssp_dma_cmd[ssp - 1].ctrl0 = xfer_size | HW_SSP_CTRL0__ENABLE | | ||
253 | HW_SSP_CTRL0__IGNORE_CRC | | ||
254 | (resp != SSP_NO_RESP ? HW_SSP_CTRL0__GET_RESP | HW_SSP_CTRL0__WAIT_FOR_IRQ : 0) | | ||
255 | (resp == SSP_LONG_RESP ? HW_SSP_CTRL0__LONG_RESP : 0) | | ||
256 | HW_SSP_CTRL0__BUS_WIDTH__ONE_BIT << HW_SSP_CTRL0__BUS_WIDTH_BP | | ||
257 | (buffer ? HW_SSP_CTRL0__DATA_XFER : 0) | | ||
258 | (read ? HW_SSP_CTRL0__READ : 0); | ||
259 | /* setup the dma parameters */ | ||
260 | ssp_dma_cmd[ssp - 1].dma.buffer = buffer; | ||
261 | ssp_dma_cmd[ssp - 1].dma.next = NULL; | ||
262 | ssp_dma_cmd[ssp - 1].dma.cmd = | ||
263 | (buffer == NULL ? HW_APB_CHx_CMD__COMMAND__NO_XFER : | ||
264 | read ? HW_APB_CHx_CMD__COMMAND__WRITE : HW_APB_CHx_CMD__COMMAND__READ) | | ||
265 | HW_APB_CHx_CMD__IRQONCMPLT | HW_APB_CHx_CMD__SEMAPHORE | | ||
266 | HW_APB_CHx_CMD__WAIT4ENDCMD | HW_APB_CHx_CMD__HALTONTERMINATE | | ||
267 | (3 << HW_APB_CHx_CMD__CMDWORDS_BP) | | ||
268 | (xfer_size << HW_APB_CHx_CMD__XFER_COUNT_BP); | ||
269 | |||
270 | imx233_dma_start_command(APB_SSP(ssp), &ssp_dma_cmd[ssp - 1].dma); | ||
271 | |||
272 | /* the SSP hardware already has a timeout but we never know; 1 sec is a maximum | ||
273 | * for all operations */ | ||
274 | enum imx233_ssp_error_t ret; | ||
275 | |||
276 | if(semaphore_wait(&ssp_sema[ssp - 1], HZ) == OBJ_WAIT_TIMEDOUT) | ||
277 | ret = SSP_TIMEOUT; | ||
278 | else if((HW_SSP_CTRL1(ssp) & HW_SSP_CTRL1__ALL_IRQ) == 0) | ||
279 | ret = SSP_SUCCESS; | ||
280 | else if(HW_SSP_CTRL1(ssp) & (HW_SSP_CTRL1__RESP_TIMEOUT_IRQ | | ||
281 | HW_SSP_CTRL1__DATA_TIMEOUT_IRQ | HW_SSP_CTRL1__RECV_TIMEOUT_IRQ)) | ||
282 | ret = SSP_TIMEOUT; | ||
283 | else | ||
284 | ret = SSP_ERROR; | ||
285 | |||
286 | if(ret == SSP_SUCCESS && resp_ptr != NULL) | ||
287 | { | ||
288 | if(resp != SSP_NO_RESP) | ||
289 | *resp_ptr++ = HW_SSP_SDRESP0(ssp); | ||
290 | if(resp == SSP_LONG_RESP) | ||
291 | { | ||
292 | *resp_ptr++ = HW_SSP_SDRESP1(ssp); | ||
293 | *resp_ptr++ = HW_SSP_SDRESP2(ssp); | ||
294 | *resp_ptr++ = HW_SSP_SDRESP3(ssp); | ||
295 | } | ||
296 | } | ||
297 | mutex_unlock(&ssp_mutex[ssp - 1]); | ||
298 | return ret; | ||
299 | } | ||
300 | |||
301 | void imx233_ssp_sd_mmc_power_up_sequence(int ssp) | ||
302 | { | ||
303 | __REG_CLR(HW_SSP_CMD0(ssp)) = HW_SSP_CMD0__SLOW_CLKING_EN; | ||
304 | __REG_SET(HW_SSP_CMD0(ssp)) = HW_SSP_CMD0__CONT_CLKING_EN; | ||
305 | mdelay(1); | ||
306 | __REG_CLR(HW_SSP_CMD0(ssp)) = HW_SSP_CMD0__CONT_CLKING_EN; | ||
307 | } | ||
diff --git a/firmware/target/arm/imx233/ssp-imx233.h b/firmware/target/arm/imx233/ssp-imx233.h new file mode 100644 index 0000000000..e9bdf62b27 --- /dev/null +++ b/firmware/target/arm/imx233/ssp-imx233.h | |||
@@ -0,0 +1,162 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2011 by amaury Pouly | ||
11 | * | ||
12 | * Based on Rockbox iriver bootloader by Linus Nielsen Feltzing | ||
13 | * and the ipodlinux bootloader by Daniel Palffy and Bernard Leach | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __SSP_IMX233_H__ | ||
25 | #define __SSP_IMX233_H__ | ||
26 | |||
27 | #include "cpu.h" | ||
28 | #include "system.h" | ||
29 | #include "system-target.h" | ||
30 | |||
31 | /* ssp can value 1 or 2 */ | ||
32 | #define __SSP_SELECT(ssp, ssp1, ssp2) ((ssp) == 1 ? (ssp1) : (ssp2)) | ||
33 | |||
34 | #define INT_SRC_SSP_DMA(ssp) __SSP_SELECT(ssp, INT_SRC_SSP1_DMA, INT_SRC_SSP2_DMA) | ||
35 | #define INT_SRC_SSP_ERROR(ssp) __SSP_SELECT(ssp, INT_SRC_SSP1_ERROR, INT_SRC_SSP2_ERROR) | ||
36 | |||
37 | #define HW_SSP1_BASE 0x80010000 | ||
38 | #define HW_SSP2_BASE 0x80034000 | ||
39 | |||
40 | #define HW_SSP_BASE(ssp) __SSP_SELECT(ssp, HW_SSP1_BASE, HW_SSP2_BASE) | ||
41 | |||
42 | #define HW_SSP_CTRL0(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x0)) | ||
43 | #define HW_SSP_CTRL0__RUN (1 << 29) | ||
44 | #define HW_SSP_CTRL0__SDIO_IRQ_CHECK (1 << 28) | ||
45 | #define HW_SSP_CTRL0__LOCK_CS (1 << 27) | ||
46 | #define HW_SSP_CTRL0__IGNORE_CRC (1 << 26) | ||
47 | #define HW_SSP_CTRL0__READ (1 << 25) | ||
48 | #define HW_SSP_CTRL0__DATA_XFER (1 << 24) | ||
49 | #define HW_SSP_CTRL0__BUS_WIDTH_BM (3 << 22) | ||
50 | #define HW_SSP_CTRL0__BUS_WIDTH_BP 22 | ||
51 | #define HW_SSP_CTRL0__BUS_WIDTH__ONE_BIT 0 | ||
52 | #define HW_SSP_CTRL0__BUS_WIDTH__FOUR_BIT 1 | ||
53 | #define HW_SSP_CTRL0__BUS_WIDTH__EIGHT_BIT 2 | ||
54 | #define HW_SSP_CTRL0__WAIT_FOR_IRQ (1 << 21) | ||
55 | #define HW_SSP_CTRL0__WAIT_FOR_CMD (1 << 20) | ||
56 | #define HW_SSP_CTRL0__LONG_RESP (1 << 19) | ||
57 | #define HW_SSP_CTRL0__CHECK_RESP (1 << 18) | ||
58 | #define HW_SSP_CTRL0__GET_RESP (1 << 17) | ||
59 | #define HW_SSP_CTRL0__ENABLE (1 << 16) | ||
60 | #define HW_SSP_CTRL0__XFER_COUNT_BM 0xffff | ||
61 | |||
62 | |||
63 | #define HW_SSP_CMD0(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x10)) | ||
64 | #define HW_SSP_CMD0__SLOW_CLKING_EN (1 << 22) | ||
65 | #define HW_SSP_CMD0__CONT_CLKING_EN (1 << 21) | ||
66 | #define HW_SSP_CMD0__APPEND_8CYC (1 << 20) | ||
67 | #define HW_SSP_CMD0__BLOCK_SIZE_BM (0xf << 16) | ||
68 | #define HW_SSP_CMD0__BLOCK_SIZE_BP 16 | ||
69 | #define HW_SSP_CMD0__BLOCK_COUNT_BM (0xff << 8) | ||
70 | #define HW_SSP_CMD0__BLOCK_COUNT_BP 16 | ||
71 | #define HW_SSP_CMD0__CMD_BM 0xff | ||
72 | |||
73 | #define HW_SSP_CMD1(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x20)) | ||
74 | |||
75 | #define HW_SSP_TIMING(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x50)) | ||
76 | #define HW_SSP_TIMING__CLOCK_TIMEOUT_BM 0xffff0000 | ||
77 | #define HW_SSP_TIMING__CLOCK_TIMEOUT_BP 16 | ||
78 | #define HW_SSP_TIMING__CLOCK_DIVIDE_BM 0xff00 | ||
79 | #define HW_SSP_TIMING__CLOCK_DIVIDE_BP 8 | ||
80 | #define HW_SSP_TIMING__CLOCK_RATE_BM 0xff | ||
81 | |||
82 | #define HW_SSP_CTRL1(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x60)) | ||
83 | #define HW_SSP_CTRL1__SDIO_IRQ (1 << 31) | ||
84 | #define HW_SSP_CTRL1__SDIO_IRQ_EN (1 << 30) | ||
85 | #define HW_SSP_CTRL1__RESP_ERR_IRQ (1 << 29) | ||
86 | #define HW_SSP_CTRL1__RESP_ERR_IRQ_EN (1 << 28) | ||
87 | #define HW_SSP_CTRL1__RESP_TIMEOUT_IRQ (1 << 27) | ||
88 | #define HW_SSP_CTRL1__RESP_TIMEOUT_IRQ_EN (1 << 26) | ||
89 | #define HW_SSP_CTRL1__DATA_TIMEOUT_IRQ (1 << 25) | ||
90 | #define HW_SSP_CTRL1__DATA_TIMEOUT_IRQ_EN (1 << 24) | ||
91 | #define HW_SSP_CTRL1__DATA_CRC_IRQ (1 << 23) | ||
92 | #define HW_SSP_CTRL1__DATA_CRC_IRQ_EN (1 << 22) | ||
93 | #define HW_SSP_CTRL1__FIFO_UNDERRUN_IRQ (1 << 21) | ||
94 | #define HW_SSP_CTRL1__FIFO_UNDERRUN_IRQ_EN (1 << 20) | ||
95 | #define HW_SSP_CTRL1__RECV_TIMEOUT_IRQ (1 << 17) | ||
96 | #define HW_SSP_CTRL1__RECV_TIMEOUT_IRQ_EN (1 << 16) | ||
97 | #define HW_SSP_CTRL1__FIFO_OVERRUN_IRQ (1 << 15) | ||
98 | #define HW_SSP_CTRL1__FIFO_OVERRUN_IRQ_EN (1 << 14) | ||
99 | #define HW_SSP_CTRL1__DMA_ENABLE (1 << 13) | ||
100 | #define HW_SSP_CTRL1__SLAVE_OUT_DISABLE (1 << 11) | ||
101 | #define HW_SSP_CTRL1__PHASE (1 << 10) | ||
102 | #define HW_SSP_CTRL1__POLARITY (1 << 9) | ||
103 | #define HW_SSP_CTRL1__SLAVE_MODE (1 << 8) | ||
104 | #define HW_SSP_CTRL1__WORD_LENGTH_BM (0xf << 4) | ||
105 | #define HW_SSP_CTRL1__WORD_LENGTH_BP 4 | ||
106 | #define HW_SSP_CTRL1__WORD_LENGTH__EIGHT_BITS 0x7 | ||
107 | #define HW_SSP_CTRL1__SSP_MODE_BM 0xf | ||
108 | #define HW_SSP_CTRL1__SSP_MODE__SD_MMC 0x3 | ||
109 | #define HW_SSP_CTRL1__ALL_IRQ 0xaaa28000 | ||
110 | |||
111 | #define HW_SSP_DATA(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x70)) | ||
112 | |||
113 | #define HW_SSP_SDRESP0(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x80)) | ||
114 | #define HW_SSP_SDRESP1(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x90)) | ||
115 | #define HW_SSP_SDRESP2(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0xA0)) | ||
116 | #define HW_SSP_SDRESP3(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0xB0)) | ||
117 | |||
118 | #define HW_SSP_STATUS(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0xC0)) | ||
119 | #define HW_SSP_STATUS__RECV_TIMEOUT_STAT (1 << 11) | ||
120 | #define HW_SSP_STATUS__TIMEOUT (1 << 12) | ||
121 | #define HW_SSP_STATUS__DATA_CRC_ERR (1 << 13) | ||
122 | #define HW_SSP_STATUS__RESP_TIMEOUT (1 << 14) | ||
123 | #define HW_SSP_STATUS__RESP_ERR (1 << 15) | ||
124 | #define HW_SSP_STATUS__RESP_CRC_ERR (1 << 16) | ||
125 | #define HW_SSP_STATUS__ALL_ERRORS 0x1f800 | ||
126 | |||
127 | #define HW_SSP_DEBUG(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x100)) | ||
128 | |||
129 | #define HW_SSP_VERSION(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x110)) | ||
130 | |||
131 | enum imx233_ssp_error_t | ||
132 | { | ||
133 | SSP_SUCCESS = 0, | ||
134 | SSP_ERROR = -1, | ||
135 | SSP_TIMEOUT = -2, | ||
136 | }; | ||
137 | |||
138 | enum imx233_ssp_resp_t | ||
139 | { | ||
140 | SSP_NO_RESP = 0, | ||
141 | SSP_SHORT_RESP, | ||
142 | SSP_LONG_RESP | ||
143 | }; | ||
144 | |||
145 | void imx233_ssp_init(void); | ||
146 | void imx233_ssp_start(int ssp); | ||
147 | void imx233_ssp_stop(int ssp); | ||
148 | /* only softreset between start and stop or it might hang ! */ | ||
149 | void imx233_ssp_softreset(int ssp); | ||
150 | void imx233_ssp_set_timings(int ssp, int divide, int rate); | ||
151 | void imx233_ssp_set_timeout(int ssp, int timeout); | ||
152 | void imx233_ssp_set_mode(int ssp, unsigned mode); | ||
153 | /* SD/MMC facilities */ | ||
154 | enum imx233_ssp_error_t imx233_ssp_sd_mmc_transfer(int ssp, uint8_t cmd, uint32_t cmd_arg, | ||
155 | enum imx233_ssp_resp_t resp, void *buffer, int xfer_size, bool read, uint32_t *resp_ptr); | ||
156 | void imx233_ssp_setup_ssp2_sd_mmc_pins(bool enable_pullups, unsigned bus_width, | ||
157 | unsigned drive_strength); | ||
158 | /* SD/MMC requires that the card be provided the clock during an init sequence of | ||
159 | * at least 1msec (or 74 clocks). Does NOT touch the clock so it has to be correct. */ | ||
160 | void imx233_ssp_sd_mmc_power_up_sequence(int ssp); | ||
161 | |||
162 | #endif /* __SSP_IMX233_H__ */ | ||
diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c index aedffd1cf6..9c843c48c1 100644 --- a/firmware/target/arm/imx233/system-imx233.c +++ b/firmware/target/arm/imx233/system-imx233.c | |||
@@ -27,6 +27,8 @@ | |||
27 | #include "clkctrl-imx233.h" | 27 | #include "clkctrl-imx233.h" |
28 | #include "pinctrl-imx233.h" | 28 | #include "pinctrl-imx233.h" |
29 | #include "timrot-imx233.h" | 29 | #include "timrot-imx233.h" |
30 | #include "dma-imx233.h" | ||
31 | #include "ssp-imx233.h" | ||
30 | #include "lcd.h" | 32 | #include "lcd.h" |
31 | #include "backlight-target.h" | 33 | #include "backlight-target.h" |
32 | 34 | ||
@@ -44,6 +46,10 @@ default_interrupt(INT_TIMER2); | |||
44 | default_interrupt(INT_TIMER3); | 46 | default_interrupt(INT_TIMER3); |
45 | default_interrupt(INT_LCDIF_DMA); | 47 | default_interrupt(INT_LCDIF_DMA); |
46 | default_interrupt(INT_LCDIF_ERROR); | 48 | default_interrupt(INT_LCDIF_ERROR); |
49 | default_interrupt(INT_SSP1_DMA); | ||
50 | default_interrupt(INT_SSP1_ERROR); | ||
51 | default_interrupt(INT_SSP2_DMA); | ||
52 | default_interrupt(INT_SSP2_ERROR); | ||
47 | 53 | ||
48 | typedef void (*isr_t)(void); | 54 | typedef void (*isr_t)(void); |
49 | 55 | ||
@@ -56,6 +62,10 @@ static isr_t isr_table[INT_SRC_NR_SOURCES] = | |||
56 | [INT_SRC_TIMER(3)] = INT_TIMER3, | 62 | [INT_SRC_TIMER(3)] = INT_TIMER3, |
57 | [INT_SRC_LCDIF_DMA] = INT_LCDIF_DMA, | 63 | [INT_SRC_LCDIF_DMA] = INT_LCDIF_DMA, |
58 | [INT_SRC_LCDIF_ERROR] = INT_LCDIF_ERROR, | 64 | [INT_SRC_LCDIF_ERROR] = INT_LCDIF_ERROR, |
65 | [INT_SRC_SSP1_DMA] = INT_SSP1_DMA, | ||
66 | [INT_SRC_SSP1_ERROR] = INT_SSP1_ERROR, | ||
67 | [INT_SRC_SSP2_DMA] = INT_SSP2_DMA, | ||
68 | [INT_SRC_SSP2_ERROR] = INT_SSP2_ERROR | ||
59 | }; | 69 | }; |
60 | 70 | ||
61 | static void UIRQ(void) | 71 | static void UIRQ(void) |
@@ -128,6 +138,8 @@ void system_init(void) | |||
128 | 138 | ||
129 | imx233_pinctrl_init(); | 139 | imx233_pinctrl_init(); |
130 | imx233_timrot_init(); | 140 | imx233_timrot_init(); |
141 | imx233_dma_init(); | ||
142 | imx233_ssp_init(); | ||
131 | } | 143 | } |
132 | 144 | ||
133 | void power_off(void) | 145 | void power_off(void) |
diff --git a/firmware/target/arm/imx233/system-target.h b/firmware/target/arm/imx233/system-target.h index 4d767b3a9f..163eacb41f 100644 --- a/firmware/target/arm/imx233/system-target.h +++ b/firmware/target/arm/imx233/system-target.h | |||
@@ -57,7 +57,11 @@ | |||
57 | #define HW_ICOLL_INTERRUPT__SOFTIRQ 0x8 | 57 | #define HW_ICOLL_INTERRUPT__SOFTIRQ 0x8 |
58 | #define HW_ICOLL_INTERRUPT__ENFIQ 0x10 | 58 | #define HW_ICOLL_INTERRUPT__ENFIQ 0x10 |
59 | 59 | ||
60 | #define INT_SRC_SSP2_ERROR 2 | ||
60 | #define INT_SRC_USB_CTRL 11 | 61 | #define INT_SRC_USB_CTRL 11 |
62 | #define INT_SRC_SSP1_DMA 14 | ||
63 | #define INT_SRC_SSP1_ERROR 15 | ||
64 | #define INT_SRC_SSP2_DMA 20 | ||
61 | #define INT_SRC_TIMER(nr) (28 + (nr)) | 65 | #define INT_SRC_TIMER(nr) (28 + (nr)) |
62 | #define INT_SRC_LCDIF_DMA 45 | 66 | #define INT_SRC_LCDIF_DMA 45 |
63 | #define INT_SRC_LCDIF_ERROR 46 | 67 | #define INT_SRC_LCDIF_ERROR 46 |
diff --git a/firmware/target/arm/imx233/usb-imx233.c b/firmware/target/arm/imx233/usb-imx233.c new file mode 100644 index 0000000000..83e50839b4 --- /dev/null +++ b/firmware/target/arm/imx233/usb-imx233.c | |||
@@ -0,0 +1,76 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2011 by Amaury Pouly | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "config.h" | ||
23 | #include "cpu.h" | ||
24 | #include "string.h" | ||
25 | #include "usb.h" | ||
26 | #include "usb_drv.h" | ||
27 | #include "usb_core.h" | ||
28 | #include "usb-target.h" | ||
29 | #include "system.h" | ||
30 | #include "system-target.h" | ||
31 | |||
32 | int usb_status = USB_EXTRACTED; | ||
33 | |||
34 | void usb_drv_usb_detect_event() | ||
35 | { | ||
36 | usb_status_event(USB_INSERTED); | ||
37 | } | ||
38 | |||
39 | void usb_attach(void) | ||
40 | { | ||
41 | usb_drv_attach(); | ||
42 | } | ||
43 | |||
44 | void usb_drv_int_enable(bool enable) | ||
45 | { | ||
46 | imx233_enable_interrupt(INT_SRC_USB_CTRL, enable); | ||
47 | } | ||
48 | |||
49 | void INT_USB_CTRL(void) | ||
50 | { | ||
51 | printf("usb int"); | ||
52 | usb_drv_int(); | ||
53 | } | ||
54 | |||
55 | void usb_init_device(void) | ||
56 | { | ||
57 | usb_drv_startup(); | ||
58 | } | ||
59 | |||
60 | int usb_detect(void) | ||
61 | { | ||
62 | return usb_status; | ||
63 | } | ||
64 | |||
65 | bool usb_plugged(void) | ||
66 | { | ||
67 | return true; | ||
68 | } | ||
69 | |||
70 | void usb_enable(bool on) | ||
71 | { | ||
72 | if(on) | ||
73 | usb_core_init(); | ||
74 | else | ||
75 | usb_core_exit(); | ||
76 | } | ||