diff options
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3700/regs-ir.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3700/regs-ir.h | 493 |
1 files changed, 493 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ir.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ir.h new file mode 100644 index 0000000000..d7c14dcecf --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-ir.h | |||
@@ -0,0 +1,493 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__IR__H__ | ||
24 | #define __HEADERGEN__STMP3700__IR__H__ | ||
25 | |||
26 | #define REGS_IR_BASE (0x80078000) | ||
27 | |||
28 | #define REGS_IR_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_IR_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_IR_CTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x0)) | ||
36 | #define HW_IR_CTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x4)) | ||
37 | #define HW_IR_CTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x8)) | ||
38 | #define HW_IR_CTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0xc)) | ||
39 | #define BP_IR_CTRL_SFTRST 31 | ||
40 | #define BM_IR_CTRL_SFTRST 0x80000000 | ||
41 | #define BV_IR_CTRL_SFTRST__RUN 0x0 | ||
42 | #define BV_IR_CTRL_SFTRST__RESET 0x1 | ||
43 | #define BF_IR_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_IR_CTRL_SFTRST_V(v) ((BV_IR_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_IR_CTRL_CLKGATE 30 | ||
46 | #define BM_IR_CTRL_CLKGATE 0x40000000 | ||
47 | #define BF_IR_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
48 | #define BP_IR_CTRL_MTA 24 | ||
49 | #define BM_IR_CTRL_MTA 0x7000000 | ||
50 | #define BV_IR_CTRL_MTA__MTA_10MS 0x0 | ||
51 | #define BV_IR_CTRL_MTA__MTA_5MS 0x1 | ||
52 | #define BV_IR_CTRL_MTA__MTA_1MS 0x2 | ||
53 | #define BV_IR_CTRL_MTA__MTA_500US 0x3 | ||
54 | #define BV_IR_CTRL_MTA__MTA_100US 0x4 | ||
55 | #define BV_IR_CTRL_MTA__MTA_50US 0x5 | ||
56 | #define BV_IR_CTRL_MTA__MTA_10US 0x6 | ||
57 | #define BV_IR_CTRL_MTA__MTA_0 0x7 | ||
58 | #define BF_IR_CTRL_MTA(v) (((v) << 24) & 0x7000000) | ||
59 | #define BF_IR_CTRL_MTA_V(v) ((BV_IR_CTRL_MTA__##v << 24) & 0x7000000) | ||
60 | #define BP_IR_CTRL_MODE 22 | ||
61 | #define BM_IR_CTRL_MODE 0xc00000 | ||
62 | #define BV_IR_CTRL_MODE__SIR 0x0 | ||
63 | #define BV_IR_CTRL_MODE__MIR 0x1 | ||
64 | #define BV_IR_CTRL_MODE__FIR 0x2 | ||
65 | #define BV_IR_CTRL_MODE__VFIR 0x3 | ||
66 | #define BF_IR_CTRL_MODE(v) (((v) << 22) & 0xc00000) | ||
67 | #define BF_IR_CTRL_MODE_V(v) ((BV_IR_CTRL_MODE__##v << 22) & 0xc00000) | ||
68 | #define BP_IR_CTRL_SPEED 19 | ||
69 | #define BM_IR_CTRL_SPEED 0x380000 | ||
70 | #define BV_IR_CTRL_SPEED__SPD000 0x0 | ||
71 | #define BV_IR_CTRL_SPEED__SPD001 0x1 | ||
72 | #define BV_IR_CTRL_SPEED__SPD010 0x2 | ||
73 | #define BV_IR_CTRL_SPEED__SPD011 0x3 | ||
74 | #define BV_IR_CTRL_SPEED__SPD100 0x4 | ||
75 | #define BV_IR_CTRL_SPEED__SPD101 0x5 | ||
76 | #define BF_IR_CTRL_SPEED(v) (((v) << 19) & 0x380000) | ||
77 | #define BF_IR_CTRL_SPEED_V(v) ((BV_IR_CTRL_SPEED__##v << 19) & 0x380000) | ||
78 | #define BP_IR_CTRL_TC_TIME_DIV 8 | ||
79 | #define BM_IR_CTRL_TC_TIME_DIV 0x3f00 | ||
80 | #define BF_IR_CTRL_TC_TIME_DIV(v) (((v) << 8) & 0x3f00) | ||
81 | #define BP_IR_CTRL_TC_TYPE 7 | ||
82 | #define BM_IR_CTRL_TC_TYPE 0x80 | ||
83 | #define BF_IR_CTRL_TC_TYPE(v) (((v) << 7) & 0x80) | ||
84 | #define BP_IR_CTRL_SIR_GAP 4 | ||
85 | #define BM_IR_CTRL_SIR_GAP 0x70 | ||
86 | #define BV_IR_CTRL_SIR_GAP__GAP_10K 0x0 | ||
87 | #define BV_IR_CTRL_SIR_GAP__GAP_5K 0x1 | ||
88 | #define BV_IR_CTRL_SIR_GAP__GAP_1K 0x2 | ||
89 | #define BV_IR_CTRL_SIR_GAP__GAP_500 0x3 | ||
90 | #define BV_IR_CTRL_SIR_GAP__GAP_100 0x4 | ||
91 | #define BV_IR_CTRL_SIR_GAP__GAP_50 0x5 | ||
92 | #define BV_IR_CTRL_SIR_GAP__GAP_10 0x6 | ||
93 | #define BV_IR_CTRL_SIR_GAP__GAP_0 0x7 | ||
94 | #define BF_IR_CTRL_SIR_GAP(v) (((v) << 4) & 0x70) | ||
95 | #define BF_IR_CTRL_SIR_GAP_V(v) ((BV_IR_CTRL_SIR_GAP__##v << 4) & 0x70) | ||
96 | #define BP_IR_CTRL_SIPEN 3 | ||
97 | #define BM_IR_CTRL_SIPEN 0x8 | ||
98 | #define BF_IR_CTRL_SIPEN(v) (((v) << 3) & 0x8) | ||
99 | #define BP_IR_CTRL_TCEN 2 | ||
100 | #define BM_IR_CTRL_TCEN 0x4 | ||
101 | #define BF_IR_CTRL_TCEN(v) (((v) << 2) & 0x4) | ||
102 | #define BP_IR_CTRL_TXEN 1 | ||
103 | #define BM_IR_CTRL_TXEN 0x2 | ||
104 | #define BF_IR_CTRL_TXEN(v) (((v) << 1) & 0x2) | ||
105 | #define BP_IR_CTRL_RXEN 0 | ||
106 | #define BM_IR_CTRL_RXEN 0x1 | ||
107 | #define BF_IR_CTRL_RXEN(v) (((v) << 0) & 0x1) | ||
108 | |||
109 | /** | ||
110 | * Register: HW_IR_TXDMA | ||
111 | * Address: 0x10 | ||
112 | * SCT: yes | ||
113 | */ | ||
114 | #define HW_IR_TXDMA (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x0)) | ||
115 | #define HW_IR_TXDMA_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x4)) | ||
116 | #define HW_IR_TXDMA_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x8)) | ||
117 | #define HW_IR_TXDMA_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0xc)) | ||
118 | #define BP_IR_TXDMA_RUN 31 | ||
119 | #define BM_IR_TXDMA_RUN 0x80000000 | ||
120 | #define BF_IR_TXDMA_RUN(v) (((v) << 31) & 0x80000000) | ||
121 | #define BP_IR_TXDMA_EMPTY 29 | ||
122 | #define BM_IR_TXDMA_EMPTY 0x20000000 | ||
123 | #define BF_IR_TXDMA_EMPTY(v) (((v) << 29) & 0x20000000) | ||
124 | #define BP_IR_TXDMA_INT 28 | ||
125 | #define BM_IR_TXDMA_INT 0x10000000 | ||
126 | #define BF_IR_TXDMA_INT(v) (((v) << 28) & 0x10000000) | ||
127 | #define BP_IR_TXDMA_CHANGE 27 | ||
128 | #define BM_IR_TXDMA_CHANGE 0x8000000 | ||
129 | #define BF_IR_TXDMA_CHANGE(v) (((v) << 27) & 0x8000000) | ||
130 | #define BP_IR_TXDMA_NEW_MTA 24 | ||
131 | #define BM_IR_TXDMA_NEW_MTA 0x7000000 | ||
132 | #define BF_IR_TXDMA_NEW_MTA(v) (((v) << 24) & 0x7000000) | ||
133 | #define BP_IR_TXDMA_NEW_MODE 22 | ||
134 | #define BM_IR_TXDMA_NEW_MODE 0xc00000 | ||
135 | #define BF_IR_TXDMA_NEW_MODE(v) (((v) << 22) & 0xc00000) | ||
136 | #define BP_IR_TXDMA_NEW_SPEED 19 | ||
137 | #define BM_IR_TXDMA_NEW_SPEED 0x380000 | ||
138 | #define BF_IR_TXDMA_NEW_SPEED(v) (((v) << 19) & 0x380000) | ||
139 | #define BP_IR_TXDMA_BOF_TYPE 18 | ||
140 | #define BM_IR_TXDMA_BOF_TYPE 0x40000 | ||
141 | #define BF_IR_TXDMA_BOF_TYPE(v) (((v) << 18) & 0x40000) | ||
142 | #define BP_IR_TXDMA_XBOFS 12 | ||
143 | #define BM_IR_TXDMA_XBOFS 0x3f000 | ||
144 | #define BF_IR_TXDMA_XBOFS(v) (((v) << 12) & 0x3f000) | ||
145 | #define BP_IR_TXDMA_XFER_COUNT 0 | ||
146 | #define BM_IR_TXDMA_XFER_COUNT 0xfff | ||
147 | #define BF_IR_TXDMA_XFER_COUNT(v) (((v) << 0) & 0xfff) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_IR_RXDMA | ||
151 | * Address: 0x20 | ||
152 | * SCT: yes | ||
153 | */ | ||
154 | #define HW_IR_RXDMA (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x0)) | ||
155 | #define HW_IR_RXDMA_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x4)) | ||
156 | #define HW_IR_RXDMA_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x8)) | ||
157 | #define HW_IR_RXDMA_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0xc)) | ||
158 | #define BP_IR_RXDMA_RUN 31 | ||
159 | #define BM_IR_RXDMA_RUN 0x80000000 | ||
160 | #define BF_IR_RXDMA_RUN(v) (((v) << 31) & 0x80000000) | ||
161 | #define BP_IR_RXDMA_XFER_COUNT 0 | ||
162 | #define BM_IR_RXDMA_XFER_COUNT 0x3ff | ||
163 | #define BF_IR_RXDMA_XFER_COUNT(v) (((v) << 0) & 0x3ff) | ||
164 | |||
165 | /** | ||
166 | * Register: HW_IR_DBGCTRL | ||
167 | * Address: 0x30 | ||
168 | * SCT: yes | ||
169 | */ | ||
170 | #define HW_IR_DBGCTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x0)) | ||
171 | #define HW_IR_DBGCTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x4)) | ||
172 | #define HW_IR_DBGCTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x8)) | ||
173 | #define HW_IR_DBGCTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0xc)) | ||
174 | #define BP_IR_DBGCTRL_VFIRSWZ 12 | ||
175 | #define BM_IR_DBGCTRL_VFIRSWZ 0x1000 | ||
176 | #define BV_IR_DBGCTRL_VFIRSWZ__NORMAL 0x0 | ||
177 | #define BV_IR_DBGCTRL_VFIRSWZ__SWAP 0x1 | ||
178 | #define BF_IR_DBGCTRL_VFIRSWZ(v) (((v) << 12) & 0x1000) | ||
179 | #define BF_IR_DBGCTRL_VFIRSWZ_V(v) ((BV_IR_DBGCTRL_VFIRSWZ__##v << 12) & 0x1000) | ||
180 | #define BP_IR_DBGCTRL_RXFRMOFF 11 | ||
181 | #define BM_IR_DBGCTRL_RXFRMOFF 0x800 | ||
182 | #define BF_IR_DBGCTRL_RXFRMOFF(v) (((v) << 11) & 0x800) | ||
183 | #define BP_IR_DBGCTRL_RXCRCOFF 10 | ||
184 | #define BM_IR_DBGCTRL_RXCRCOFF 0x400 | ||
185 | #define BF_IR_DBGCTRL_RXCRCOFF(v) (((v) << 10) & 0x400) | ||
186 | #define BP_IR_DBGCTRL_RXINVERT 9 | ||
187 | #define BM_IR_DBGCTRL_RXINVERT 0x200 | ||
188 | #define BF_IR_DBGCTRL_RXINVERT(v) (((v) << 9) & 0x200) | ||
189 | #define BP_IR_DBGCTRL_TXFRMOFF 8 | ||
190 | #define BM_IR_DBGCTRL_TXFRMOFF 0x100 | ||
191 | #define BF_IR_DBGCTRL_TXFRMOFF(v) (((v) << 8) & 0x100) | ||
192 | #define BP_IR_DBGCTRL_TXCRCOFF 7 | ||
193 | #define BM_IR_DBGCTRL_TXCRCOFF 0x80 | ||
194 | #define BF_IR_DBGCTRL_TXCRCOFF(v) (((v) << 7) & 0x80) | ||
195 | #define BP_IR_DBGCTRL_TXINVERT 6 | ||
196 | #define BM_IR_DBGCTRL_TXINVERT 0x40 | ||
197 | #define BF_IR_DBGCTRL_TXINVERT(v) (((v) << 6) & 0x40) | ||
198 | #define BP_IR_DBGCTRL_INTLOOPBACK 5 | ||
199 | #define BM_IR_DBGCTRL_INTLOOPBACK 0x20 | ||
200 | #define BF_IR_DBGCTRL_INTLOOPBACK(v) (((v) << 5) & 0x20) | ||
201 | #define BP_IR_DBGCTRL_DUPLEX 4 | ||
202 | #define BM_IR_DBGCTRL_DUPLEX 0x10 | ||
203 | #define BF_IR_DBGCTRL_DUPLEX(v) (((v) << 4) & 0x10) | ||
204 | #define BP_IR_DBGCTRL_MIO_RX 3 | ||
205 | #define BM_IR_DBGCTRL_MIO_RX 0x8 | ||
206 | #define BF_IR_DBGCTRL_MIO_RX(v) (((v) << 3) & 0x8) | ||
207 | #define BP_IR_DBGCTRL_MIO_TX 2 | ||
208 | #define BM_IR_DBGCTRL_MIO_TX 0x4 | ||
209 | #define BF_IR_DBGCTRL_MIO_TX(v) (((v) << 2) & 0x4) | ||
210 | #define BP_IR_DBGCTRL_MIO_SCLK 1 | ||
211 | #define BM_IR_DBGCTRL_MIO_SCLK 0x2 | ||
212 | #define BF_IR_DBGCTRL_MIO_SCLK(v) (((v) << 1) & 0x2) | ||
213 | #define BP_IR_DBGCTRL_MIO_EN 0 | ||
214 | #define BM_IR_DBGCTRL_MIO_EN 0x1 | ||
215 | #define BF_IR_DBGCTRL_MIO_EN(v) (((v) << 0) & 0x1) | ||
216 | |||
217 | /** | ||
218 | * Register: HW_IR_INTR | ||
219 | * Address: 0x40 | ||
220 | * SCT: yes | ||
221 | */ | ||
222 | #define HW_IR_INTR (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x0)) | ||
223 | #define HW_IR_INTR_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x4)) | ||
224 | #define HW_IR_INTR_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x8)) | ||
225 | #define HW_IR_INTR_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0xc)) | ||
226 | #define BP_IR_INTR_RXABORT_IRQ_EN 22 | ||
227 | #define BM_IR_INTR_RXABORT_IRQ_EN 0x400000 | ||
228 | #define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0 | ||
229 | #define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED 0x1 | ||
230 | #define BF_IR_INTR_RXABORT_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
231 | #define BF_IR_INTR_RXABORT_IRQ_EN_V(v) ((BV_IR_INTR_RXABORT_IRQ_EN__##v << 22) & 0x400000) | ||
232 | #define BP_IR_INTR_SPEED_IRQ_EN 21 | ||
233 | #define BM_IR_INTR_SPEED_IRQ_EN 0x200000 | ||
234 | #define BV_IR_INTR_SPEED_IRQ_EN__DISABLED 0x0 | ||
235 | #define BV_IR_INTR_SPEED_IRQ_EN__ENABLED 0x1 | ||
236 | #define BF_IR_INTR_SPEED_IRQ_EN(v) (((v) << 21) & 0x200000) | ||
237 | #define BF_IR_INTR_SPEED_IRQ_EN_V(v) ((BV_IR_INTR_SPEED_IRQ_EN__##v << 21) & 0x200000) | ||
238 | #define BP_IR_INTR_RXOF_IRQ_EN 20 | ||
239 | #define BM_IR_INTR_RXOF_IRQ_EN 0x100000 | ||
240 | #define BV_IR_INTR_RXOF_IRQ_EN__DISABLED 0x0 | ||
241 | #define BV_IR_INTR_RXOF_IRQ_EN__ENABLED 0x1 | ||
242 | #define BF_IR_INTR_RXOF_IRQ_EN(v) (((v) << 20) & 0x100000) | ||
243 | #define BF_IR_INTR_RXOF_IRQ_EN_V(v) ((BV_IR_INTR_RXOF_IRQ_EN__##v << 20) & 0x100000) | ||
244 | #define BP_IR_INTR_TXUF_IRQ_EN 19 | ||
245 | #define BM_IR_INTR_TXUF_IRQ_EN 0x80000 | ||
246 | #define BV_IR_INTR_TXUF_IRQ_EN__DISABLED 0x0 | ||
247 | #define BV_IR_INTR_TXUF_IRQ_EN__ENABLED 0x1 | ||
248 | #define BF_IR_INTR_TXUF_IRQ_EN(v) (((v) << 19) & 0x80000) | ||
249 | #define BF_IR_INTR_TXUF_IRQ_EN_V(v) ((BV_IR_INTR_TXUF_IRQ_EN__##v << 19) & 0x80000) | ||
250 | #define BP_IR_INTR_TC_IRQ_EN 18 | ||
251 | #define BM_IR_INTR_TC_IRQ_EN 0x40000 | ||
252 | #define BV_IR_INTR_TC_IRQ_EN__DISABLED 0x0 | ||
253 | #define BV_IR_INTR_TC_IRQ_EN__ENABLED 0x1 | ||
254 | #define BF_IR_INTR_TC_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
255 | #define BF_IR_INTR_TC_IRQ_EN_V(v) ((BV_IR_INTR_TC_IRQ_EN__##v << 18) & 0x40000) | ||
256 | #define BP_IR_INTR_RX_IRQ_EN 17 | ||
257 | #define BM_IR_INTR_RX_IRQ_EN 0x20000 | ||
258 | #define BV_IR_INTR_RX_IRQ_EN__DISABLED 0x0 | ||
259 | #define BV_IR_INTR_RX_IRQ_EN__ENABLED 0x1 | ||
260 | #define BF_IR_INTR_RX_IRQ_EN(v) (((v) << 17) & 0x20000) | ||
261 | #define BF_IR_INTR_RX_IRQ_EN_V(v) ((BV_IR_INTR_RX_IRQ_EN__##v << 17) & 0x20000) | ||
262 | #define BP_IR_INTR_TX_IRQ_EN 16 | ||
263 | #define BM_IR_INTR_TX_IRQ_EN 0x10000 | ||
264 | #define BV_IR_INTR_TX_IRQ_EN__DISABLED 0x0 | ||
265 | #define BV_IR_INTR_TX_IRQ_EN__ENABLED 0x1 | ||
266 | #define BF_IR_INTR_TX_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
267 | #define BF_IR_INTR_TX_IRQ_EN_V(v) ((BV_IR_INTR_TX_IRQ_EN__##v << 16) & 0x10000) | ||
268 | #define BP_IR_INTR_RXABORT_IRQ 6 | ||
269 | #define BM_IR_INTR_RXABORT_IRQ 0x40 | ||
270 | #define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST 0x0 | ||
271 | #define BV_IR_INTR_RXABORT_IRQ__REQUEST 0x1 | ||
272 | #define BF_IR_INTR_RXABORT_IRQ(v) (((v) << 6) & 0x40) | ||
273 | #define BF_IR_INTR_RXABORT_IRQ_V(v) ((BV_IR_INTR_RXABORT_IRQ__##v << 6) & 0x40) | ||
274 | #define BP_IR_INTR_SPEED_IRQ 5 | ||
275 | #define BM_IR_INTR_SPEED_IRQ 0x20 | ||
276 | #define BV_IR_INTR_SPEED_IRQ__NO_REQUEST 0x0 | ||
277 | #define BV_IR_INTR_SPEED_IRQ__REQUEST 0x1 | ||
278 | #define BF_IR_INTR_SPEED_IRQ(v) (((v) << 5) & 0x20) | ||
279 | #define BF_IR_INTR_SPEED_IRQ_V(v) ((BV_IR_INTR_SPEED_IRQ__##v << 5) & 0x20) | ||
280 | #define BP_IR_INTR_RXOF_IRQ 4 | ||
281 | #define BM_IR_INTR_RXOF_IRQ 0x10 | ||
282 | #define BV_IR_INTR_RXOF_IRQ__NO_REQUEST 0x0 | ||
283 | #define BV_IR_INTR_RXOF_IRQ__REQUEST 0x1 | ||
284 | #define BF_IR_INTR_RXOF_IRQ(v) (((v) << 4) & 0x10) | ||
285 | #define BF_IR_INTR_RXOF_IRQ_V(v) ((BV_IR_INTR_RXOF_IRQ__##v << 4) & 0x10) | ||
286 | #define BP_IR_INTR_TXUF_IRQ 3 | ||
287 | #define BM_IR_INTR_TXUF_IRQ 0x8 | ||
288 | #define BV_IR_INTR_TXUF_IRQ__NO_REQUEST 0x0 | ||
289 | #define BV_IR_INTR_TXUF_IRQ__REQUEST 0x1 | ||
290 | #define BF_IR_INTR_TXUF_IRQ(v) (((v) << 3) & 0x8) | ||
291 | #define BF_IR_INTR_TXUF_IRQ_V(v) ((BV_IR_INTR_TXUF_IRQ__##v << 3) & 0x8) | ||
292 | #define BP_IR_INTR_TC_IRQ 2 | ||
293 | #define BM_IR_INTR_TC_IRQ 0x4 | ||
294 | #define BV_IR_INTR_TC_IRQ__NO_REQUEST 0x0 | ||
295 | #define BV_IR_INTR_TC_IRQ__REQUEST 0x1 | ||
296 | #define BF_IR_INTR_TC_IRQ(v) (((v) << 2) & 0x4) | ||
297 | #define BF_IR_INTR_TC_IRQ_V(v) ((BV_IR_INTR_TC_IRQ__##v << 2) & 0x4) | ||
298 | #define BP_IR_INTR_RX_IRQ 1 | ||
299 | #define BM_IR_INTR_RX_IRQ 0x2 | ||
300 | #define BV_IR_INTR_RX_IRQ__NO_REQUEST 0x0 | ||
301 | #define BV_IR_INTR_RX_IRQ__REQUEST 0x1 | ||
302 | #define BF_IR_INTR_RX_IRQ(v) (((v) << 1) & 0x2) | ||
303 | #define BF_IR_INTR_RX_IRQ_V(v) ((BV_IR_INTR_RX_IRQ__##v << 1) & 0x2) | ||
304 | #define BP_IR_INTR_TX_IRQ 0 | ||
305 | #define BM_IR_INTR_TX_IRQ 0x1 | ||
306 | #define BV_IR_INTR_TX_IRQ__NO_REQUEST 0x0 | ||
307 | #define BV_IR_INTR_TX_IRQ__REQUEST 0x1 | ||
308 | #define BF_IR_INTR_TX_IRQ(v) (((v) << 0) & 0x1) | ||
309 | #define BF_IR_INTR_TX_IRQ_V(v) ((BV_IR_INTR_TX_IRQ__##v << 0) & 0x1) | ||
310 | |||
311 | /** | ||
312 | * Register: HW_IR_DATA | ||
313 | * Address: 0x50 | ||
314 | * SCT: no | ||
315 | */ | ||
316 | #define HW_IR_DATA (*(volatile unsigned long *)(REGS_IR_BASE + 0x50)) | ||
317 | #define BP_IR_DATA_DATA 0 | ||
318 | #define BM_IR_DATA_DATA 0xffffffff | ||
319 | #define BF_IR_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
320 | |||
321 | /** | ||
322 | * Register: HW_IR_STAT | ||
323 | * Address: 0x60 | ||
324 | * SCT: no | ||
325 | */ | ||
326 | #define HW_IR_STAT (*(volatile unsigned long *)(REGS_IR_BASE + 0x60)) | ||
327 | #define BP_IR_STAT_PRESENT 31 | ||
328 | #define BM_IR_STAT_PRESENT 0x80000000 | ||
329 | #define BV_IR_STAT_PRESENT__UNAVAILABLE 0x0 | ||
330 | #define BV_IR_STAT_PRESENT__AVAILABLE 0x1 | ||
331 | #define BF_IR_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
332 | #define BF_IR_STAT_PRESENT_V(v) ((BV_IR_STAT_PRESENT__##v << 31) & 0x80000000) | ||
333 | #define BP_IR_STAT_MODE_ALLOWED 29 | ||
334 | #define BM_IR_STAT_MODE_ALLOWED 0x60000000 | ||
335 | #define BV_IR_STAT_MODE_ALLOWED__VFIR 0x0 | ||
336 | #define BV_IR_STAT_MODE_ALLOWED__FIR 0x1 | ||
337 | #define BV_IR_STAT_MODE_ALLOWED__MIR 0x2 | ||
338 | #define BV_IR_STAT_MODE_ALLOWED__SIR 0x3 | ||
339 | #define BF_IR_STAT_MODE_ALLOWED(v) (((v) << 29) & 0x60000000) | ||
340 | #define BF_IR_STAT_MODE_ALLOWED_V(v) ((BV_IR_STAT_MODE_ALLOWED__##v << 29) & 0x60000000) | ||
341 | #define BP_IR_STAT_ANY_IRQ 28 | ||
342 | #define BM_IR_STAT_ANY_IRQ 0x10000000 | ||
343 | #define BV_IR_STAT_ANY_IRQ__NO_REQUEST 0x0 | ||
344 | #define BV_IR_STAT_ANY_IRQ__REQUEST 0x1 | ||
345 | #define BF_IR_STAT_ANY_IRQ(v) (((v) << 28) & 0x10000000) | ||
346 | #define BF_IR_STAT_ANY_IRQ_V(v) ((BV_IR_STAT_ANY_IRQ__##v << 28) & 0x10000000) | ||
347 | #define BP_IR_STAT_RXABORT_SUMMARY 22 | ||
348 | #define BM_IR_STAT_RXABORT_SUMMARY 0x400000 | ||
349 | #define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST 0x0 | ||
350 | #define BV_IR_STAT_RXABORT_SUMMARY__REQUEST 0x1 | ||
351 | #define BF_IR_STAT_RXABORT_SUMMARY(v) (((v) << 22) & 0x400000) | ||
352 | #define BF_IR_STAT_RXABORT_SUMMARY_V(v) ((BV_IR_STAT_RXABORT_SUMMARY__##v << 22) & 0x400000) | ||
353 | #define BP_IR_STAT_SPEED_SUMMARY 21 | ||
354 | #define BM_IR_STAT_SPEED_SUMMARY 0x200000 | ||
355 | #define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST 0x0 | ||
356 | #define BV_IR_STAT_SPEED_SUMMARY__REQUEST 0x1 | ||
357 | #define BF_IR_STAT_SPEED_SUMMARY(v) (((v) << 21) & 0x200000) | ||
358 | #define BF_IR_STAT_SPEED_SUMMARY_V(v) ((BV_IR_STAT_SPEED_SUMMARY__##v << 21) & 0x200000) | ||
359 | #define BP_IR_STAT_RXOF_SUMMARY 20 | ||
360 | #define BM_IR_STAT_RXOF_SUMMARY 0x100000 | ||
361 | #define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST 0x0 | ||
362 | #define BV_IR_STAT_RXOF_SUMMARY__REQUEST 0x1 | ||
363 | #define BF_IR_STAT_RXOF_SUMMARY(v) (((v) << 20) & 0x100000) | ||
364 | #define BF_IR_STAT_RXOF_SUMMARY_V(v) ((BV_IR_STAT_RXOF_SUMMARY__##v << 20) & 0x100000) | ||
365 | #define BP_IR_STAT_TXUF_SUMMARY 19 | ||
366 | #define BM_IR_STAT_TXUF_SUMMARY 0x80000 | ||
367 | #define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST 0x0 | ||
368 | #define BV_IR_STAT_TXUF_SUMMARY__REQUEST 0x1 | ||
369 | #define BF_IR_STAT_TXUF_SUMMARY(v) (((v) << 19) & 0x80000) | ||
370 | #define BF_IR_STAT_TXUF_SUMMARY_V(v) ((BV_IR_STAT_TXUF_SUMMARY__##v << 19) & 0x80000) | ||
371 | #define BP_IR_STAT_TC_SUMMARY 18 | ||
372 | #define BM_IR_STAT_TC_SUMMARY 0x40000 | ||
373 | #define BV_IR_STAT_TC_SUMMARY__NO_REQUEST 0x0 | ||
374 | #define BV_IR_STAT_TC_SUMMARY__REQUEST 0x1 | ||
375 | #define BF_IR_STAT_TC_SUMMARY(v) (((v) << 18) & 0x40000) | ||
376 | #define BF_IR_STAT_TC_SUMMARY_V(v) ((BV_IR_STAT_TC_SUMMARY__##v << 18) & 0x40000) | ||
377 | #define BP_IR_STAT_RX_SUMMARY 17 | ||
378 | #define BM_IR_STAT_RX_SUMMARY 0x20000 | ||
379 | #define BV_IR_STAT_RX_SUMMARY__NO_REQUEST 0x0 | ||
380 | #define BV_IR_STAT_RX_SUMMARY__REQUEST 0x1 | ||
381 | #define BF_IR_STAT_RX_SUMMARY(v) (((v) << 17) & 0x20000) | ||
382 | #define BF_IR_STAT_RX_SUMMARY_V(v) ((BV_IR_STAT_RX_SUMMARY__##v << 17) & 0x20000) | ||
383 | #define BP_IR_STAT_TX_SUMMARY 16 | ||
384 | #define BM_IR_STAT_TX_SUMMARY 0x10000 | ||
385 | #define BV_IR_STAT_TX_SUMMARY__NO_REQUEST 0x0 | ||
386 | #define BV_IR_STAT_TX_SUMMARY__REQUEST 0x1 | ||
387 | #define BF_IR_STAT_TX_SUMMARY(v) (((v) << 16) & 0x10000) | ||
388 | #define BF_IR_STAT_TX_SUMMARY_V(v) ((BV_IR_STAT_TX_SUMMARY__##v << 16) & 0x10000) | ||
389 | #define BP_IR_STAT_MEDIA_BUSY 2 | ||
390 | #define BM_IR_STAT_MEDIA_BUSY 0x4 | ||
391 | #define BF_IR_STAT_MEDIA_BUSY(v) (((v) << 2) & 0x4) | ||
392 | #define BP_IR_STAT_RX_ACTIVE 1 | ||
393 | #define BM_IR_STAT_RX_ACTIVE 0x2 | ||
394 | #define BF_IR_STAT_RX_ACTIVE(v) (((v) << 1) & 0x2) | ||
395 | #define BP_IR_STAT_TX_ACTIVE 0 | ||
396 | #define BM_IR_STAT_TX_ACTIVE 0x1 | ||
397 | #define BF_IR_STAT_TX_ACTIVE(v) (((v) << 0) & 0x1) | ||
398 | |||
399 | /** | ||
400 | * Register: HW_IR_TCCTRL | ||
401 | * Address: 0x70 | ||
402 | * SCT: yes | ||
403 | */ | ||
404 | #define HW_IR_TCCTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x0)) | ||
405 | #define HW_IR_TCCTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x4)) | ||
406 | #define HW_IR_TCCTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x8)) | ||
407 | #define HW_IR_TCCTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0xc)) | ||
408 | #define BP_IR_TCCTRL_INIT 31 | ||
409 | #define BM_IR_TCCTRL_INIT 0x80000000 | ||
410 | #define BF_IR_TCCTRL_INIT(v) (((v) << 31) & 0x80000000) | ||
411 | #define BP_IR_TCCTRL_GO 30 | ||
412 | #define BM_IR_TCCTRL_GO 0x40000000 | ||
413 | #define BF_IR_TCCTRL_GO(v) (((v) << 30) & 0x40000000) | ||
414 | #define BP_IR_TCCTRL_BUSY 29 | ||
415 | #define BM_IR_TCCTRL_BUSY 0x20000000 | ||
416 | #define BF_IR_TCCTRL_BUSY(v) (((v) << 29) & 0x20000000) | ||
417 | #define BP_IR_TCCTRL_TEMIC 24 | ||
418 | #define BM_IR_TCCTRL_TEMIC 0x1000000 | ||
419 | #define BV_IR_TCCTRL_TEMIC__LOW 0x0 | ||
420 | #define BV_IR_TCCTRL_TEMIC__HIGH 0x1 | ||
421 | #define BF_IR_TCCTRL_TEMIC(v) (((v) << 24) & 0x1000000) | ||
422 | #define BF_IR_TCCTRL_TEMIC_V(v) ((BV_IR_TCCTRL_TEMIC__##v << 24) & 0x1000000) | ||
423 | #define BP_IR_TCCTRL_EXT_DATA 16 | ||
424 | #define BM_IR_TCCTRL_EXT_DATA 0xff0000 | ||
425 | #define BF_IR_TCCTRL_EXT_DATA(v) (((v) << 16) & 0xff0000) | ||
426 | #define BP_IR_TCCTRL_DATA 8 | ||
427 | #define BM_IR_TCCTRL_DATA 0xff00 | ||
428 | #define BF_IR_TCCTRL_DATA(v) (((v) << 8) & 0xff00) | ||
429 | #define BP_IR_TCCTRL_ADDR 5 | ||
430 | #define BM_IR_TCCTRL_ADDR 0xe0 | ||
431 | #define BF_IR_TCCTRL_ADDR(v) (((v) << 5) & 0xe0) | ||
432 | #define BP_IR_TCCTRL_INDX 1 | ||
433 | #define BM_IR_TCCTRL_INDX 0x1e | ||
434 | #define BF_IR_TCCTRL_INDX(v) (((v) << 1) & 0x1e) | ||
435 | #define BP_IR_TCCTRL_C 0 | ||
436 | #define BM_IR_TCCTRL_C 0x1 | ||
437 | #define BF_IR_TCCTRL_C(v) (((v) << 0) & 0x1) | ||
438 | |||
439 | /** | ||
440 | * Register: HW_IR_SI_READ | ||
441 | * Address: 0x80 | ||
442 | * SCT: no | ||
443 | */ | ||
444 | #define HW_IR_SI_READ (*(volatile unsigned long *)(REGS_IR_BASE + 0x80)) | ||
445 | #define BP_IR_SI_READ_ABORT 8 | ||
446 | #define BM_IR_SI_READ_ABORT 0x100 | ||
447 | #define BF_IR_SI_READ_ABORT(v) (((v) << 8) & 0x100) | ||
448 | #define BP_IR_SI_READ_DATA 0 | ||
449 | #define BM_IR_SI_READ_DATA 0xff | ||
450 | #define BF_IR_SI_READ_DATA(v) (((v) << 0) & 0xff) | ||
451 | |||
452 | /** | ||
453 | * Register: HW_IR_DEBUG | ||
454 | * Address: 0x90 | ||
455 | * SCT: no | ||
456 | */ | ||
457 | #define HW_IR_DEBUG (*(volatile unsigned long *)(REGS_IR_BASE + 0x90)) | ||
458 | #define BP_IR_DEBUG_TXDMAKICK 5 | ||
459 | #define BM_IR_DEBUG_TXDMAKICK 0x20 | ||
460 | #define BF_IR_DEBUG_TXDMAKICK(v) (((v) << 5) & 0x20) | ||
461 | #define BP_IR_DEBUG_RXDMAKICK 4 | ||
462 | #define BM_IR_DEBUG_RXDMAKICK 0x10 | ||
463 | #define BF_IR_DEBUG_RXDMAKICK(v) (((v) << 4) & 0x10) | ||
464 | #define BP_IR_DEBUG_TXDMAEND 3 | ||
465 | #define BM_IR_DEBUG_TXDMAEND 0x8 | ||
466 | #define BF_IR_DEBUG_TXDMAEND(v) (((v) << 3) & 0x8) | ||
467 | #define BP_IR_DEBUG_RXDMAEND 2 | ||
468 | #define BM_IR_DEBUG_RXDMAEND 0x4 | ||
469 | #define BF_IR_DEBUG_RXDMAEND(v) (((v) << 2) & 0x4) | ||
470 | #define BP_IR_DEBUG_TXDMAREQ 1 | ||
471 | #define BM_IR_DEBUG_TXDMAREQ 0x2 | ||
472 | #define BF_IR_DEBUG_TXDMAREQ(v) (((v) << 1) & 0x2) | ||
473 | #define BP_IR_DEBUG_RXDMAREQ 0 | ||
474 | #define BM_IR_DEBUG_RXDMAREQ 0x1 | ||
475 | #define BF_IR_DEBUG_RXDMAREQ(v) (((v) << 0) & 0x1) | ||
476 | |||
477 | /** | ||
478 | * Register: HW_IR_VERSION | ||
479 | * Address: 0xa0 | ||
480 | * SCT: no | ||
481 | */ | ||
482 | #define HW_IR_VERSION (*(volatile unsigned long *)(REGS_IR_BASE + 0xa0)) | ||
483 | #define BP_IR_VERSION_MAJOR 24 | ||
484 | #define BM_IR_VERSION_MAJOR 0xff000000 | ||
485 | #define BF_IR_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
486 | #define BP_IR_VERSION_MINOR 16 | ||
487 | #define BM_IR_VERSION_MINOR 0xff0000 | ||
488 | #define BF_IR_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
489 | #define BP_IR_VERSION_STEP 0 | ||
490 | #define BM_IR_VERSION_STEP 0xffff | ||
491 | #define BF_IR_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
492 | |||
493 | #endif /* __HEADERGEN__STMP3700__IR__H__ */ | ||