diff options
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h | 410 |
1 files changed, 410 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h b/firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h new file mode 100644 index 0000000000..a4b7d51519 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h | |||
@@ -0,0 +1,410 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__ICOLL__H__ | ||
24 | #define __HEADERGEN__STMP3700__ICOLL__H__ | ||
25 | |||
26 | #define REGS_ICOLL_BASE (0x80000000) | ||
27 | |||
28 | #define REGS_ICOLL_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_ICOLL_VECTOR | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_ICOLL_VECTOR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_ICOLL_VECTOR_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_ICOLL_VECTOR_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_ICOLL_VECTOR_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_ICOLL_VECTOR_IRQVECTOR 2 | ||
40 | #define BM_ICOLL_VECTOR_IRQVECTOR 0xfffffffc | ||
41 | #define BF_ICOLL_VECTOR_IRQVECTOR(v) (((v) << 2) & 0xfffffffc) | ||
42 | |||
43 | /** | ||
44 | * Register: HW_ICOLL_LEVELACK | ||
45 | * Address: 0x10 | ||
46 | * SCT: no | ||
47 | */ | ||
48 | #define HW_ICOLL_LEVELACK (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x10)) | ||
49 | #define BP_ICOLL_LEVELACK_IRQLEVELACK 0 | ||
50 | #define BM_ICOLL_LEVELACK_IRQLEVELACK 0xf | ||
51 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 | ||
52 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2 | ||
53 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4 | ||
54 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8 | ||
55 | #define BF_ICOLL_LEVELACK_IRQLEVELACK(v) (((v) << 0) & 0xf) | ||
56 | #define BF_ICOLL_LEVELACK_IRQLEVELACK_V(v) ((BV_ICOLL_LEVELACK_IRQLEVELACK__##v << 0) & 0xf) | ||
57 | |||
58 | /** | ||
59 | * Register: HW_ICOLL_CTRL | ||
60 | * Address: 0x20 | ||
61 | * SCT: yes | ||
62 | */ | ||
63 | #define HW_ICOLL_CTRL (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x0)) | ||
64 | #define HW_ICOLL_CTRL_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x4)) | ||
65 | #define HW_ICOLL_CTRL_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x8)) | ||
66 | #define HW_ICOLL_CTRL_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0xc)) | ||
67 | #define BP_ICOLL_CTRL_SFTRST 31 | ||
68 | #define BM_ICOLL_CTRL_SFTRST 0x80000000 | ||
69 | #define BV_ICOLL_CTRL_SFTRST__RUN 0x0 | ||
70 | #define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1 | ||
71 | #define BF_ICOLL_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
72 | #define BF_ICOLL_CTRL_SFTRST_V(v) ((BV_ICOLL_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
73 | #define BP_ICOLL_CTRL_CLKGATE 30 | ||
74 | #define BM_ICOLL_CTRL_CLKGATE 0x40000000 | ||
75 | #define BV_ICOLL_CTRL_CLKGATE__RUN 0x0 | ||
76 | #define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1 | ||
77 | #define BF_ICOLL_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
78 | #define BF_ICOLL_CTRL_CLKGATE_V(v) ((BV_ICOLL_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
79 | #define BP_ICOLL_CTRL_VECTOR_PITCH 21 | ||
80 | #define BM_ICOLL_CTRL_VECTOR_PITCH 0xe00000 | ||
81 | #define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0 | ||
82 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY4 0x1 | ||
83 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY8 0x2 | ||
84 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY12 0x3 | ||
85 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY16 0x4 | ||
86 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY20 0x5 | ||
87 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY24 0x6 | ||
88 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY28 0x7 | ||
89 | #define BF_ICOLL_CTRL_VECTOR_PITCH(v) (((v) << 21) & 0xe00000) | ||
90 | #define BF_ICOLL_CTRL_VECTOR_PITCH_V(v) ((BV_ICOLL_CTRL_VECTOR_PITCH__##v << 21) & 0xe00000) | ||
91 | #define BP_ICOLL_CTRL_BYPASS_FSM 20 | ||
92 | #define BM_ICOLL_CTRL_BYPASS_FSM 0x100000 | ||
93 | #define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0 | ||
94 | #define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1 | ||
95 | #define BF_ICOLL_CTRL_BYPASS_FSM(v) (((v) << 20) & 0x100000) | ||
96 | #define BF_ICOLL_CTRL_BYPASS_FSM_V(v) ((BV_ICOLL_CTRL_BYPASS_FSM__##v << 20) & 0x100000) | ||
97 | #define BP_ICOLL_CTRL_NO_NESTING 19 | ||
98 | #define BM_ICOLL_CTRL_NO_NESTING 0x80000 | ||
99 | #define BV_ICOLL_CTRL_NO_NESTING__NORMAL 0x0 | ||
100 | #define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1 | ||
101 | #define BF_ICOLL_CTRL_NO_NESTING(v) (((v) << 19) & 0x80000) | ||
102 | #define BF_ICOLL_CTRL_NO_NESTING_V(v) ((BV_ICOLL_CTRL_NO_NESTING__##v << 19) & 0x80000) | ||
103 | #define BP_ICOLL_CTRL_ARM_RSE_MODE 18 | ||
104 | #define BM_ICOLL_CTRL_ARM_RSE_MODE 0x40000 | ||
105 | #define BV_ICOLL_CTRL_ARM_RSE_MODE__MUST_WRITE 0x0 | ||
106 | #define BV_ICOLL_CTRL_ARM_RSE_MODE__READ_SIDE_EFFECT 0x1 | ||
107 | #define BF_ICOLL_CTRL_ARM_RSE_MODE(v) (((v) << 18) & 0x40000) | ||
108 | #define BF_ICOLL_CTRL_ARM_RSE_MODE_V(v) ((BV_ICOLL_CTRL_ARM_RSE_MODE__##v << 18) & 0x40000) | ||
109 | #define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE 17 | ||
110 | #define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x20000 | ||
111 | #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0 | ||
112 | #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE 0x1 | ||
113 | #define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v) (((v) << 17) & 0x20000) | ||
114 | #define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v) ((BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##v << 17) & 0x20000) | ||
115 | #define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE 16 | ||
116 | #define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x10000 | ||
117 | #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0 | ||
118 | #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE 0x1 | ||
119 | #define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v) (((v) << 16) & 0x10000) | ||
120 | #define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v) ((BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##v << 16) & 0x10000) | ||
121 | #define BP_ICOLL_CTRL_ENABLE2FIQ35 7 | ||
122 | #define BM_ICOLL_CTRL_ENABLE2FIQ35 0x80 | ||
123 | #define BV_ICOLL_CTRL_ENABLE2FIQ35__DISABLE 0x0 | ||
124 | #define BV_ICOLL_CTRL_ENABLE2FIQ35__ENABLE 0x1 | ||
125 | #define BF_ICOLL_CTRL_ENABLE2FIQ35(v) (((v) << 7) & 0x80) | ||
126 | #define BF_ICOLL_CTRL_ENABLE2FIQ35_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ35__##v << 7) & 0x80) | ||
127 | #define BP_ICOLL_CTRL_ENABLE2FIQ34 6 | ||
128 | #define BM_ICOLL_CTRL_ENABLE2FIQ34 0x40 | ||
129 | #define BV_ICOLL_CTRL_ENABLE2FIQ34__DISABLE 0x0 | ||
130 | #define BV_ICOLL_CTRL_ENABLE2FIQ34__ENABLE 0x1 | ||
131 | #define BF_ICOLL_CTRL_ENABLE2FIQ34(v) (((v) << 6) & 0x40) | ||
132 | #define BF_ICOLL_CTRL_ENABLE2FIQ34_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ34__##v << 6) & 0x40) | ||
133 | #define BP_ICOLL_CTRL_ENABLE2FIQ33 5 | ||
134 | #define BM_ICOLL_CTRL_ENABLE2FIQ33 0x20 | ||
135 | #define BV_ICOLL_CTRL_ENABLE2FIQ33__DISABLE 0x0 | ||
136 | #define BV_ICOLL_CTRL_ENABLE2FIQ33__ENABLE 0x1 | ||
137 | #define BF_ICOLL_CTRL_ENABLE2FIQ33(v) (((v) << 5) & 0x20) | ||
138 | #define BF_ICOLL_CTRL_ENABLE2FIQ33_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ33__##v << 5) & 0x20) | ||
139 | #define BP_ICOLL_CTRL_ENABLE2FIQ32 4 | ||
140 | #define BM_ICOLL_CTRL_ENABLE2FIQ32 0x10 | ||
141 | #define BV_ICOLL_CTRL_ENABLE2FIQ32__DISABLE 0x0 | ||
142 | #define BV_ICOLL_CTRL_ENABLE2FIQ32__ENABLE 0x1 | ||
143 | #define BF_ICOLL_CTRL_ENABLE2FIQ32(v) (((v) << 4) & 0x10) | ||
144 | #define BF_ICOLL_CTRL_ENABLE2FIQ32_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ32__##v << 4) & 0x10) | ||
145 | #define BP_ICOLL_CTRL_ENABLE2FIQ_T3 3 | ||
146 | #define BM_ICOLL_CTRL_ENABLE2FIQ_T3 0x8 | ||
147 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T3__DISABLE 0x0 | ||
148 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T3__ENABLE 0x1 | ||
149 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T3(v) (((v) << 3) & 0x8) | ||
150 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T3_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ_T3__##v << 3) & 0x8) | ||
151 | #define BP_ICOLL_CTRL_ENABLE2FIQ_T2 2 | ||
152 | #define BM_ICOLL_CTRL_ENABLE2FIQ_T2 0x4 | ||
153 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T2__DISABLE 0x0 | ||
154 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T2__ENABLE 0x1 | ||
155 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T2(v) (((v) << 2) & 0x4) | ||
156 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T2_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ_T2__##v << 2) & 0x4) | ||
157 | #define BP_ICOLL_CTRL_ENABLE2FIQ_T1 1 | ||
158 | #define BM_ICOLL_CTRL_ENABLE2FIQ_T1 0x2 | ||
159 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T1__DISABLE 0x0 | ||
160 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T1__ENABLE 0x1 | ||
161 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T1(v) (((v) << 1) & 0x2) | ||
162 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T1_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ_T1__##v << 1) & 0x2) | ||
163 | #define BP_ICOLL_CTRL_ENABLE2FIQ_T0 0 | ||
164 | #define BM_ICOLL_CTRL_ENABLE2FIQ_T0 0x1 | ||
165 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T0__DISABLE 0x0 | ||
166 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T0__ENABLE 0x1 | ||
167 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T0(v) (((v) << 0) & 0x1) | ||
168 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T0_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ_T0__##v << 0) & 0x1) | ||
169 | |||
170 | /** | ||
171 | * Register: HW_ICOLL_STAT | ||
172 | * Address: 0x30 | ||
173 | * SCT: no | ||
174 | */ | ||
175 | #define HW_ICOLL_STAT (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x30)) | ||
176 | #define BP_ICOLL_STAT_VECTOR_NUMBER 0 | ||
177 | #define BM_ICOLL_STAT_VECTOR_NUMBER 0x3f | ||
178 | #define BF_ICOLL_STAT_VECTOR_NUMBER(v) (((v) << 0) & 0x3f) | ||
179 | |||
180 | /** | ||
181 | * Register: HW_ICOLL_RAWn | ||
182 | * Address: 0x40+n*0x10 | ||
183 | * SCT: no | ||
184 | */ | ||
185 | #define HW_ICOLL_RAWn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40+(n)*0x10)) | ||
186 | #define BP_ICOLL_RAWn_RAW_IRQS 0 | ||
187 | #define BM_ICOLL_RAWn_RAW_IRQS 0xffffffff | ||
188 | #define BF_ICOLL_RAWn_RAW_IRQS(v) (((v) << 0) & 0xffffffff) | ||
189 | |||
190 | /** | ||
191 | * Register: HW_ICOLL_PRIORITYn | ||
192 | * Address: 0x60+n*0x10 | ||
193 | * SCT: yes | ||
194 | */ | ||
195 | #define HW_ICOLL_PRIORITYn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x0)) | ||
196 | #define HW_ICOLL_PRIORITYn_SET(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x4)) | ||
197 | #define HW_ICOLL_PRIORITYn_CLR(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x8)) | ||
198 | #define HW_ICOLL_PRIORITYn_TOG(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0xc)) | ||
199 | #define BP_ICOLL_PRIORITYn_SOFTIRQ3 27 | ||
200 | #define BM_ICOLL_PRIORITYn_SOFTIRQ3 0x8000000 | ||
201 | #define BV_ICOLL_PRIORITYn_SOFTIRQ3__NO_INTERRUPT 0x0 | ||
202 | #define BV_ICOLL_PRIORITYn_SOFTIRQ3__FORCE_INTERRUPT 0x1 | ||
203 | #define BF_ICOLL_PRIORITYn_SOFTIRQ3(v) (((v) << 27) & 0x8000000) | ||
204 | #define BF_ICOLL_PRIORITYn_SOFTIRQ3_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ3__##v << 27) & 0x8000000) | ||
205 | #define BP_ICOLL_PRIORITYn_ENABLE3 26 | ||
206 | #define BM_ICOLL_PRIORITYn_ENABLE3 0x4000000 | ||
207 | #define BV_ICOLL_PRIORITYn_ENABLE3__DISABLE 0x0 | ||
208 | #define BV_ICOLL_PRIORITYn_ENABLE3__ENABLE 0x1 | ||
209 | #define BF_ICOLL_PRIORITYn_ENABLE3(v) (((v) << 26) & 0x4000000) | ||
210 | #define BF_ICOLL_PRIORITYn_ENABLE3_V(v) ((BV_ICOLL_PRIORITYn_ENABLE3__##v << 26) & 0x4000000) | ||
211 | #define BP_ICOLL_PRIORITYn_PRIORITY3 24 | ||
212 | #define BM_ICOLL_PRIORITYn_PRIORITY3 0x3000000 | ||
213 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL0 0x0 | ||
214 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL1 0x1 | ||
215 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL2 0x2 | ||
216 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL3 0x3 | ||
217 | #define BF_ICOLL_PRIORITYn_PRIORITY3(v) (((v) << 24) & 0x3000000) | ||
218 | #define BF_ICOLL_PRIORITYn_PRIORITY3_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY3__##v << 24) & 0x3000000) | ||
219 | #define BP_ICOLL_PRIORITYn_SOFTIRQ2 19 | ||
220 | #define BM_ICOLL_PRIORITYn_SOFTIRQ2 0x80000 | ||
221 | #define BV_ICOLL_PRIORITYn_SOFTIRQ2__NO_INTERRUPT 0x0 | ||
222 | #define BV_ICOLL_PRIORITYn_SOFTIRQ2__FORCE_INTERRUPT 0x1 | ||
223 | #define BF_ICOLL_PRIORITYn_SOFTIRQ2(v) (((v) << 19) & 0x80000) | ||
224 | #define BF_ICOLL_PRIORITYn_SOFTIRQ2_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ2__##v << 19) & 0x80000) | ||
225 | #define BP_ICOLL_PRIORITYn_ENABLE2 18 | ||
226 | #define BM_ICOLL_PRIORITYn_ENABLE2 0x40000 | ||
227 | #define BV_ICOLL_PRIORITYn_ENABLE2__DISABLE 0x0 | ||
228 | #define BV_ICOLL_PRIORITYn_ENABLE2__ENABLE 0x1 | ||
229 | #define BF_ICOLL_PRIORITYn_ENABLE2(v) (((v) << 18) & 0x40000) | ||
230 | #define BF_ICOLL_PRIORITYn_ENABLE2_V(v) ((BV_ICOLL_PRIORITYn_ENABLE2__##v << 18) & 0x40000) | ||
231 | #define BP_ICOLL_PRIORITYn_PRIORITY2 16 | ||
232 | #define BM_ICOLL_PRIORITYn_PRIORITY2 0x30000 | ||
233 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL0 0x0 | ||
234 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL1 0x1 | ||
235 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL2 0x2 | ||
236 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL3 0x3 | ||
237 | #define BF_ICOLL_PRIORITYn_PRIORITY2(v) (((v) << 16) & 0x30000) | ||
238 | #define BF_ICOLL_PRIORITYn_PRIORITY2_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY2__##v << 16) & 0x30000) | ||
239 | #define BP_ICOLL_PRIORITYn_SOFTIRQ1 11 | ||
240 | #define BM_ICOLL_PRIORITYn_SOFTIRQ1 0x800 | ||
241 | #define BV_ICOLL_PRIORITYn_SOFTIRQ1__NO_INTERRUPT 0x0 | ||
242 | #define BV_ICOLL_PRIORITYn_SOFTIRQ1__FORCE_INTERRUPT 0x1 | ||
243 | #define BF_ICOLL_PRIORITYn_SOFTIRQ1(v) (((v) << 11) & 0x800) | ||
244 | #define BF_ICOLL_PRIORITYn_SOFTIRQ1_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ1__##v << 11) & 0x800) | ||
245 | #define BP_ICOLL_PRIORITYn_ENABLE1 10 | ||
246 | #define BM_ICOLL_PRIORITYn_ENABLE1 0x400 | ||
247 | #define BV_ICOLL_PRIORITYn_ENABLE1__DISABLE 0x0 | ||
248 | #define BV_ICOLL_PRIORITYn_ENABLE1__ENABLE 0x1 | ||
249 | #define BF_ICOLL_PRIORITYn_ENABLE1(v) (((v) << 10) & 0x400) | ||
250 | #define BF_ICOLL_PRIORITYn_ENABLE1_V(v) ((BV_ICOLL_PRIORITYn_ENABLE1__##v << 10) & 0x400) | ||
251 | #define BP_ICOLL_PRIORITYn_PRIORITY1 8 | ||
252 | #define BM_ICOLL_PRIORITYn_PRIORITY1 0x300 | ||
253 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL0 0x0 | ||
254 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL1 0x1 | ||
255 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL2 0x2 | ||
256 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL3 0x3 | ||
257 | #define BF_ICOLL_PRIORITYn_PRIORITY1(v) (((v) << 8) & 0x300) | ||
258 | #define BF_ICOLL_PRIORITYn_PRIORITY1_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY1__##v << 8) & 0x300) | ||
259 | #define BP_ICOLL_PRIORITYn_SOFTIRQ0 3 | ||
260 | #define BM_ICOLL_PRIORITYn_SOFTIRQ0 0x8 | ||
261 | #define BV_ICOLL_PRIORITYn_SOFTIRQ0__NO_INTERRUPT 0x0 | ||
262 | #define BV_ICOLL_PRIORITYn_SOFTIRQ0__FORCE_INTERRUPT 0x1 | ||
263 | #define BF_ICOLL_PRIORITYn_SOFTIRQ0(v) (((v) << 3) & 0x8) | ||
264 | #define BF_ICOLL_PRIORITYn_SOFTIRQ0_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ0__##v << 3) & 0x8) | ||
265 | #define BP_ICOLL_PRIORITYn_ENABLE0 2 | ||
266 | #define BM_ICOLL_PRIORITYn_ENABLE0 0x4 | ||
267 | #define BV_ICOLL_PRIORITYn_ENABLE0__DISABLE 0x0 | ||
268 | #define BV_ICOLL_PRIORITYn_ENABLE0__ENABLE 0x1 | ||
269 | #define BF_ICOLL_PRIORITYn_ENABLE0(v) (((v) << 2) & 0x4) | ||
270 | #define BF_ICOLL_PRIORITYn_ENABLE0_V(v) ((BV_ICOLL_PRIORITYn_ENABLE0__##v << 2) & 0x4) | ||
271 | #define BP_ICOLL_PRIORITYn_PRIORITY0 0 | ||
272 | #define BM_ICOLL_PRIORITYn_PRIORITY0 0x3 | ||
273 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL0 0x0 | ||
274 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL1 0x1 | ||
275 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL2 0x2 | ||
276 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL3 0x3 | ||
277 | #define BF_ICOLL_PRIORITYn_PRIORITY0(v) (((v) << 0) & 0x3) | ||
278 | #define BF_ICOLL_PRIORITYn_PRIORITY0_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY0__##v << 0) & 0x3) | ||
279 | |||
280 | /** | ||
281 | * Register: HW_ICOLL_VBASE | ||
282 | * Address: 0x160 | ||
283 | * SCT: yes | ||
284 | */ | ||
285 | #define HW_ICOLL_VBASE (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x0)) | ||
286 | #define HW_ICOLL_VBASE_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x4)) | ||
287 | #define HW_ICOLL_VBASE_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x8)) | ||
288 | #define HW_ICOLL_VBASE_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0xc)) | ||
289 | #define BP_ICOLL_VBASE_TABLE_ADDRESS 2 | ||
290 | #define BM_ICOLL_VBASE_TABLE_ADDRESS 0xfffffffc | ||
291 | #define BF_ICOLL_VBASE_TABLE_ADDRESS(v) (((v) << 2) & 0xfffffffc) | ||
292 | |||
293 | /** | ||
294 | * Register: HW_ICOLL_DEBUG | ||
295 | * Address: 0x170 | ||
296 | * SCT: no | ||
297 | */ | ||
298 | #define HW_ICOLL_DEBUG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x170)) | ||
299 | #define BP_ICOLL_DEBUG_INSERVICE 28 | ||
300 | #define BM_ICOLL_DEBUG_INSERVICE 0xf0000000 | ||
301 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1 | ||
302 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2 | ||
303 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4 | ||
304 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8 | ||
305 | #define BF_ICOLL_DEBUG_INSERVICE(v) (((v) << 28) & 0xf0000000) | ||
306 | #define BF_ICOLL_DEBUG_INSERVICE_V(v) ((BV_ICOLL_DEBUG_INSERVICE__##v << 28) & 0xf0000000) | ||
307 | #define BP_ICOLL_DEBUG_LEVEL_REQUESTS 24 | ||
308 | #define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0xf000000 | ||
309 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1 | ||
310 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2 | ||
311 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4 | ||
312 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8 | ||
313 | #define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v) (((v) << 24) & 0xf000000) | ||
314 | #define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(v) ((BV_ICOLL_DEBUG_LEVEL_REQUESTS__##v << 24) & 0xf000000) | ||
315 | #define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL 20 | ||
316 | #define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0xf00000 | ||
317 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1 | ||
318 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2 | ||
319 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4 | ||
320 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8 | ||
321 | #define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v) (((v) << 20) & 0xf00000) | ||
322 | #define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v) ((BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##v << 20) & 0xf00000) | ||
323 | #define BP_ICOLL_DEBUG_FIQ 17 | ||
324 | #define BM_ICOLL_DEBUG_FIQ 0x20000 | ||
325 | #define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0 | ||
326 | #define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED 0x1 | ||
327 | #define BF_ICOLL_DEBUG_FIQ(v) (((v) << 17) & 0x20000) | ||
328 | #define BF_ICOLL_DEBUG_FIQ_V(v) ((BV_ICOLL_DEBUG_FIQ__##v << 17) & 0x20000) | ||
329 | #define BP_ICOLL_DEBUG_IRQ 16 | ||
330 | #define BM_ICOLL_DEBUG_IRQ 0x10000 | ||
331 | #define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0 | ||
332 | #define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED 0x1 | ||
333 | #define BF_ICOLL_DEBUG_IRQ(v) (((v) << 16) & 0x10000) | ||
334 | #define BF_ICOLL_DEBUG_IRQ_V(v) ((BV_ICOLL_DEBUG_IRQ__##v << 16) & 0x10000) | ||
335 | #define BP_ICOLL_DEBUG_VECTOR_FSM 0 | ||
336 | #define BM_ICOLL_DEBUG_VECTOR_FSM 0x3ff | ||
337 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE 0x0 | ||
338 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1 0x1 | ||
339 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2 0x2 | ||
340 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING 0x4 | ||
341 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3 0x8 | ||
342 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4 0x10 | ||
343 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20 | ||
344 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40 | ||
345 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80 | ||
346 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5 0x100 | ||
347 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6 0x200 | ||
348 | #define BF_ICOLL_DEBUG_VECTOR_FSM(v) (((v) << 0) & 0x3ff) | ||
349 | #define BF_ICOLL_DEBUG_VECTOR_FSM_V(v) ((BV_ICOLL_DEBUG_VECTOR_FSM__##v << 0) & 0x3ff) | ||
350 | |||
351 | /** | ||
352 | * Register: HW_ICOLL_DBGREAD0 | ||
353 | * Address: 0x180 | ||
354 | * SCT: no | ||
355 | */ | ||
356 | #define HW_ICOLL_DBGREAD0 (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x180)) | ||
357 | #define BP_ICOLL_DBGREAD0_VALUE 0 | ||
358 | #define BM_ICOLL_DBGREAD0_VALUE 0xffffffff | ||
359 | #define BF_ICOLL_DBGREAD0_VALUE(v) (((v) << 0) & 0xffffffff) | ||
360 | |||
361 | /** | ||
362 | * Register: HW_ICOLL_DBGREAD1 | ||
363 | * Address: 0x190 | ||
364 | * SCT: no | ||
365 | */ | ||
366 | #define HW_ICOLL_DBGREAD1 (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x190)) | ||
367 | #define BP_ICOLL_DBGREAD1_VALUE 0 | ||
368 | #define BM_ICOLL_DBGREAD1_VALUE 0xffffffff | ||
369 | #define BF_ICOLL_DBGREAD1_VALUE(v) (((v) << 0) & 0xffffffff) | ||
370 | |||
371 | /** | ||
372 | * Register: HW_ICOLL_DBGFLAG | ||
373 | * Address: 0x1a0 | ||
374 | * SCT: yes | ||
375 | */ | ||
376 | #define HW_ICOLL_DBGFLAG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x0)) | ||
377 | #define HW_ICOLL_DBGFLAG_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x4)) | ||
378 | #define HW_ICOLL_DBGFLAG_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x8)) | ||
379 | #define HW_ICOLL_DBGFLAG_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0xc)) | ||
380 | #define BP_ICOLL_DBGFLAG_FLAG 0 | ||
381 | #define BM_ICOLL_DBGFLAG_FLAG 0xffff | ||
382 | #define BF_ICOLL_DBGFLAG_FLAG(v) (((v) << 0) & 0xffff) | ||
383 | |||
384 | /** | ||
385 | * Register: HW_ICOLL_DBGREQUESTn | ||
386 | * Address: 0x1b0+n*0x10 | ||
387 | * SCT: no | ||
388 | */ | ||
389 | #define HW_ICOLL_DBGREQUESTn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1b0+(n)*0x10)) | ||
390 | #define BP_ICOLL_DBGREQUESTn_BITS 0 | ||
391 | #define BM_ICOLL_DBGREQUESTn_BITS 0xffffffff | ||
392 | #define BF_ICOLL_DBGREQUESTn_BITS(v) (((v) << 0) & 0xffffffff) | ||
393 | |||
394 | /** | ||
395 | * Register: HW_ICOLL_VERSION | ||
396 | * Address: 0x1d0 | ||
397 | * SCT: no | ||
398 | */ | ||
399 | #define HW_ICOLL_VERSION (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1d0)) | ||
400 | #define BP_ICOLL_VERSION_MAJOR 24 | ||
401 | #define BM_ICOLL_VERSION_MAJOR 0xff000000 | ||
402 | #define BF_ICOLL_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
403 | #define BP_ICOLL_VERSION_MINOR 16 | ||
404 | #define BM_ICOLL_VERSION_MINOR 0xff0000 | ||
405 | #define BF_ICOLL_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
406 | #define BP_ICOLL_VERSION_STEP 0 | ||
407 | #define BM_ICOLL_VERSION_STEP 0xffff | ||
408 | #define BF_ICOLL_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
409 | |||
410 | #endif /* __HEADERGEN__STMP3700__ICOLL__H__ */ | ||