diff options
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h | 537 |
1 files changed, 537 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h b/firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h new file mode 100644 index 0000000000..ea34d27db2 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h | |||
@@ -0,0 +1,537 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__I2C__H__ | ||
24 | #define __HEADERGEN__STMP3700__I2C__H__ | ||
25 | |||
26 | #define REGS_I2C_BASE (0x80058000) | ||
27 | |||
28 | #define REGS_I2C_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_I2C_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_I2C_CTRL0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x0)) | ||
36 | #define HW_I2C_CTRL0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x4)) | ||
37 | #define HW_I2C_CTRL0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x8)) | ||
38 | #define HW_I2C_CTRL0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0xc)) | ||
39 | #define BP_I2C_CTRL0_SFTRST 31 | ||
40 | #define BM_I2C_CTRL0_SFTRST 0x80000000 | ||
41 | #define BV_I2C_CTRL0_SFTRST__RUN 0x0 | ||
42 | #define BV_I2C_CTRL0_SFTRST__RESET 0x1 | ||
43 | #define BF_I2C_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_I2C_CTRL0_SFTRST_V(v) ((BV_I2C_CTRL0_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_I2C_CTRL0_CLKGATE 30 | ||
46 | #define BM_I2C_CTRL0_CLKGATE 0x40000000 | ||
47 | #define BV_I2C_CTRL0_CLKGATE__RUN 0x0 | ||
48 | #define BV_I2C_CTRL0_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_I2C_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_I2C_CTRL0_CLKGATE_V(v) ((BV_I2C_CTRL0_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_I2C_CTRL0_RUN 29 | ||
52 | #define BM_I2C_CTRL0_RUN 0x20000000 | ||
53 | #define BV_I2C_CTRL0_RUN__HALT 0x0 | ||
54 | #define BV_I2C_CTRL0_RUN__RUN 0x1 | ||
55 | #define BF_I2C_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
56 | #define BF_I2C_CTRL0_RUN_V(v) ((BV_I2C_CTRL0_RUN__##v << 29) & 0x20000000) | ||
57 | #define BP_I2C_CTRL0_PRE_ACK 27 | ||
58 | #define BM_I2C_CTRL0_PRE_ACK 0x8000000 | ||
59 | #define BF_I2C_CTRL0_PRE_ACK(v) (((v) << 27) & 0x8000000) | ||
60 | #define BP_I2C_CTRL0_ACKNOWLEDGE 26 | ||
61 | #define BM_I2C_CTRL0_ACKNOWLEDGE 0x4000000 | ||
62 | #define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK 0x0 | ||
63 | #define BV_I2C_CTRL0_ACKNOWLEDGE__ACK 0x1 | ||
64 | #define BF_I2C_CTRL0_ACKNOWLEDGE(v) (((v) << 26) & 0x4000000) | ||
65 | #define BF_I2C_CTRL0_ACKNOWLEDGE_V(v) ((BV_I2C_CTRL0_ACKNOWLEDGE__##v << 26) & 0x4000000) | ||
66 | #define BP_I2C_CTRL0_SEND_NAK_ON_LAST 25 | ||
67 | #define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x2000000 | ||
68 | #define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT 0x0 | ||
69 | #define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT 0x1 | ||
70 | #define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v) (((v) << 25) & 0x2000000) | ||
71 | #define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(v) ((BV_I2C_CTRL0_SEND_NAK_ON_LAST__##v << 25) & 0x2000000) | ||
72 | #define BP_I2C_CTRL0_PIO_MODE 24 | ||
73 | #define BM_I2C_CTRL0_PIO_MODE 0x1000000 | ||
74 | #define BF_I2C_CTRL0_PIO_MODE(v) (((v) << 24) & 0x1000000) | ||
75 | #define BP_I2C_CTRL0_MULTI_MASTER 23 | ||
76 | #define BM_I2C_CTRL0_MULTI_MASTER 0x800000 | ||
77 | #define BV_I2C_CTRL0_MULTI_MASTER__SINGLE 0x0 | ||
78 | #define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE 0x1 | ||
79 | #define BF_I2C_CTRL0_MULTI_MASTER(v) (((v) << 23) & 0x800000) | ||
80 | #define BF_I2C_CTRL0_MULTI_MASTER_V(v) ((BV_I2C_CTRL0_MULTI_MASTER__##v << 23) & 0x800000) | ||
81 | #define BP_I2C_CTRL0_CLOCK_HELD 22 | ||
82 | #define BM_I2C_CTRL0_CLOCK_HELD 0x400000 | ||
83 | #define BV_I2C_CTRL0_CLOCK_HELD__RELEASE 0x0 | ||
84 | #define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW 0x1 | ||
85 | #define BF_I2C_CTRL0_CLOCK_HELD(v) (((v) << 22) & 0x400000) | ||
86 | #define BF_I2C_CTRL0_CLOCK_HELD_V(v) ((BV_I2C_CTRL0_CLOCK_HELD__##v << 22) & 0x400000) | ||
87 | #define BP_I2C_CTRL0_RETAIN_CLOCK 21 | ||
88 | #define BM_I2C_CTRL0_RETAIN_CLOCK 0x200000 | ||
89 | #define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE 0x0 | ||
90 | #define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW 0x1 | ||
91 | #define BF_I2C_CTRL0_RETAIN_CLOCK(v) (((v) << 21) & 0x200000) | ||
92 | #define BF_I2C_CTRL0_RETAIN_CLOCK_V(v) ((BV_I2C_CTRL0_RETAIN_CLOCK__##v << 21) & 0x200000) | ||
93 | #define BP_I2C_CTRL0_POST_SEND_STOP 20 | ||
94 | #define BM_I2C_CTRL0_POST_SEND_STOP 0x100000 | ||
95 | #define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP 0x0 | ||
96 | #define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP 0x1 | ||
97 | #define BF_I2C_CTRL0_POST_SEND_STOP(v) (((v) << 20) & 0x100000) | ||
98 | #define BF_I2C_CTRL0_POST_SEND_STOP_V(v) ((BV_I2C_CTRL0_POST_SEND_STOP__##v << 20) & 0x100000) | ||
99 | #define BP_I2C_CTRL0_PRE_SEND_START 19 | ||
100 | #define BM_I2C_CTRL0_PRE_SEND_START 0x80000 | ||
101 | #define BV_I2C_CTRL0_PRE_SEND_START__NO_START 0x0 | ||
102 | #define BV_I2C_CTRL0_PRE_SEND_START__SEND_START 0x1 | ||
103 | #define BF_I2C_CTRL0_PRE_SEND_START(v) (((v) << 19) & 0x80000) | ||
104 | #define BF_I2C_CTRL0_PRE_SEND_START_V(v) ((BV_I2C_CTRL0_PRE_SEND_START__##v << 19) & 0x80000) | ||
105 | #define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 18 | ||
106 | #define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 0x40000 | ||
107 | #define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0 | ||
108 | #define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED 0x1 | ||
109 | #define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v) (((v) << 18) & 0x40000) | ||
110 | #define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v) ((BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##v << 18) & 0x40000) | ||
111 | #define BP_I2C_CTRL0_MASTER_MODE 17 | ||
112 | #define BM_I2C_CTRL0_MASTER_MODE 0x20000 | ||
113 | #define BV_I2C_CTRL0_MASTER_MODE__SLAVE 0x0 | ||
114 | #define BV_I2C_CTRL0_MASTER_MODE__MASTER 0x1 | ||
115 | #define BF_I2C_CTRL0_MASTER_MODE(v) (((v) << 17) & 0x20000) | ||
116 | #define BF_I2C_CTRL0_MASTER_MODE_V(v) ((BV_I2C_CTRL0_MASTER_MODE__##v << 17) & 0x20000) | ||
117 | #define BP_I2C_CTRL0_DIRECTION 16 | ||
118 | #define BM_I2C_CTRL0_DIRECTION 0x10000 | ||
119 | #define BV_I2C_CTRL0_DIRECTION__RECEIVE 0x0 | ||
120 | #define BV_I2C_CTRL0_DIRECTION__TRANSMIT 0x1 | ||
121 | #define BF_I2C_CTRL0_DIRECTION(v) (((v) << 16) & 0x10000) | ||
122 | #define BF_I2C_CTRL0_DIRECTION_V(v) ((BV_I2C_CTRL0_DIRECTION__##v << 16) & 0x10000) | ||
123 | #define BP_I2C_CTRL0_XFER_COUNT 0 | ||
124 | #define BM_I2C_CTRL0_XFER_COUNT 0xffff | ||
125 | #define BF_I2C_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
126 | |||
127 | /** | ||
128 | * Register: HW_I2C_TIMING0 | ||
129 | * Address: 0x10 | ||
130 | * SCT: yes | ||
131 | */ | ||
132 | #define HW_I2C_TIMING0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x0)) | ||
133 | #define HW_I2C_TIMING0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x4)) | ||
134 | #define HW_I2C_TIMING0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x8)) | ||
135 | #define HW_I2C_TIMING0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0xc)) | ||
136 | #define BP_I2C_TIMING0_HIGH_COUNT 16 | ||
137 | #define BM_I2C_TIMING0_HIGH_COUNT 0x3ff0000 | ||
138 | #define BF_I2C_TIMING0_HIGH_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
139 | #define BP_I2C_TIMING0_RCV_COUNT 0 | ||
140 | #define BM_I2C_TIMING0_RCV_COUNT 0x3ff | ||
141 | #define BF_I2C_TIMING0_RCV_COUNT(v) (((v) << 0) & 0x3ff) | ||
142 | |||
143 | /** | ||
144 | * Register: HW_I2C_TIMING1 | ||
145 | * Address: 0x20 | ||
146 | * SCT: yes | ||
147 | */ | ||
148 | #define HW_I2C_TIMING1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x0)) | ||
149 | #define HW_I2C_TIMING1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x4)) | ||
150 | #define HW_I2C_TIMING1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x8)) | ||
151 | #define HW_I2C_TIMING1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0xc)) | ||
152 | #define BP_I2C_TIMING1_LOW_COUNT 16 | ||
153 | #define BM_I2C_TIMING1_LOW_COUNT 0x3ff0000 | ||
154 | #define BF_I2C_TIMING1_LOW_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
155 | #define BP_I2C_TIMING1_XMIT_COUNT 0 | ||
156 | #define BM_I2C_TIMING1_XMIT_COUNT 0x3ff | ||
157 | #define BF_I2C_TIMING1_XMIT_COUNT(v) (((v) << 0) & 0x3ff) | ||
158 | |||
159 | /** | ||
160 | * Register: HW_I2C_TIMING2 | ||
161 | * Address: 0x30 | ||
162 | * SCT: yes | ||
163 | */ | ||
164 | #define HW_I2C_TIMING2 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x0)) | ||
165 | #define HW_I2C_TIMING2_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x4)) | ||
166 | #define HW_I2C_TIMING2_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x8)) | ||
167 | #define HW_I2C_TIMING2_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0xc)) | ||
168 | #define BP_I2C_TIMING2_BUS_FREE 16 | ||
169 | #define BM_I2C_TIMING2_BUS_FREE 0x3ff0000 | ||
170 | #define BF_I2C_TIMING2_BUS_FREE(v) (((v) << 16) & 0x3ff0000) | ||
171 | #define BP_I2C_TIMING2_LEADIN_COUNT 0 | ||
172 | #define BM_I2C_TIMING2_LEADIN_COUNT 0x3ff | ||
173 | #define BF_I2C_TIMING2_LEADIN_COUNT(v) (((v) << 0) & 0x3ff) | ||
174 | |||
175 | /** | ||
176 | * Register: HW_I2C_CTRL1 | ||
177 | * Address: 0x40 | ||
178 | * SCT: yes | ||
179 | */ | ||
180 | #define HW_I2C_CTRL1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x0)) | ||
181 | #define HW_I2C_CTRL1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x4)) | ||
182 | #define HW_I2C_CTRL1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x8)) | ||
183 | #define HW_I2C_CTRL1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0xc)) | ||
184 | #define BP_I2C_CTRL1_BCAST_SLAVE_EN 24 | ||
185 | #define BM_I2C_CTRL1_BCAST_SLAVE_EN 0x1000000 | ||
186 | #define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST 0x0 | ||
187 | #define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST 0x1 | ||
188 | #define BF_I2C_CTRL1_BCAST_SLAVE_EN(v) (((v) << 24) & 0x1000000) | ||
189 | #define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(v) ((BV_I2C_CTRL1_BCAST_SLAVE_EN__##v << 24) & 0x1000000) | ||
190 | #define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE 16 | ||
191 | #define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE 0xff0000 | ||
192 | #define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) (((v) << 16) & 0xff0000) | ||
193 | #define BP_I2C_CTRL1_BUS_FREE_IRQ_EN 15 | ||
194 | #define BM_I2C_CTRL1_BUS_FREE_IRQ_EN 0x8000 | ||
195 | #define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED 0x0 | ||
196 | #define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED 0x1 | ||
197 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v) (((v) << 15) & 0x8000) | ||
198 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v) ((BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##v << 15) & 0x8000) | ||
199 | #define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 14 | ||
200 | #define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 0x4000 | ||
201 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED 0x0 | ||
202 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED 0x1 | ||
203 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
204 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v) ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##v << 14) & 0x4000) | ||
205 | #define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 13 | ||
206 | #define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 0x2000 | ||
207 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED 0x0 | ||
208 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED 0x1 | ||
209 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v) (((v) << 13) & 0x2000) | ||
210 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v) ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##v << 13) & 0x2000) | ||
211 | #define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 12 | ||
212 | #define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 0x1000 | ||
213 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED 0x0 | ||
214 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED 0x1 | ||
215 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v) (((v) << 12) & 0x1000) | ||
216 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v) ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##v << 12) & 0x1000) | ||
217 | #define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN 11 | ||
218 | #define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN 0x800 | ||
219 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED 0x0 | ||
220 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED 0x1 | ||
221 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v) (((v) << 11) & 0x800) | ||
222 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v) ((BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##v << 11) & 0x800) | ||
223 | #define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN 10 | ||
224 | #define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN 0x400 | ||
225 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED 0x0 | ||
226 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED 0x1 | ||
227 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v) (((v) << 10) & 0x400) | ||
228 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v) ((BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##v << 10) & 0x400) | ||
229 | #define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN 9 | ||
230 | #define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN 0x200 | ||
231 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED 0x0 | ||
232 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED 0x1 | ||
233 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v) (((v) << 9) & 0x200) | ||
234 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v) ((BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##v << 9) & 0x200) | ||
235 | #define BP_I2C_CTRL1_SLAVE_IRQ_EN 8 | ||
236 | #define BM_I2C_CTRL1_SLAVE_IRQ_EN 0x100 | ||
237 | #define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED 0x0 | ||
238 | #define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED 0x1 | ||
239 | #define BF_I2C_CTRL1_SLAVE_IRQ_EN(v) (((v) << 8) & 0x100) | ||
240 | #define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(v) ((BV_I2C_CTRL1_SLAVE_IRQ_EN__##v << 8) & 0x100) | ||
241 | #define BP_I2C_CTRL1_BUS_FREE_IRQ 7 | ||
242 | #define BM_I2C_CTRL1_BUS_FREE_IRQ 0x80 | ||
243 | #define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST 0x0 | ||
244 | #define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST 0x1 | ||
245 | #define BF_I2C_CTRL1_BUS_FREE_IRQ(v) (((v) << 7) & 0x80) | ||
246 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_V(v) ((BV_I2C_CTRL1_BUS_FREE_IRQ__##v << 7) & 0x80) | ||
247 | #define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 6 | ||
248 | #define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40 | ||
249 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST 0x0 | ||
250 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST 0x1 | ||
251 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v) (((v) << 6) & 0x40) | ||
252 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v) ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##v << 6) & 0x40) | ||
253 | #define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ 5 | ||
254 | #define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20 | ||
255 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST 0x0 | ||
256 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST 0x1 | ||
257 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v) (((v) << 5) & 0x20) | ||
258 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v) ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##v << 5) & 0x20) | ||
259 | #define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 4 | ||
260 | #define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10 | ||
261 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST 0x0 | ||
262 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST 0x1 | ||
263 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v) (((v) << 4) & 0x10) | ||
264 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v) ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##v << 4) & 0x10) | ||
265 | #define BP_I2C_CTRL1_EARLY_TERM_IRQ 3 | ||
266 | #define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x8 | ||
267 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST 0x0 | ||
268 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST 0x1 | ||
269 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ(v) (((v) << 3) & 0x8) | ||
270 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(v) ((BV_I2C_CTRL1_EARLY_TERM_IRQ__##v << 3) & 0x8) | ||
271 | #define BP_I2C_CTRL1_MASTER_LOSS_IRQ 2 | ||
272 | #define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x4 | ||
273 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST 0x0 | ||
274 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST 0x1 | ||
275 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v) (((v) << 2) & 0x4) | ||
276 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(v) ((BV_I2C_CTRL1_MASTER_LOSS_IRQ__##v << 2) & 0x4) | ||
277 | #define BP_I2C_CTRL1_SLAVE_STOP_IRQ 1 | ||
278 | #define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x2 | ||
279 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST 0x0 | ||
280 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST 0x1 | ||
281 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v) (((v) << 1) & 0x2) | ||
282 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(v) ((BV_I2C_CTRL1_SLAVE_STOP_IRQ__##v << 1) & 0x2) | ||
283 | #define BP_I2C_CTRL1_SLAVE_IRQ 0 | ||
284 | #define BM_I2C_CTRL1_SLAVE_IRQ 0x1 | ||
285 | #define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST 0x0 | ||
286 | #define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST 0x1 | ||
287 | #define BF_I2C_CTRL1_SLAVE_IRQ(v) (((v) << 0) & 0x1) | ||
288 | #define BF_I2C_CTRL1_SLAVE_IRQ_V(v) ((BV_I2C_CTRL1_SLAVE_IRQ__##v << 0) & 0x1) | ||
289 | |||
290 | /** | ||
291 | * Register: HW_I2C_STAT | ||
292 | * Address: 0x50 | ||
293 | * SCT: no | ||
294 | */ | ||
295 | #define HW_I2C_STAT (*(volatile unsigned long *)(REGS_I2C_BASE + 0x50)) | ||
296 | #define BP_I2C_STAT_MASTER_PRESENT 31 | ||
297 | #define BM_I2C_STAT_MASTER_PRESENT 0x80000000 | ||
298 | #define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE 0x0 | ||
299 | #define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE 0x1 | ||
300 | #define BF_I2C_STAT_MASTER_PRESENT(v) (((v) << 31) & 0x80000000) | ||
301 | #define BF_I2C_STAT_MASTER_PRESENT_V(v) ((BV_I2C_STAT_MASTER_PRESENT__##v << 31) & 0x80000000) | ||
302 | #define BP_I2C_STAT_SLAVE_PRESENT 30 | ||
303 | #define BM_I2C_STAT_SLAVE_PRESENT 0x40000000 | ||
304 | #define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE 0x0 | ||
305 | #define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE 0x1 | ||
306 | #define BF_I2C_STAT_SLAVE_PRESENT(v) (((v) << 30) & 0x40000000) | ||
307 | #define BF_I2C_STAT_SLAVE_PRESENT_V(v) ((BV_I2C_STAT_SLAVE_PRESENT__##v << 30) & 0x40000000) | ||
308 | #define BP_I2C_STAT_ANY_ENABLED_IRQ 29 | ||
309 | #define BM_I2C_STAT_ANY_ENABLED_IRQ 0x20000000 | ||
310 | #define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS 0x0 | ||
311 | #define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST 0x1 | ||
312 | #define BF_I2C_STAT_ANY_ENABLED_IRQ(v) (((v) << 29) & 0x20000000) | ||
313 | #define BF_I2C_STAT_ANY_ENABLED_IRQ_V(v) ((BV_I2C_STAT_ANY_ENABLED_IRQ__##v << 29) & 0x20000000) | ||
314 | #define BP_I2C_STAT_RCVD_SLAVE_ADDR 16 | ||
315 | #define BM_I2C_STAT_RCVD_SLAVE_ADDR 0xff0000 | ||
316 | #define BF_I2C_STAT_RCVD_SLAVE_ADDR(v) (((v) << 16) & 0xff0000) | ||
317 | #define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO 15 | ||
318 | #define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO 0x8000 | ||
319 | #define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED 0x0 | ||
320 | #define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO 0x1 | ||
321 | #define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v) (((v) << 15) & 0x8000) | ||
322 | #define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v) ((BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##v << 15) & 0x8000) | ||
323 | #define BP_I2C_STAT_SLAVE_FOUND 14 | ||
324 | #define BM_I2C_STAT_SLAVE_FOUND 0x4000 | ||
325 | #define BV_I2C_STAT_SLAVE_FOUND__IDLE 0x0 | ||
326 | #define BV_I2C_STAT_SLAVE_FOUND__WAITING 0x1 | ||
327 | #define BF_I2C_STAT_SLAVE_FOUND(v) (((v) << 14) & 0x4000) | ||
328 | #define BF_I2C_STAT_SLAVE_FOUND_V(v) ((BV_I2C_STAT_SLAVE_FOUND__##v << 14) & 0x4000) | ||
329 | #define BP_I2C_STAT_SLAVE_SEARCHING 13 | ||
330 | #define BM_I2C_STAT_SLAVE_SEARCHING 0x2000 | ||
331 | #define BV_I2C_STAT_SLAVE_SEARCHING__IDLE 0x0 | ||
332 | #define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE 0x1 | ||
333 | #define BF_I2C_STAT_SLAVE_SEARCHING(v) (((v) << 13) & 0x2000) | ||
334 | #define BF_I2C_STAT_SLAVE_SEARCHING_V(v) ((BV_I2C_STAT_SLAVE_SEARCHING__##v << 13) & 0x2000) | ||
335 | #define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT 12 | ||
336 | #define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT 0x1000 | ||
337 | #define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE 0x0 | ||
338 | #define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING 0x1 | ||
339 | #define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v) (((v) << 12) & 0x1000) | ||
340 | #define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v) ((BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##v << 12) & 0x1000) | ||
341 | #define BP_I2C_STAT_BUS_BUSY 11 | ||
342 | #define BM_I2C_STAT_BUS_BUSY 0x800 | ||
343 | #define BV_I2C_STAT_BUS_BUSY__IDLE 0x0 | ||
344 | #define BV_I2C_STAT_BUS_BUSY__BUSY 0x1 | ||
345 | #define BF_I2C_STAT_BUS_BUSY(v) (((v) << 11) & 0x800) | ||
346 | #define BF_I2C_STAT_BUS_BUSY_V(v) ((BV_I2C_STAT_BUS_BUSY__##v << 11) & 0x800) | ||
347 | #define BP_I2C_STAT_CLK_GEN_BUSY 10 | ||
348 | #define BM_I2C_STAT_CLK_GEN_BUSY 0x400 | ||
349 | #define BV_I2C_STAT_CLK_GEN_BUSY__IDLE 0x0 | ||
350 | #define BV_I2C_STAT_CLK_GEN_BUSY__BUSY 0x1 | ||
351 | #define BF_I2C_STAT_CLK_GEN_BUSY(v) (((v) << 10) & 0x400) | ||
352 | #define BF_I2C_STAT_CLK_GEN_BUSY_V(v) ((BV_I2C_STAT_CLK_GEN_BUSY__##v << 10) & 0x400) | ||
353 | #define BP_I2C_STAT_DATA_ENGINE_BUSY 9 | ||
354 | #define BM_I2C_STAT_DATA_ENGINE_BUSY 0x200 | ||
355 | #define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE 0x0 | ||
356 | #define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY 0x1 | ||
357 | #define BF_I2C_STAT_DATA_ENGINE_BUSY(v) (((v) << 9) & 0x200) | ||
358 | #define BF_I2C_STAT_DATA_ENGINE_BUSY_V(v) ((BV_I2C_STAT_DATA_ENGINE_BUSY__##v << 9) & 0x200) | ||
359 | #define BP_I2C_STAT_SLAVE_BUSY 8 | ||
360 | #define BM_I2C_STAT_SLAVE_BUSY 0x100 | ||
361 | #define BV_I2C_STAT_SLAVE_BUSY__IDLE 0x0 | ||
362 | #define BV_I2C_STAT_SLAVE_BUSY__BUSY 0x1 | ||
363 | #define BF_I2C_STAT_SLAVE_BUSY(v) (((v) << 8) & 0x100) | ||
364 | #define BF_I2C_STAT_SLAVE_BUSY_V(v) ((BV_I2C_STAT_SLAVE_BUSY__##v << 8) & 0x100) | ||
365 | #define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY 7 | ||
366 | #define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY 0x80 | ||
367 | #define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
368 | #define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST 0x1 | ||
369 | #define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v) (((v) << 7) & 0x80) | ||
370 | #define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##v << 7) & 0x80) | ||
371 | #define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 6 | ||
372 | #define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 0x40 | ||
373 | #define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
374 | #define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST 0x1 | ||
375 | #define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v) (((v) << 6) & 0x40) | ||
376 | #define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##v << 6) & 0x40) | ||
377 | #define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 5 | ||
378 | #define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 0x20 | ||
379 | #define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
380 | #define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST 0x1 | ||
381 | #define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v) (((v) << 5) & 0x20) | ||
382 | #define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##v << 5) & 0x20) | ||
383 | #define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 4 | ||
384 | #define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 0x10 | ||
385 | #define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
386 | #define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST 0x1 | ||
387 | #define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v) (((v) << 4) & 0x10) | ||
388 | #define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##v << 4) & 0x10) | ||
389 | #define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 3 | ||
390 | #define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 0x8 | ||
391 | #define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
392 | #define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST 0x1 | ||
393 | #define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v) (((v) << 3) & 0x8) | ||
394 | #define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##v << 3) & 0x8) | ||
395 | #define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 2 | ||
396 | #define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 0x4 | ||
397 | #define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
398 | #define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST 0x1 | ||
399 | #define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v) (((v) << 2) & 0x4) | ||
400 | #define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##v << 2) & 0x4) | ||
401 | #define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 1 | ||
402 | #define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 0x2 | ||
403 | #define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
404 | #define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST 0x1 | ||
405 | #define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v) (((v) << 1) & 0x2) | ||
406 | #define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##v << 1) & 0x2) | ||
407 | #define BP_I2C_STAT_SLAVE_IRQ_SUMMARY 0 | ||
408 | #define BM_I2C_STAT_SLAVE_IRQ_SUMMARY 0x1 | ||
409 | #define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
410 | #define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST 0x1 | ||
411 | #define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v) (((v) << 0) & 0x1) | ||
412 | #define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##v << 0) & 0x1) | ||
413 | |||
414 | /** | ||
415 | * Register: HW_I2C_DATA | ||
416 | * Address: 0x60 | ||
417 | * SCT: no | ||
418 | */ | ||
419 | #define HW_I2C_DATA (*(volatile unsigned long *)(REGS_I2C_BASE + 0x60)) | ||
420 | #define BP_I2C_DATA_DATA 0 | ||
421 | #define BM_I2C_DATA_DATA 0xffffffff | ||
422 | #define BF_I2C_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
423 | |||
424 | /** | ||
425 | * Register: HW_I2C_DEBUG0 | ||
426 | * Address: 0x70 | ||
427 | * SCT: yes | ||
428 | */ | ||
429 | #define HW_I2C_DEBUG0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x0)) | ||
430 | #define HW_I2C_DEBUG0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x4)) | ||
431 | #define HW_I2C_DEBUG0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x8)) | ||
432 | #define HW_I2C_DEBUG0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0xc)) | ||
433 | #define BP_I2C_DEBUG0_DMAREQ 31 | ||
434 | #define BM_I2C_DEBUG0_DMAREQ 0x80000000 | ||
435 | #define BF_I2C_DEBUG0_DMAREQ(v) (((v) << 31) & 0x80000000) | ||
436 | #define BP_I2C_DEBUG0_DMAENDCMD 30 | ||
437 | #define BM_I2C_DEBUG0_DMAENDCMD 0x40000000 | ||
438 | #define BF_I2C_DEBUG0_DMAENDCMD(v) (((v) << 30) & 0x40000000) | ||
439 | #define BP_I2C_DEBUG0_DMAKICK 29 | ||
440 | #define BM_I2C_DEBUG0_DMAKICK 0x20000000 | ||
441 | #define BF_I2C_DEBUG0_DMAKICK(v) (((v) << 29) & 0x20000000) | ||
442 | #define BP_I2C_DEBUG0_TBD 26 | ||
443 | #define BM_I2C_DEBUG0_TBD 0x1c000000 | ||
444 | #define BF_I2C_DEBUG0_TBD(v) (((v) << 26) & 0x1c000000) | ||
445 | #define BP_I2C_DEBUG0_DMA_STATE 16 | ||
446 | #define BM_I2C_DEBUG0_DMA_STATE 0x3ff0000 | ||
447 | #define BF_I2C_DEBUG0_DMA_STATE(v) (((v) << 16) & 0x3ff0000) | ||
448 | #define BP_I2C_DEBUG0_START_TOGGLE 15 | ||
449 | #define BM_I2C_DEBUG0_START_TOGGLE 0x8000 | ||
450 | #define BF_I2C_DEBUG0_START_TOGGLE(v) (((v) << 15) & 0x8000) | ||
451 | #define BP_I2C_DEBUG0_STOP_TOGGLE 14 | ||
452 | #define BM_I2C_DEBUG0_STOP_TOGGLE 0x4000 | ||
453 | #define BF_I2C_DEBUG0_STOP_TOGGLE(v) (((v) << 14) & 0x4000) | ||
454 | #define BP_I2C_DEBUG0_GRAB_TOGGLE 13 | ||
455 | #define BM_I2C_DEBUG0_GRAB_TOGGLE 0x2000 | ||
456 | #define BF_I2C_DEBUG0_GRAB_TOGGLE(v) (((v) << 13) & 0x2000) | ||
457 | #define BP_I2C_DEBUG0_CHANGE_TOGGLE 12 | ||
458 | #define BM_I2C_DEBUG0_CHANGE_TOGGLE 0x1000 | ||
459 | #define BF_I2C_DEBUG0_CHANGE_TOGGLE(v) (((v) << 12) & 0x1000) | ||
460 | #define BP_I2C_DEBUG0_TESTMODE 11 | ||
461 | #define BM_I2C_DEBUG0_TESTMODE 0x800 | ||
462 | #define BF_I2C_DEBUG0_TESTMODE(v) (((v) << 11) & 0x800) | ||
463 | #define BP_I2C_DEBUG0_SLAVE_HOLD_CLK 10 | ||
464 | #define BM_I2C_DEBUG0_SLAVE_HOLD_CLK 0x400 | ||
465 | #define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v) (((v) << 10) & 0x400) | ||
466 | #define BP_I2C_DEBUG0_SLAVE_STATE 0 | ||
467 | #define BM_I2C_DEBUG0_SLAVE_STATE 0x3ff | ||
468 | #define BF_I2C_DEBUG0_SLAVE_STATE(v) (((v) << 0) & 0x3ff) | ||
469 | |||
470 | /** | ||
471 | * Register: HW_I2C_DEBUG1 | ||
472 | * Address: 0x80 | ||
473 | * SCT: yes | ||
474 | */ | ||
475 | #define HW_I2C_DEBUG1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x0)) | ||
476 | #define HW_I2C_DEBUG1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x4)) | ||
477 | #define HW_I2C_DEBUG1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x8)) | ||
478 | #define HW_I2C_DEBUG1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0xc)) | ||
479 | #define BP_I2C_DEBUG1_I2C_CLK_IN 31 | ||
480 | #define BM_I2C_DEBUG1_I2C_CLK_IN 0x80000000 | ||
481 | #define BF_I2C_DEBUG1_I2C_CLK_IN(v) (((v) << 31) & 0x80000000) | ||
482 | #define BP_I2C_DEBUG1_I2C_DATA_IN 30 | ||
483 | #define BM_I2C_DEBUG1_I2C_DATA_IN 0x40000000 | ||
484 | #define BF_I2C_DEBUG1_I2C_DATA_IN(v) (((v) << 30) & 0x40000000) | ||
485 | #define BP_I2C_DEBUG1_DMA_BYTE_ENABLES 24 | ||
486 | #define BM_I2C_DEBUG1_DMA_BYTE_ENABLES 0xf000000 | ||
487 | #define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v) (((v) << 24) & 0xf000000) | ||
488 | #define BP_I2C_DEBUG1_CLK_GEN_STATE 16 | ||
489 | #define BM_I2C_DEBUG1_CLK_GEN_STATE 0x7f0000 | ||
490 | #define BF_I2C_DEBUG1_CLK_GEN_STATE(v) (((v) << 16) & 0x7f0000) | ||
491 | #define BP_I2C_DEBUG1_LST_MODE 9 | ||
492 | #define BM_I2C_DEBUG1_LST_MODE 0x600 | ||
493 | #define BV_I2C_DEBUG1_LST_MODE__BCAST 0x0 | ||
494 | #define BV_I2C_DEBUG1_LST_MODE__MY_WRITE 0x1 | ||
495 | #define BV_I2C_DEBUG1_LST_MODE__MY_READ 0x2 | ||
496 | #define BV_I2C_DEBUG1_LST_MODE__NOT_ME 0x3 | ||
497 | #define BF_I2C_DEBUG1_LST_MODE(v) (((v) << 9) & 0x600) | ||
498 | #define BF_I2C_DEBUG1_LST_MODE_V(v) ((BV_I2C_DEBUG1_LST_MODE__##v << 9) & 0x600) | ||
499 | #define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST 8 | ||
500 | #define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST 0x100 | ||
501 | #define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v) (((v) << 8) & 0x100) | ||
502 | #define BP_I2C_DEBUG1_FORCE_CLK_ON 5 | ||
503 | #define BM_I2C_DEBUG1_FORCE_CLK_ON 0x20 | ||
504 | #define BF_I2C_DEBUG1_FORCE_CLK_ON(v) (((v) << 5) & 0x20) | ||
505 | #define BP_I2C_DEBUG1_FORCE_CLK_IDLE 4 | ||
506 | #define BM_I2C_DEBUG1_FORCE_CLK_IDLE 0x10 | ||
507 | #define BF_I2C_DEBUG1_FORCE_CLK_IDLE(v) (((v) << 4) & 0x10) | ||
508 | #define BP_I2C_DEBUG1_FORCE_ARB_LOSS 3 | ||
509 | #define BM_I2C_DEBUG1_FORCE_ARB_LOSS 0x8 | ||
510 | #define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v) (((v) << 3) & 0x8) | ||
511 | #define BP_I2C_DEBUG1_FORCE_RCV_ACK 2 | ||
512 | #define BM_I2C_DEBUG1_FORCE_RCV_ACK 0x4 | ||
513 | #define BF_I2C_DEBUG1_FORCE_RCV_ACK(v) (((v) << 2) & 0x4) | ||
514 | #define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE 1 | ||
515 | #define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE 0x2 | ||
516 | #define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v) (((v) << 1) & 0x2) | ||
517 | #define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE 0 | ||
518 | #define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE 0x1 | ||
519 | #define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v) (((v) << 0) & 0x1) | ||
520 | |||
521 | /** | ||
522 | * Register: HW_I2C_VERSION | ||
523 | * Address: 0x90 | ||
524 | * SCT: no | ||
525 | */ | ||
526 | #define HW_I2C_VERSION (*(volatile unsigned long *)(REGS_I2C_BASE + 0x90)) | ||
527 | #define BP_I2C_VERSION_MAJOR 24 | ||
528 | #define BM_I2C_VERSION_MAJOR 0xff000000 | ||
529 | #define BF_I2C_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
530 | #define BP_I2C_VERSION_MINOR 16 | ||
531 | #define BM_I2C_VERSION_MINOR 0xff0000 | ||
532 | #define BF_I2C_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
533 | #define BP_I2C_VERSION_STEP 0 | ||
534 | #define BM_I2C_VERSION_STEP 0xffff | ||
535 | #define BF_I2C_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
536 | |||
537 | #endif /* __HEADERGEN__STMP3700__I2C__H__ */ | ||