diff options
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3600')
30 files changed, 9147 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-anatop.h b/firmware/target/arm/imx233/regs/stmp3600/regs-anatop.h new file mode 100644 index 0000000000..d18835f044 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-anatop.h | |||
| @@ -0,0 +1,82 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__ANATOP__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__ANATOP__H__ | ||
| 25 | |||
| 26 | #define REGS_ANATOP_BASE (0x8003c200) | ||
| 27 | |||
| 28 | #define REGS_ANATOP_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_ANATOP_PROBE_OUTPUT_SELECT | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_ANATOP_PROBE_OUTPUT_SELECT (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_ANATOP_PROBE_OUTPUT_SELECT_SET (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_ANATOP_PROBE_OUTPUT_SELECT_CLR (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_ANATOP_PROBE_OUTPUT_SELECT_TOG (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT 0 | ||
| 40 | #define BM_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT 0xffffffff | ||
| 41 | #define BF_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT(v) (((v) << 0) & 0xffffffff) | ||
| 42 | |||
| 43 | /** | ||
| 44 | * Register: HW_ANATOP_PROBE_INPUT_SELECT | ||
| 45 | * Address: 0x10 | ||
| 46 | * SCT: yes | ||
| 47 | */ | ||
| 48 | #define HW_ANATOP_PROBE_INPUT_SELECT (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0x0)) | ||
| 49 | #define HW_ANATOP_PROBE_INPUT_SELECT_SET (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0x4)) | ||
| 50 | #define HW_ANATOP_PROBE_INPUT_SELECT_CLR (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0x8)) | ||
| 51 | #define HW_ANATOP_PROBE_INPUT_SELECT_TOG (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0xc)) | ||
| 52 | #define BP_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT 0 | ||
| 53 | #define BM_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT 0xffffffff | ||
| 54 | #define BF_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT(v) (((v) << 0) & 0xffffffff) | ||
| 55 | |||
| 56 | /** | ||
| 57 | * Register: HW_ANATOP_PROBE_DATA | ||
| 58 | * Address: 0x20 | ||
| 59 | * SCT: yes | ||
| 60 | */ | ||
| 61 | #define HW_ANATOP_PROBE_DATA (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0x0)) | ||
| 62 | #define HW_ANATOP_PROBE_DATA_SET (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0x4)) | ||
| 63 | #define HW_ANATOP_PROBE_DATA_CLR (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0x8)) | ||
| 64 | #define HW_ANATOP_PROBE_DATA_TOG (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0xc)) | ||
| 65 | #define BP_ANATOP_PROBE_DATA_DATA 0 | ||
| 66 | #define BM_ANATOP_PROBE_DATA_DATA 0xffffffff | ||
| 67 | #define BF_ANATOP_PROBE_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 68 | |||
| 69 | /** | ||
| 70 | * Register: HW_ANATOP_PROBE_DIGTOP_SELECT | ||
| 71 | * Address: 0x30 | ||
| 72 | * SCT: yes | ||
| 73 | */ | ||
| 74 | #define HW_ANATOP_PROBE_DIGTOP_SELECT (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0x0)) | ||
| 75 | #define HW_ANATOP_PROBE_DIGTOP_SELECT_SET (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0x4)) | ||
| 76 | #define HW_ANATOP_PROBE_DIGTOP_SELECT_CLR (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0x8)) | ||
| 77 | #define HW_ANATOP_PROBE_DIGTOP_SELECT_TOG (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0xc)) | ||
| 78 | #define BP_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT 0 | ||
| 79 | #define BM_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT 0xffffffff | ||
| 80 | #define BF_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT(v) (((v) << 0) & 0xffffffff) | ||
| 81 | |||
| 82 | #endif /* __HEADERGEN__STMP3600__ANATOP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h b/firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h new file mode 100644 index 0000000000..ab8d9e6deb --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h | |||
| @@ -0,0 +1,288 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.4.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__APBH__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__APBH__H__ | ||
| 25 | |||
| 26 | #define REGS_APBH_BASE (0x80004000) | ||
| 27 | |||
| 28 | #define REGS_APBH_VERSION "2.4.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_APBH_CTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_APBH_CTRL0 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_APBH_CTRL0_SET (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_APBH_CTRL0_CLR (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_APBH_CTRL0_TOG (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_APBH_CTRL0_SFTRST 31 | ||
| 40 | #define BM_APBH_CTRL0_SFTRST 0x80000000 | ||
| 41 | #define BF_APBH_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_APBH_CTRL0_CLKGATE 30 | ||
| 43 | #define BM_APBH_CTRL0_CLKGATE 0x40000000 | ||
| 44 | #define BF_APBH_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_APBH_CTRL0_RESET_CHANNEL 16 | ||
| 46 | #define BM_APBH_CTRL0_RESET_CHANNEL 0xff0000 | ||
| 47 | #define BV_APBH_CTRL0_RESET_CHANNEL__HWECC 0x1 | ||
| 48 | #define BV_APBH_CTRL0_RESET_CHANNEL__SSP 0x2 | ||
| 49 | #define BV_APBH_CTRL0_RESET_CHANNEL__SRC 0x4 | ||
| 50 | #define BV_APBH_CTRL0_RESET_CHANNEL__DEST 0x8 | ||
| 51 | #define BV_APBH_CTRL0_RESET_CHANNEL__ATA 0x10 | ||
| 52 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND0 0x10 | ||
| 53 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND1 0x20 | ||
| 54 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND2 0x30 | ||
| 55 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND3 0x40 | ||
| 56 | #define BF_APBH_CTRL0_RESET_CHANNEL(v) (((v) << 16) & 0xff0000) | ||
| 57 | #define BF_APBH_CTRL0_RESET_CHANNEL_V(v) ((BV_APBH_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000) | ||
| 58 | #define BP_APBH_CTRL0_CLKGATE_CHANNEL 8 | ||
| 59 | #define BM_APBH_CTRL0_CLKGATE_CHANNEL 0xff00 | ||
| 60 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__HWECC 0x1 | ||
| 61 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP 0x2 | ||
| 62 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__SRC 0x4 | ||
| 63 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__DEST 0x8 | ||
| 64 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA 0x10 | ||
| 65 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x10 | ||
| 66 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x20 | ||
| 67 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x30 | ||
| 68 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x40 | ||
| 69 | #define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) (((v) << 8) & 0xff00) | ||
| 70 | #define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(v) ((BV_APBH_CTRL0_CLKGATE_CHANNEL__##v << 8) & 0xff00) | ||
| 71 | #define BP_APBH_CTRL0_FREEZE_CHANNEL 0 | ||
| 72 | #define BM_APBH_CTRL0_FREEZE_CHANNEL 0xff | ||
| 73 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__HWECC 0x1 | ||
| 74 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP 0x2 | ||
| 75 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__SRC 0x4 | ||
| 76 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__DEST 0x8 | ||
| 77 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA 0x10 | ||
| 78 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0 0x10 | ||
| 79 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1 0x20 | ||
| 80 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2 0x30 | ||
| 81 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3 0x40 | ||
| 82 | #define BF_APBH_CTRL0_FREEZE_CHANNEL(v) (((v) << 0) & 0xff) | ||
| 83 | #define BF_APBH_CTRL0_FREEZE_CHANNEL_V(v) ((BV_APBH_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff) | ||
| 84 | |||
| 85 | /** | ||
| 86 | * Register: HW_APBH_CTRL1 | ||
| 87 | * Address: 0x10 | ||
| 88 | * SCT: yes | ||
| 89 | */ | ||
| 90 | #define HW_APBH_CTRL1 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x0)) | ||
| 91 | #define HW_APBH_CTRL1_SET (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x4)) | ||
| 92 | #define HW_APBH_CTRL1_CLR (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x8)) | ||
| 93 | #define HW_APBH_CTRL1_TOG (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0xc)) | ||
| 94 | #define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN 16 | ||
| 95 | #define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN 0xff0000 | ||
| 96 | #define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 16) & 0xff0000) | ||
| 97 | #define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ 0 | ||
| 98 | #define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ 0xff | ||
| 99 | #define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v) (((v) << 0) & 0xff) | ||
| 100 | |||
| 101 | /** | ||
| 102 | * Register: HW_APBH_DEVSEL | ||
| 103 | * Address: 0x20 | ||
| 104 | * SCT: no | ||
| 105 | */ | ||
| 106 | #define HW_APBH_DEVSEL (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20)) | ||
| 107 | #define BP_APBH_DEVSEL_CH7 28 | ||
| 108 | #define BM_APBH_DEVSEL_CH7 0xf0000000 | ||
| 109 | #define BF_APBH_DEVSEL_CH7(v) (((v) << 28) & 0xf0000000) | ||
| 110 | #define BP_APBH_DEVSEL_CH6 24 | ||
| 111 | #define BM_APBH_DEVSEL_CH6 0xf000000 | ||
| 112 | #define BF_APBH_DEVSEL_CH6(v) (((v) << 24) & 0xf000000) | ||
| 113 | #define BP_APBH_DEVSEL_CH5 20 | ||
| 114 | #define BM_APBH_DEVSEL_CH5 0xf00000 | ||
| 115 | #define BF_APBH_DEVSEL_CH5(v) (((v) << 20) & 0xf00000) | ||
| 116 | #define BP_APBH_DEVSEL_CH4 16 | ||
| 117 | #define BM_APBH_DEVSEL_CH4 0xf0000 | ||
| 118 | #define BF_APBH_DEVSEL_CH4(v) (((v) << 16) & 0xf0000) | ||
| 119 | #define BP_APBH_DEVSEL_CH3 12 | ||
| 120 | #define BM_APBH_DEVSEL_CH3 0xf000 | ||
| 121 | #define BF_APBH_DEVSEL_CH3(v) (((v) << 12) & 0xf000) | ||
| 122 | #define BP_APBH_DEVSEL_CH2 8 | ||
| 123 | #define BM_APBH_DEVSEL_CH2 0xf00 | ||
| 124 | #define BF_APBH_DEVSEL_CH2(v) (((v) << 8) & 0xf00) | ||
| 125 | #define BP_APBH_DEVSEL_CH1 4 | ||
| 126 | #define BM_APBH_DEVSEL_CH1 0xf0 | ||
| 127 | #define BF_APBH_DEVSEL_CH1(v) (((v) << 4) & 0xf0) | ||
| 128 | #define BP_APBH_DEVSEL_CH0 0 | ||
| 129 | #define BM_APBH_DEVSEL_CH0 0xf | ||
| 130 | #define BF_APBH_DEVSEL_CH0(v) (((v) << 0) & 0xf) | ||
| 131 | |||
| 132 | /** | ||
| 133 | * Register: HW_APBH_CHn_DEBUG2 | ||
| 134 | * Address: 0x90+n*0x70 | ||
| 135 | * SCT: no | ||
| 136 | */ | ||
| 137 | #define HW_APBH_CHn_DEBUG2(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x90+(n)*0x70)) | ||
| 138 | #define BP_APBH_CHn_DEBUG2_APB_BYTES 16 | ||
| 139 | #define BM_APBH_CHn_DEBUG2_APB_BYTES 0xffff0000 | ||
| 140 | #define BF_APBH_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000) | ||
| 141 | #define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 | ||
| 142 | #define BM_APBH_CHn_DEBUG2_AHB_BYTES 0xffff | ||
| 143 | #define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff) | ||
| 144 | |||
| 145 | /** | ||
| 146 | * Register: HW_APBH_CHn_CURCMDAR | ||
| 147 | * Address: 0x30+n*0x70 | ||
| 148 | * SCT: no | ||
| 149 | */ | ||
| 150 | #define HW_APBH_CHn_CURCMDAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x30+(n)*0x70)) | ||
| 151 | #define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 | ||
| 152 | #define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xffffffff | ||
| 153 | #define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 154 | |||
| 155 | /** | ||
| 156 | * Register: HW_APBH_CHn_BAR | ||
| 157 | * Address: 0x60+n*0x70 | ||
| 158 | * SCT: no | ||
| 159 | */ | ||
| 160 | #define HW_APBH_CHn_BAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x60+(n)*0x70)) | ||
| 161 | #define BP_APBH_CHn_BAR_ADDRESS 0 | ||
| 162 | #define BM_APBH_CHn_BAR_ADDRESS 0xffffffff | ||
| 163 | #define BF_APBH_CHn_BAR_ADDRESS(v) (((v) << 0) & 0xffffffff) | ||
| 164 | |||
| 165 | /** | ||
| 166 | * Register: HW_APBH_CHn_CMD | ||
| 167 | * Address: 0x50+n*0x70 | ||
| 168 | * SCT: no | ||
| 169 | */ | ||
| 170 | #define HW_APBH_CHn_CMD(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x50+(n)*0x70)) | ||
| 171 | #define BP_APBH_CHn_CMD_XFER_COUNT 16 | ||
| 172 | #define BM_APBH_CHn_CMD_XFER_COUNT 0xffff0000 | ||
| 173 | #define BF_APBH_CHn_CMD_XFER_COUNT(v) (((v) << 16) & 0xffff0000) | ||
| 174 | #define BP_APBH_CHn_CMD_CMDWORDS 12 | ||
| 175 | #define BM_APBH_CHn_CMD_CMDWORDS 0xf000 | ||
| 176 | #define BF_APBH_CHn_CMD_CMDWORDS(v) (((v) << 12) & 0xf000) | ||
| 177 | #define BP_APBH_CHn_CMD_WAIT4ENDCMD 7 | ||
| 178 | #define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x80 | ||
| 179 | #define BF_APBH_CHn_CMD_WAIT4ENDCMD(v) (((v) << 7) & 0x80) | ||
| 180 | #define BP_APBH_CHn_CMD_SEMAPHORE 6 | ||
| 181 | #define BM_APBH_CHn_CMD_SEMAPHORE 0x40 | ||
| 182 | #define BF_APBH_CHn_CMD_SEMAPHORE(v) (((v) << 6) & 0x40) | ||
| 183 | #define BP_APBH_CHn_CMD_NANDWAIT4READY 5 | ||
| 184 | #define BM_APBH_CHn_CMD_NANDWAIT4READY 0x20 | ||
| 185 | #define BF_APBH_CHn_CMD_NANDWAIT4READY(v) (((v) << 5) & 0x20) | ||
| 186 | #define BP_APBH_CHn_CMD_NANDLOCK 4 | ||
| 187 | #define BM_APBH_CHn_CMD_NANDLOCK 0x10 | ||
| 188 | #define BF_APBH_CHn_CMD_NANDLOCK(v) (((v) << 4) & 0x10) | ||
| 189 | #define BP_APBH_CHn_CMD_IRQONCMPLT 3 | ||
| 190 | #define BM_APBH_CHn_CMD_IRQONCMPLT 0x8 | ||
| 191 | #define BF_APBH_CHn_CMD_IRQONCMPLT(v) (((v) << 3) & 0x8) | ||
| 192 | #define BP_APBH_CHn_CMD_CHAIN 2 | ||
| 193 | #define BM_APBH_CHn_CMD_CHAIN 0x4 | ||
| 194 | #define BF_APBH_CHn_CMD_CHAIN(v) (((v) << 2) & 0x4) | ||
| 195 | #define BP_APBH_CHn_CMD_COMMAND 0 | ||
| 196 | #define BM_APBH_CHn_CMD_COMMAND 0x3 | ||
| 197 | #define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 | ||
| 198 | #define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 | ||
| 199 | #define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 | ||
| 200 | #define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 | ||
| 201 | #define BF_APBH_CHn_CMD_COMMAND(v) (((v) << 0) & 0x3) | ||
| 202 | #define BF_APBH_CHn_CMD_COMMAND_V(v) ((BV_APBH_CHn_CMD_COMMAND__##v << 0) & 0x3) | ||
| 203 | |||
| 204 | /** | ||
| 205 | * Register: HW_APBH_CHn_NXTCMDAR | ||
| 206 | * Address: 0x40+n*0x70 | ||
| 207 | * SCT: no | ||
| 208 | */ | ||
| 209 | #define HW_APBH_CHn_NXTCMDAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x40+(n)*0x70)) | ||
| 210 | #define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 | ||
| 211 | #define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xffffffff | ||
| 212 | #define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 213 | |||
| 214 | /** | ||
| 215 | * Register: HW_APBH_CHn_SEMA | ||
| 216 | * Address: 0x70+n*0x70 | ||
| 217 | * SCT: no | ||
| 218 | */ | ||
| 219 | #define HW_APBH_CHn_SEMA(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x70+(n)*0x70)) | ||
| 220 | #define BP_APBH_CHn_SEMA_PHORE 16 | ||
| 221 | #define BM_APBH_CHn_SEMA_PHORE 0xff0000 | ||
| 222 | #define BF_APBH_CHn_SEMA_PHORE(v) (((v) << 16) & 0xff0000) | ||
| 223 | #define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 | ||
| 224 | #define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0xff | ||
| 225 | #define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) (((v) << 0) & 0xff) | ||
| 226 | |||
| 227 | /** | ||
| 228 | * Register: HW_APBH_CHn_DEBUG1 | ||
| 229 | * Address: 0x80+n*0x70 | ||
| 230 | * SCT: no | ||
| 231 | */ | ||
| 232 | #define HW_APBH_CHn_DEBUG1(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x80+(n)*0x70)) | ||
| 233 | #define BP_APBH_CHn_DEBUG1_REQ 31 | ||
| 234 | #define BM_APBH_CHn_DEBUG1_REQ 0x80000000 | ||
| 235 | #define BF_APBH_CHn_DEBUG1_REQ(v) (((v) << 31) & 0x80000000) | ||
| 236 | #define BP_APBH_CHn_DEBUG1_BURST 30 | ||
| 237 | #define BM_APBH_CHn_DEBUG1_BURST 0x40000000 | ||
| 238 | #define BF_APBH_CHn_DEBUG1_BURST(v) (((v) << 30) & 0x40000000) | ||
| 239 | #define BP_APBH_CHn_DEBUG1_KICK 29 | ||
| 240 | #define BM_APBH_CHn_DEBUG1_KICK 0x20000000 | ||
| 241 | #define BF_APBH_CHn_DEBUG1_KICK(v) (((v) << 29) & 0x20000000) | ||
| 242 | #define BP_APBH_CHn_DEBUG1_END 28 | ||
| 243 | #define BM_APBH_CHn_DEBUG1_END 0x10000000 | ||
| 244 | #define BF_APBH_CHn_DEBUG1_END(v) (((v) << 28) & 0x10000000) | ||
| 245 | #define BP_APBH_CHn_DEBUG1_RSVD2 25 | ||
| 246 | #define BM_APBH_CHn_DEBUG1_RSVD2 0xe000000 | ||
| 247 | #define BF_APBH_CHn_DEBUG1_RSVD2(v) (((v) << 25) & 0xe000000) | ||
| 248 | #define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 24 | ||
| 249 | #define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x1000000 | ||
| 250 | #define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v) (((v) << 24) & 0x1000000) | ||
| 251 | #define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 23 | ||
| 252 | #define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x800000 | ||
| 253 | #define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v) (((v) << 23) & 0x800000) | ||
| 254 | #define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL 22 | ||
| 255 | #define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x400000 | ||
| 256 | #define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v) (((v) << 22) & 0x400000) | ||
| 257 | #define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 21 | ||
| 258 | #define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x200000 | ||
| 259 | #define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v) (((v) << 21) & 0x200000) | ||
| 260 | #define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL 20 | ||
| 261 | #define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x100000 | ||
| 262 | #define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v) (((v) << 20) & 0x100000) | ||
| 263 | #define BP_APBH_CHn_DEBUG1_RSVD1 5 | ||
| 264 | #define BM_APBH_CHn_DEBUG1_RSVD1 0xfffe0 | ||
| 265 | #define BF_APBH_CHn_DEBUG1_RSVD1(v) (((v) << 5) & 0xfffe0) | ||
| 266 | #define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 | ||
| 267 | #define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x1f | ||
| 268 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x0 | ||
| 269 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x1 | ||
| 270 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x2 | ||
| 271 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x3 | ||
| 272 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x4 | ||
| 273 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x5 | ||
| 274 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x6 | ||
| 275 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x7 | ||
| 276 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x8 | ||
| 277 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x9 | ||
| 278 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0xc | ||
| 279 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0xd | ||
| 280 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0xe | ||
| 281 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0xf | ||
| 282 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 | ||
| 283 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1c | ||
| 284 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1e | ||
| 285 | #define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) (((v) << 0) & 0x1f) | ||
| 286 | #define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(v) ((BV_APBH_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f) | ||
| 287 | |||
| 288 | #endif /* __HEADERGEN__STMP3600__APBH__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-apbx.h b/firmware/target/arm/imx233/regs/stmp3600/regs-apbx.h new file mode 100644 index 0000000000..fcb9949616 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-apbx.h | |||
| @@ -0,0 +1,276 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.4.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__APBX__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__APBX__H__ | ||
| 25 | |||
| 26 | #define REGS_APBX_BASE (0x80024000) | ||
| 27 | |||
| 28 | #define REGS_APBX_VERSION "2.4.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_APBX_CTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_APBX_CTRL0 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_APBX_CTRL0_SET (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_APBX_CTRL0_CLR (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_APBX_CTRL0_TOG (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_APBX_CTRL0_SFTRST 31 | ||
| 40 | #define BM_APBX_CTRL0_SFTRST 0x80000000 | ||
| 41 | #define BF_APBX_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_APBX_CTRL0_CLKGATE 30 | ||
| 43 | #define BM_APBX_CTRL0_CLKGATE 0x40000000 | ||
| 44 | #define BF_APBX_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_APBX_CTRL0_RESET_CHANNEL 16 | ||
| 46 | #define BM_APBX_CTRL0_RESET_CHANNEL 0xff0000 | ||
| 47 | #define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOIN 0x1 | ||
| 48 | #define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOOUT 0x2 | ||
| 49 | #define BV_APBX_CTRL0_RESET_CHANNEL__SPDIF_TX 0x4 | ||
| 50 | #define BV_APBX_CTRL0_RESET_CHANNEL__I2C 0x8 | ||
| 51 | #define BV_APBX_CTRL0_RESET_CHANNEL__LCDIF 0x10 | ||
| 52 | #define BV_APBX_CTRL0_RESET_CHANNEL__DRI 0x20 | ||
| 53 | #define BV_APBX_CTRL0_RESET_CHANNEL__UART_RX 0x30 | ||
| 54 | #define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_RX 0x30 | ||
| 55 | #define BV_APBX_CTRL0_RESET_CHANNEL__UART_TX 0x40 | ||
| 56 | #define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_TX 0x40 | ||
| 57 | #define BF_APBX_CTRL0_RESET_CHANNEL(v) (((v) << 16) & 0xff0000) | ||
| 58 | #define BF_APBX_CTRL0_RESET_CHANNEL_V(v) ((BV_APBX_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000) | ||
| 59 | #define BP_APBX_CTRL0_FREEZE_CHANNEL 0 | ||
| 60 | #define BM_APBX_CTRL0_FREEZE_CHANNEL 0xff | ||
| 61 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOIN 0x1 | ||
| 62 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOOUT 0x2 | ||
| 63 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__SPDIF_TX 0x4 | ||
| 64 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__I2C 0x8 | ||
| 65 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__LCDIF 0x10 | ||
| 66 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__DRI 0x20 | ||
| 67 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_RX 0x30 | ||
| 68 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_RX 0x30 | ||
| 69 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_TX 0x40 | ||
| 70 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_TX 0x40 | ||
| 71 | #define BF_APBX_CTRL0_FREEZE_CHANNEL(v) (((v) << 0) & 0xff) | ||
| 72 | #define BF_APBX_CTRL0_FREEZE_CHANNEL_V(v) ((BV_APBX_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff) | ||
| 73 | |||
| 74 | /** | ||
| 75 | * Register: HW_APBX_CTRL1 | ||
| 76 | * Address: 0x10 | ||
| 77 | * SCT: yes | ||
| 78 | */ | ||
| 79 | #define HW_APBX_CTRL1 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x0)) | ||
| 80 | #define HW_APBX_CTRL1_SET (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x4)) | ||
| 81 | #define HW_APBX_CTRL1_CLR (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x8)) | ||
| 82 | #define HW_APBX_CTRL1_TOG (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0xc)) | ||
| 83 | #define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN 16 | ||
| 84 | #define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN 0xff0000 | ||
| 85 | #define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 16) & 0xff0000) | ||
| 86 | #define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ 0 | ||
| 87 | #define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ 0xff | ||
| 88 | #define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v) (((v) << 0) & 0xff) | ||
| 89 | |||
| 90 | /** | ||
| 91 | * Register: HW_APBX_DEVSEL | ||
| 92 | * Address: 0x20 | ||
| 93 | * SCT: no | ||
| 94 | */ | ||
| 95 | #define HW_APBX_DEVSEL (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20)) | ||
| 96 | #define BP_APBX_DEVSEL_CH7 28 | ||
| 97 | #define BM_APBX_DEVSEL_CH7 0xf0000000 | ||
| 98 | #define BV_APBX_DEVSEL_CH7__USE_UART 0x0 | ||
| 99 | #define BV_APBX_DEVSEL_CH7__USE_IRDA 0x1 | ||
| 100 | #define BF_APBX_DEVSEL_CH7(v) (((v) << 28) & 0xf0000000) | ||
| 101 | #define BF_APBX_DEVSEL_CH7_V(v) ((BV_APBX_DEVSEL_CH7__##v << 28) & 0xf0000000) | ||
| 102 | #define BP_APBX_DEVSEL_CH6 24 | ||
| 103 | #define BM_APBX_DEVSEL_CH6 0xf000000 | ||
| 104 | #define BV_APBX_DEVSEL_CH6__USE_UART 0x0 | ||
| 105 | #define BV_APBX_DEVSEL_CH6__USE_IRDA 0x1 | ||
| 106 | #define BF_APBX_DEVSEL_CH6(v) (((v) << 24) & 0xf000000) | ||
| 107 | #define BF_APBX_DEVSEL_CH6_V(v) ((BV_APBX_DEVSEL_CH6__##v << 24) & 0xf000000) | ||
| 108 | #define BP_APBX_DEVSEL_CH5 20 | ||
| 109 | #define BM_APBX_DEVSEL_CH5 0xf00000 | ||
| 110 | #define BF_APBX_DEVSEL_CH5(v) (((v) << 20) & 0xf00000) | ||
| 111 | #define BP_APBX_DEVSEL_CH4 16 | ||
| 112 | #define BM_APBX_DEVSEL_CH4 0xf0000 | ||
| 113 | #define BF_APBX_DEVSEL_CH4(v) (((v) << 16) & 0xf0000) | ||
| 114 | #define BP_APBX_DEVSEL_CH3 12 | ||
| 115 | #define BM_APBX_DEVSEL_CH3 0xf000 | ||
| 116 | #define BF_APBX_DEVSEL_CH3(v) (((v) << 12) & 0xf000) | ||
| 117 | #define BP_APBX_DEVSEL_CH2 8 | ||
| 118 | #define BM_APBX_DEVSEL_CH2 0xf00 | ||
| 119 | #define BF_APBX_DEVSEL_CH2(v) (((v) << 8) & 0xf00) | ||
| 120 | #define BP_APBX_DEVSEL_CH1 4 | ||
| 121 | #define BM_APBX_DEVSEL_CH1 0xf0 | ||
| 122 | #define BF_APBX_DEVSEL_CH1(v) (((v) << 4) & 0xf0) | ||
| 123 | #define BP_APBX_DEVSEL_CH0 0 | ||
| 124 | #define BM_APBX_DEVSEL_CH0 0xf | ||
| 125 | #define BF_APBX_DEVSEL_CH0(v) (((v) << 0) & 0xf) | ||
| 126 | |||
| 127 | /** | ||
| 128 | * Register: HW_APBX_CHn_NXTCMDAR | ||
| 129 | * Address: 0x40+n*0x70 | ||
| 130 | * SCT: no | ||
| 131 | */ | ||
| 132 | #define HW_APBX_CHn_NXTCMDAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x40+(n)*0x70)) | ||
| 133 | #define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0 | ||
| 134 | #define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xffffffff | ||
| 135 | #define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 136 | |||
| 137 | /** | ||
| 138 | * Register: HW_APBX_CHn_DEBUG2 | ||
| 139 | * Address: 0x90+n*0x70 | ||
| 140 | * SCT: no | ||
| 141 | */ | ||
| 142 | #define HW_APBX_CHn_DEBUG2(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x90+(n)*0x70)) | ||
| 143 | #define BP_APBX_CHn_DEBUG2_APB_BYTES 16 | ||
| 144 | #define BM_APBX_CHn_DEBUG2_APB_BYTES 0xffff0000 | ||
| 145 | #define BF_APBX_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000) | ||
| 146 | #define BP_APBX_CHn_DEBUG2_AHB_BYTES 0 | ||
| 147 | #define BM_APBX_CHn_DEBUG2_AHB_BYTES 0xffff | ||
| 148 | #define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff) | ||
| 149 | |||
| 150 | /** | ||
| 151 | * Register: HW_APBX_CHn_BAR | ||
| 152 | * Address: 0x60+n*0x70 | ||
| 153 | * SCT: no | ||
| 154 | */ | ||
| 155 | #define HW_APBX_CHn_BAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x60+(n)*0x70)) | ||
| 156 | #define BP_APBX_CHn_BAR_ADDRESS 0 | ||
| 157 | #define BM_APBX_CHn_BAR_ADDRESS 0xffffffff | ||
| 158 | #define BF_APBX_CHn_BAR_ADDRESS(v) (((v) << 0) & 0xffffffff) | ||
| 159 | |||
| 160 | /** | ||
| 161 | * Register: HW_APBX_CHn_CMD | ||
| 162 | * Address: 0x50+n*0x70 | ||
| 163 | * SCT: no | ||
| 164 | */ | ||
| 165 | #define HW_APBX_CHn_CMD(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x50+(n)*0x70)) | ||
| 166 | #define BP_APBX_CHn_CMD_XFER_COUNT 16 | ||
| 167 | #define BM_APBX_CHn_CMD_XFER_COUNT 0xffff0000 | ||
| 168 | #define BF_APBX_CHn_CMD_XFER_COUNT(v) (((v) << 16) & 0xffff0000) | ||
| 169 | #define BP_APBX_CHn_CMD_CMDWORDS 12 | ||
| 170 | #define BM_APBX_CHn_CMD_CMDWORDS 0xf000 | ||
| 171 | #define BF_APBX_CHn_CMD_CMDWORDS(v) (((v) << 12) & 0xf000) | ||
| 172 | #define BP_APBX_CHn_CMD_WAIT4ENDCMD 7 | ||
| 173 | #define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x80 | ||
| 174 | #define BF_APBX_CHn_CMD_WAIT4ENDCMD(v) (((v) << 7) & 0x80) | ||
| 175 | #define BP_APBX_CHn_CMD_SEMAPHORE 6 | ||
| 176 | #define BM_APBX_CHn_CMD_SEMAPHORE 0x40 | ||
| 177 | #define BF_APBX_CHn_CMD_SEMAPHORE(v) (((v) << 6) & 0x40) | ||
| 178 | #define BP_APBX_CHn_CMD_IRQONCMPLT 3 | ||
| 179 | #define BM_APBX_CHn_CMD_IRQONCMPLT 0x8 | ||
| 180 | #define BF_APBX_CHn_CMD_IRQONCMPLT(v) (((v) << 3) & 0x8) | ||
| 181 | #define BP_APBX_CHn_CMD_CHAIN 2 | ||
| 182 | #define BM_APBX_CHn_CMD_CHAIN 0x4 | ||
| 183 | #define BF_APBX_CHn_CMD_CHAIN(v) (((v) << 2) & 0x4) | ||
| 184 | #define BP_APBX_CHn_CMD_COMMAND 0 | ||
| 185 | #define BM_APBX_CHn_CMD_COMMAND 0x3 | ||
| 186 | #define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 | ||
| 187 | #define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1 | ||
| 188 | #define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2 | ||
| 189 | #define BF_APBX_CHn_CMD_COMMAND(v) (((v) << 0) & 0x3) | ||
| 190 | #define BF_APBX_CHn_CMD_COMMAND_V(v) ((BV_APBX_CHn_CMD_COMMAND__##v << 0) & 0x3) | ||
| 191 | |||
| 192 | /** | ||
| 193 | * Register: HW_APBX_CHn_DEBUG1 | ||
| 194 | * Address: 0x80+n*0x70 | ||
| 195 | * SCT: no | ||
| 196 | */ | ||
| 197 | #define HW_APBX_CHn_DEBUG1(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x80+(n)*0x70)) | ||
| 198 | #define BP_APBX_CHn_DEBUG1_REQ 31 | ||
| 199 | #define BM_APBX_CHn_DEBUG1_REQ 0x80000000 | ||
| 200 | #define BF_APBX_CHn_DEBUG1_REQ(v) (((v) << 31) & 0x80000000) | ||
| 201 | #define BP_APBX_CHn_DEBUG1_BURST 30 | ||
| 202 | #define BM_APBX_CHn_DEBUG1_BURST 0x40000000 | ||
| 203 | #define BF_APBX_CHn_DEBUG1_BURST(v) (((v) << 30) & 0x40000000) | ||
| 204 | #define BP_APBX_CHn_DEBUG1_KICK 29 | ||
| 205 | #define BM_APBX_CHn_DEBUG1_KICK 0x20000000 | ||
| 206 | #define BF_APBX_CHn_DEBUG1_KICK(v) (((v) << 29) & 0x20000000) | ||
| 207 | #define BP_APBX_CHn_DEBUG1_END 28 | ||
| 208 | #define BM_APBX_CHn_DEBUG1_END 0x10000000 | ||
| 209 | #define BF_APBX_CHn_DEBUG1_END(v) (((v) << 28) & 0x10000000) | ||
| 210 | #define BP_APBX_CHn_DEBUG1_RSVD2 25 | ||
| 211 | #define BM_APBX_CHn_DEBUG1_RSVD2 0xe000000 | ||
| 212 | #define BF_APBX_CHn_DEBUG1_RSVD2(v) (((v) << 25) & 0xe000000) | ||
| 213 | #define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 24 | ||
| 214 | #define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 0x1000000 | ||
| 215 | #define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v) (((v) << 24) & 0x1000000) | ||
| 216 | #define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 23 | ||
| 217 | #define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 0x800000 | ||
| 218 | #define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v) (((v) << 23) & 0x800000) | ||
| 219 | #define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL 22 | ||
| 220 | #define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL 0x400000 | ||
| 221 | #define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v) (((v) << 22) & 0x400000) | ||
| 222 | #define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 21 | ||
| 223 | #define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 0x200000 | ||
| 224 | #define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v) (((v) << 21) & 0x200000) | ||
| 225 | #define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL 20 | ||
| 226 | #define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL 0x100000 | ||
| 227 | #define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v) (((v) << 20) & 0x100000) | ||
| 228 | #define BP_APBX_CHn_DEBUG1_RSVD1 5 | ||
| 229 | #define BM_APBX_CHn_DEBUG1_RSVD1 0xfffe0 | ||
| 230 | #define BF_APBX_CHn_DEBUG1_RSVD1(v) (((v) << 5) & 0xfffe0) | ||
| 231 | #define BP_APBX_CHn_DEBUG1_STATEMACHINE 0 | ||
| 232 | #define BM_APBX_CHn_DEBUG1_STATEMACHINE 0x1f | ||
| 233 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE 0x0 | ||
| 234 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x1 | ||
| 235 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x2 | ||
| 236 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x3 | ||
| 237 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x4 | ||
| 238 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x5 | ||
| 239 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x6 | ||
| 240 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x7 | ||
| 241 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x8 | ||
| 242 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x9 | ||
| 243 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE 0xc | ||
| 244 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ 0xd | ||
| 245 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0xe | ||
| 246 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0xf | ||
| 247 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 | ||
| 248 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1c | ||
| 249 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1e | ||
| 250 | #define BF_APBX_CHn_DEBUG1_STATEMACHINE(v) (((v) << 0) & 0x1f) | ||
| 251 | #define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(v) ((BV_APBX_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f) | ||
| 252 | |||
| 253 | /** | ||
| 254 | * Register: HW_APBX_CHn_SEMA | ||
| 255 | * Address: 0x70+n*0x70 | ||
| 256 | * SCT: no | ||
| 257 | */ | ||
| 258 | #define HW_APBX_CHn_SEMA(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x70+(n)*0x70)) | ||
| 259 | #define BP_APBX_CHn_SEMA_PHORE 16 | ||
| 260 | #define BM_APBX_CHn_SEMA_PHORE 0xff0000 | ||
| 261 | #define BF_APBX_CHn_SEMA_PHORE(v) (((v) << 16) & 0xff0000) | ||
| 262 | #define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 | ||
| 263 | #define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0xff | ||
| 264 | #define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) (((v) << 0) & 0xff) | ||
| 265 | |||
| 266 | /** | ||
| 267 | * Register: HW_APBX_CHn_CURCMDAR | ||
| 268 | * Address: 0x30+n*0x70 | ||
| 269 | * SCT: no | ||
| 270 | */ | ||
| 271 | #define HW_APBX_CHn_CURCMDAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30+(n)*0x70)) | ||
| 272 | #define BP_APBX_CHn_CURCMDAR_CMD_ADDR 0 | ||
| 273 | #define BM_APBX_CHn_CURCMDAR_CMD_ADDR 0xffffffff | ||
| 274 | #define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 275 | |||
| 276 | #endif /* __HEADERGEN__STMP3600__APBX__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-arc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-arc.h new file mode 100644 index 0000000000..af64d3a4ef --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-arc.h | |||
| @@ -0,0 +1,268 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__ARC__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__ARC__H__ | ||
| 25 | |||
| 26 | #define REGS_ARC_BASE (0x80080000) | ||
| 27 | |||
| 28 | #define REGS_ARC_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_ARC_BASE | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: no | ||
| 34 | */ | ||
| 35 | #define HW_ARC_BASE (*(volatile unsigned long *)(REGS_ARC_BASE + 0x0)) | ||
| 36 | |||
| 37 | /** | ||
| 38 | * Register: HW_ARC_ID | ||
| 39 | * Address: 0 | ||
| 40 | * SCT: no | ||
| 41 | */ | ||
| 42 | #define HW_ARC_ID (*(volatile unsigned long *)(REGS_ARC_BASE + 0x0)) | ||
| 43 | |||
| 44 | /** | ||
| 45 | * Register: HW_ARC_HCSPARAMS | ||
| 46 | * Address: 0x104 | ||
| 47 | * SCT: no | ||
| 48 | */ | ||
| 49 | #define HW_ARC_HCSPARAMS (*(volatile unsigned long *)(REGS_ARC_BASE + 0x104)) | ||
| 50 | |||
| 51 | /** | ||
| 52 | * Register: HW_ARC_USBCMD | ||
| 53 | * Address: 0x140 | ||
| 54 | * SCT: no | ||
| 55 | */ | ||
| 56 | #define HW_ARC_USBCMD (*(volatile unsigned long *)(REGS_ARC_BASE + 0x140)) | ||
| 57 | |||
| 58 | /** | ||
| 59 | * Register: HW_ARC_USBSTS | ||
| 60 | * Address: 0x144 | ||
| 61 | * SCT: no | ||
| 62 | */ | ||
| 63 | #define HW_ARC_USBSTS (*(volatile unsigned long *)(REGS_ARC_BASE + 0x144)) | ||
| 64 | |||
| 65 | /** | ||
| 66 | * Register: HW_ARC_USBINTR | ||
| 67 | * Address: 0x148 | ||
| 68 | * SCT: no | ||
| 69 | */ | ||
| 70 | #define HW_ARC_USBINTR (*(volatile unsigned long *)(REGS_ARC_BASE + 0x148)) | ||
| 71 | |||
| 72 | /** | ||
| 73 | * Register: HW_ARC_FRINDEX | ||
| 74 | * Address: 0x14c | ||
| 75 | * SCT: no | ||
| 76 | */ | ||
| 77 | #define HW_ARC_FRINDEX (*(volatile unsigned long *)(REGS_ARC_BASE + 0x14c)) | ||
| 78 | |||
| 79 | /** | ||
| 80 | * Register: HW_ARC_DEVADDR | ||
| 81 | * Address: 0x154 | ||
| 82 | * SCT: no | ||
| 83 | */ | ||
| 84 | #define HW_ARC_DEVADDR (*(volatile unsigned long *)(REGS_ARC_BASE + 0x154)) | ||
| 85 | |||
| 86 | /** | ||
| 87 | * Register: HW_ARC_ENDPTLISTADDR | ||
| 88 | * Address: 0x158 | ||
| 89 | * SCT: no | ||
| 90 | */ | ||
| 91 | #define HW_ARC_ENDPTLISTADDR (*(volatile unsigned long *)(REGS_ARC_BASE + 0x158)) | ||
| 92 | |||
| 93 | /** | ||
| 94 | * Register: HW_ARC_PORTSC1 | ||
| 95 | * Address: 0x184 | ||
| 96 | * SCT: no | ||
| 97 | */ | ||
| 98 | #define HW_ARC_PORTSC1 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x184)) | ||
| 99 | |||
| 100 | /** | ||
| 101 | * Register: HW_ARC_OTGSC | ||
| 102 | * Address: 0x1a4 | ||
| 103 | * SCT: no | ||
| 104 | */ | ||
| 105 | #define HW_ARC_OTGSC (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1a4)) | ||
| 106 | |||
| 107 | /** | ||
| 108 | * Register: HW_ARC_USBMODE | ||
| 109 | * Address: 0x1a8 | ||
| 110 | * SCT: no | ||
| 111 | */ | ||
| 112 | #define HW_ARC_USBMODE (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1a8)) | ||
| 113 | |||
| 114 | /** | ||
| 115 | * Register: HW_ARC_ENDPTSETUPSTAT | ||
| 116 | * Address: 0x1ac | ||
| 117 | * SCT: no | ||
| 118 | */ | ||
| 119 | #define HW_ARC_ENDPTSETUPSTAT (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1ac)) | ||
| 120 | |||
| 121 | /** | ||
| 122 | * Register: HW_ARC_ENDPTPRIME | ||
| 123 | * Address: 0x1b0 | ||
| 124 | * SCT: no | ||
| 125 | */ | ||
| 126 | #define HW_ARC_ENDPTPRIME (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1b0)) | ||
| 127 | |||
| 128 | /** | ||
| 129 | * Register: HW_ARC_ENDPTFLUSH | ||
| 130 | * Address: 0x1b4 | ||
| 131 | * SCT: no | ||
| 132 | */ | ||
| 133 | #define HW_ARC_ENDPTFLUSH (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1b4)) | ||
| 134 | |||
| 135 | /** | ||
| 136 | * Register: HW_ARC_ENDPTSTATUS | ||
| 137 | * Address: 0x1b8 | ||
| 138 | * SCT: no | ||
| 139 | */ | ||
| 140 | #define HW_ARC_ENDPTSTATUS (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1b8)) | ||
| 141 | |||
| 142 | /** | ||
| 143 | * Register: HW_ARC_ENDPTCOMPLETE | ||
| 144 | * Address: 0x1bc | ||
| 145 | * SCT: no | ||
| 146 | */ | ||
| 147 | #define HW_ARC_ENDPTCOMPLETE (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1bc)) | ||
| 148 | |||
| 149 | /** | ||
| 150 | * Register: HW_ARC_ENDPTCTRL0 | ||
| 151 | * Address: 0x1c0 | ||
| 152 | * SCT: no | ||
| 153 | */ | ||
| 154 | #define HW_ARC_ENDPTCTRL0 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c0)) | ||
| 155 | |||
| 156 | /** | ||
| 157 | * Register: HW_ARC_ENDPTCTRL1 | ||
| 158 | * Address: 0x1c4 | ||
| 159 | * SCT: no | ||
| 160 | */ | ||
| 161 | #define HW_ARC_ENDPTCTRL1 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c4)) | ||
| 162 | |||
| 163 | /** | ||
| 164 | * Register: HW_ARC_ENDPTCTRL2 | ||
| 165 | * Address: 0x1c8 | ||
| 166 | * SCT: no | ||
| 167 | */ | ||
| 168 | #define HW_ARC_ENDPTCTRL2 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c8)) | ||
| 169 | |||
| 170 | /** | ||
| 171 | * Register: HW_ARC_ENDPTCTRL3 | ||
| 172 | * Address: 0x1cc | ||
| 173 | * SCT: no | ||
| 174 | */ | ||
| 175 | #define HW_ARC_ENDPTCTRL3 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1cc)) | ||
| 176 | |||
| 177 | /** | ||
| 178 | * Register: HW_ARC_ENDPTCTRL4 | ||
| 179 | * Address: 0x1d0 | ||
| 180 | * SCT: no | ||
| 181 | */ | ||
| 182 | #define HW_ARC_ENDPTCTRL4 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1d0)) | ||
| 183 | |||
| 184 | /** | ||
| 185 | * Register: HW_ARC_ENDPTCTRL5 | ||
| 186 | * Address: 0x1d4 | ||
| 187 | * SCT: no | ||
| 188 | */ | ||
| 189 | #define HW_ARC_ENDPTCTRL5 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1d4)) | ||
| 190 | |||
| 191 | /** | ||
| 192 | * Register: HW_ARC_ENDPTCTRL6 | ||
| 193 | * Address: 0x1d8 | ||
| 194 | * SCT: no | ||
| 195 | */ | ||
| 196 | #define HW_ARC_ENDPTCTRL6 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1d8)) | ||
| 197 | |||
| 198 | /** | ||
| 199 | * Register: HW_ARC_ENDPTCTRL7 | ||
| 200 | * Address: 0x1dc | ||
| 201 | * SCT: no | ||
| 202 | */ | ||
| 203 | #define HW_ARC_ENDPTCTRL7 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1dc)) | ||
| 204 | |||
| 205 | /** | ||
| 206 | * Register: HW_ARC_ENDPTCTRL8 | ||
| 207 | * Address: 0x1e0 | ||
| 208 | * SCT: no | ||
| 209 | */ | ||
| 210 | #define HW_ARC_ENDPTCTRL8 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1e0)) | ||
| 211 | |||
| 212 | /** | ||
| 213 | * Register: HW_ARC_ENDPTCTRL9 | ||
| 214 | * Address: 0x1e4 | ||
| 215 | * SCT: no | ||
| 216 | */ | ||
| 217 | #define HW_ARC_ENDPTCTRL9 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1e4)) | ||
| 218 | |||
| 219 | /** | ||
| 220 | * Register: HW_ARC_ENDPTCTRL10 | ||
| 221 | * Address: 0x1e8 | ||
| 222 | * SCT: no | ||
| 223 | */ | ||
| 224 | #define HW_ARC_ENDPTCTRL10 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1e8)) | ||
| 225 | |||
| 226 | /** | ||
| 227 | * Register: HW_ARC_ENDPTCTRL11 | ||
| 228 | * Address: 0x1ec | ||
| 229 | * SCT: no | ||
| 230 | */ | ||
| 231 | #define HW_ARC_ENDPTCTRL11 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1ec)) | ||
| 232 | |||
| 233 | /** | ||
| 234 | * Register: HW_ARC_ENDPTCTRL12 | ||
| 235 | * Address: 0x1f0 | ||
| 236 | * SCT: no | ||
| 237 | */ | ||
| 238 | #define HW_ARC_ENDPTCTRL12 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1f0)) | ||
| 239 | |||
| 240 | /** | ||
| 241 | * Register: HW_ARC_ENDPTCTRL13 | ||
| 242 | * Address: 0x1f4 | ||
| 243 | * SCT: no | ||
| 244 | */ | ||
| 245 | #define HW_ARC_ENDPTCTRL13 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1f4)) | ||
| 246 | |||
| 247 | /** | ||
| 248 | * Register: HW_ARC_ENDPTCTRL14 | ||
| 249 | * Address: 0x1f8 | ||
| 250 | * SCT: no | ||
| 251 | */ | ||
| 252 | #define HW_ARC_ENDPTCTRL14 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1f8)) | ||
| 253 | |||
| 254 | /** | ||
| 255 | * Register: HW_ARC_ENDPTCTRL15 | ||
| 256 | * Address: 0x1fc | ||
| 257 | * SCT: no | ||
| 258 | */ | ||
| 259 | #define HW_ARC_ENDPTCTRL15 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1fc)) | ||
| 260 | |||
| 261 | /** | ||
| 262 | * Register: HW_ARC_ENDPTCTRLn | ||
| 263 | * Address: 0x1c0+n*0x4 | ||
| 264 | * SCT: no | ||
| 265 | */ | ||
| 266 | #define HW_ARC_ENDPTCTRLn(n) (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c0+(n)*0x4)) | ||
| 267 | |||
| 268 | #endif /* __HEADERGEN__STMP3600__ARC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-audioin.h b/firmware/target/arm/imx233/regs/stmp3600/regs-audioin.h new file mode 100644 index 0000000000..8b5fbac6ea --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-audioin.h | |||
| @@ -0,0 +1,281 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.5.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__AUDIOIN__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__AUDIOIN__H__ | ||
| 25 | |||
| 26 | #define REGS_AUDIOIN_BASE (0x8004c000) | ||
| 27 | |||
| 28 | #define REGS_AUDIOIN_VERSION "2.5.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_AUDIOIN_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_AUDIOIN_CTRL (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_AUDIOIN_CTRL_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_AUDIOIN_CTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_AUDIOIN_CTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_AUDIOIN_CTRL_SFTRST 31 | ||
| 40 | #define BM_AUDIOIN_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_AUDIOIN_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_AUDIOIN_CTRL_CLKGATE 30 | ||
| 43 | #define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_AUDIOIN_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_AUDIOIN_CTRL_DMAWAIT_COUNT 16 | ||
| 46 | #define BM_AUDIOIN_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
| 47 | #define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
| 48 | #define BP_AUDIOIN_CTRL_LR_SWAP 10 | ||
| 49 | #define BM_AUDIOIN_CTRL_LR_SWAP 0x400 | ||
| 50 | #define BF_AUDIOIN_CTRL_LR_SWAP(v) (((v) << 10) & 0x400) | ||
| 51 | #define BP_AUDIOIN_CTRL_EDGE_SYNC 9 | ||
| 52 | #define BM_AUDIOIN_CTRL_EDGE_SYNC 0x200 | ||
| 53 | #define BF_AUDIOIN_CTRL_EDGE_SYNC(v) (((v) << 9) & 0x200) | ||
| 54 | #define BP_AUDIOIN_CTRL_INVERT_1BIT 8 | ||
| 55 | #define BM_AUDIOIN_CTRL_INVERT_1BIT 0x100 | ||
| 56 | #define BF_AUDIOIN_CTRL_INVERT_1BIT(v) (((v) << 8) & 0x100) | ||
| 57 | #define BP_AUDIOIN_CTRL_OFFSET_ENABLE 7 | ||
| 58 | #define BM_AUDIOIN_CTRL_OFFSET_ENABLE 0x80 | ||
| 59 | #define BF_AUDIOIN_CTRL_OFFSET_ENABLE(v) (((v) << 7) & 0x80) | ||
| 60 | #define BP_AUDIOIN_CTRL_HPF_ENABLE 6 | ||
| 61 | #define BM_AUDIOIN_CTRL_HPF_ENABLE 0x40 | ||
| 62 | #define BF_AUDIOIN_CTRL_HPF_ENABLE(v) (((v) << 6) & 0x40) | ||
| 63 | #define BP_AUDIOIN_CTRL_WORD_LENGTH 5 | ||
| 64 | #define BM_AUDIOIN_CTRL_WORD_LENGTH 0x20 | ||
| 65 | #define BF_AUDIOIN_CTRL_WORD_LENGTH(v) (((v) << 5) & 0x20) | ||
| 66 | #define BP_AUDIOIN_CTRL_LOOPBACK 4 | ||
| 67 | #define BM_AUDIOIN_CTRL_LOOPBACK 0x10 | ||
| 68 | #define BF_AUDIOIN_CTRL_LOOPBACK(v) (((v) << 4) & 0x10) | ||
| 69 | #define BP_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 3 | ||
| 70 | #define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x8 | ||
| 71 | #define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
| 72 | #define BP_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 2 | ||
| 73 | #define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x4 | ||
| 74 | #define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) | ||
| 75 | #define BP_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 1 | ||
| 76 | #define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x2 | ||
| 77 | #define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
| 78 | #define BP_AUDIOIN_CTRL_RUN 0 | ||
| 79 | #define BM_AUDIOIN_CTRL_RUN 0x1 | ||
| 80 | #define BF_AUDIOIN_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
| 81 | |||
| 82 | /** | ||
| 83 | * Register: HW_AUDIOIN_STAT | ||
| 84 | * Address: 0x10 | ||
| 85 | * SCT: no | ||
| 86 | */ | ||
| 87 | #define HW_AUDIOIN_STAT (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10)) | ||
| 88 | #define BP_AUDIOIN_STAT_ADC_PRESENT 31 | ||
| 89 | #define BM_AUDIOIN_STAT_ADC_PRESENT 0x80000000 | ||
| 90 | #define BF_AUDIOIN_STAT_ADC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 91 | |||
| 92 | /** | ||
| 93 | * Register: HW_AUDIOIN_ADCSRR | ||
| 94 | * Address: 0x20 | ||
| 95 | * SCT: yes | ||
| 96 | */ | ||
| 97 | #define HW_AUDIOIN_ADCSRR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x0)) | ||
| 98 | #define HW_AUDIOIN_ADCSRR_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x4)) | ||
| 99 | #define HW_AUDIOIN_ADCSRR_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x8)) | ||
| 100 | #define HW_AUDIOIN_ADCSRR_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0xc)) | ||
| 101 | #define BP_AUDIOIN_ADCSRR_OSR 31 | ||
| 102 | #define BM_AUDIOIN_ADCSRR_OSR 0x80000000 | ||
| 103 | #define BV_AUDIOIN_ADCSRR_OSR__OSR6 0x0 | ||
| 104 | #define BV_AUDIOIN_ADCSRR_OSR__OSR12 0x1 | ||
| 105 | #define BF_AUDIOIN_ADCSRR_OSR(v) (((v) << 31) & 0x80000000) | ||
| 106 | #define BF_AUDIOIN_ADCSRR_OSR_V(v) ((BV_AUDIOIN_ADCSRR_OSR__##v << 31) & 0x80000000) | ||
| 107 | #define BP_AUDIOIN_ADCSRR_BASEMULT 28 | ||
| 108 | #define BM_AUDIOIN_ADCSRR_BASEMULT 0x70000000 | ||
| 109 | #define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1 | ||
| 110 | #define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2 | ||
| 111 | #define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE 0x4 | ||
| 112 | #define BF_AUDIOIN_ADCSRR_BASEMULT(v) (((v) << 28) & 0x70000000) | ||
| 113 | #define BF_AUDIOIN_ADCSRR_BASEMULT_V(v) ((BV_AUDIOIN_ADCSRR_BASEMULT__##v << 28) & 0x70000000) | ||
| 114 | #define BP_AUDIOIN_ADCSRR_SRC_HOLD 24 | ||
| 115 | #define BM_AUDIOIN_ADCSRR_SRC_HOLD 0x7000000 | ||
| 116 | #define BF_AUDIOIN_ADCSRR_SRC_HOLD(v) (((v) << 24) & 0x7000000) | ||
| 117 | #define BP_AUDIOIN_ADCSRR_SRC_INT 16 | ||
| 118 | #define BM_AUDIOIN_ADCSRR_SRC_INT 0x1f0000 | ||
| 119 | #define BF_AUDIOIN_ADCSRR_SRC_INT(v) (((v) << 16) & 0x1f0000) | ||
| 120 | #define BP_AUDIOIN_ADCSRR_SRC_FRAC 0 | ||
| 121 | #define BM_AUDIOIN_ADCSRR_SRC_FRAC 0x1fff | ||
| 122 | #define BF_AUDIOIN_ADCSRR_SRC_FRAC(v) (((v) << 0) & 0x1fff) | ||
| 123 | |||
| 124 | /** | ||
| 125 | * Register: HW_AUDIOIN_ADCVOLUME | ||
| 126 | * Address: 0x30 | ||
| 127 | * SCT: yes | ||
| 128 | */ | ||
| 129 | #define HW_AUDIOIN_ADCVOLUME (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x0)) | ||
| 130 | #define HW_AUDIOIN_ADCVOLUME_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x4)) | ||
| 131 | #define HW_AUDIOIN_ADCVOLUME_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x8)) | ||
| 132 | #define HW_AUDIOIN_ADCVOLUME_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0xc)) | ||
| 133 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 28 | ||
| 134 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 0x10000000 | ||
| 135 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v) (((v) << 28) & 0x10000000) | ||
| 136 | #define BP_AUDIOIN_ADCVOLUME_EN_ZCD 25 | ||
| 137 | #define BM_AUDIOIN_ADCVOLUME_EN_ZCD 0x2000000 | ||
| 138 | #define BF_AUDIOIN_ADCVOLUME_EN_ZCD(v) (((v) << 25) & 0x2000000) | ||
| 139 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 | ||
| 140 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0xff0000 | ||
| 141 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v) (((v) << 16) & 0xff0000) | ||
| 142 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 12 | ||
| 143 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 0x1000 | ||
| 144 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000) | ||
| 145 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 | ||
| 146 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0xff | ||
| 147 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v) (((v) << 0) & 0xff) | ||
| 148 | |||
| 149 | /** | ||
| 150 | * Register: HW_AUDIOIN_ADCDEBUG | ||
| 151 | * Address: 0x40 | ||
| 152 | * SCT: yes | ||
| 153 | */ | ||
| 154 | #define HW_AUDIOIN_ADCDEBUG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x0)) | ||
| 155 | #define HW_AUDIOIN_ADCDEBUG_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x4)) | ||
| 156 | #define HW_AUDIOIN_ADCDEBUG_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x8)) | ||
| 157 | #define HW_AUDIOIN_ADCDEBUG_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0xc)) | ||
| 158 | #define BP_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 31 | ||
| 159 | #define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 0x80000000 | ||
| 160 | #define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v) (((v) << 31) & 0x80000000) | ||
| 161 | #define BP_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 3 | ||
| 162 | #define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 0x8 | ||
| 163 | #define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v) (((v) << 3) & 0x8) | ||
| 164 | #define BP_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 2 | ||
| 165 | #define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 0x4 | ||
| 166 | #define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v) (((v) << 2) & 0x4) | ||
| 167 | #define BP_AUDIOIN_ADCDEBUG_DMA_PREQ 1 | ||
| 168 | #define BM_AUDIOIN_ADCDEBUG_DMA_PREQ 0x2 | ||
| 169 | #define BF_AUDIOIN_ADCDEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) | ||
| 170 | #define BP_AUDIOIN_ADCDEBUG_FIFO_STATUS 0 | ||
| 171 | #define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS 0x1 | ||
| 172 | #define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) | ||
| 173 | |||
| 174 | /** | ||
| 175 | * Register: HW_AUDIOIN_ADCVOL | ||
| 176 | * Address: 0x50 | ||
| 177 | * SCT: yes | ||
| 178 | */ | ||
| 179 | #define HW_AUDIOIN_ADCVOL (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x0)) | ||
| 180 | #define HW_AUDIOIN_ADCVOL_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x4)) | ||
| 181 | #define HW_AUDIOIN_ADCVOL_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x8)) | ||
| 182 | #define HW_AUDIOIN_ADCVOL_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0xc)) | ||
| 183 | #define BP_AUDIOIN_ADCVOL_SELECT_LEFT 28 | ||
| 184 | #define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x30000000 | ||
| 185 | #define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v) (((v) << 28) & 0x30000000) | ||
| 186 | #define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 24 | ||
| 187 | #define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x3000000 | ||
| 188 | #define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v) (((v) << 24) & 0x3000000) | ||
| 189 | #define BP_AUDIOIN_ADCVOL_MUTE 8 | ||
| 190 | #define BM_AUDIOIN_ADCVOL_MUTE 0x100 | ||
| 191 | #define BF_AUDIOIN_ADCVOL_MUTE(v) (((v) << 8) & 0x100) | ||
| 192 | #define BP_AUDIOIN_ADCVOL_GAIN_LEFT 4 | ||
| 193 | #define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0xf0 | ||
| 194 | #define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v) (((v) << 4) & 0xf0) | ||
| 195 | #define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 | ||
| 196 | #define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0xf | ||
| 197 | #define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v) (((v) << 0) & 0xf) | ||
| 198 | |||
| 199 | /** | ||
| 200 | * Register: HW_AUDIOIN_MICLINE | ||
| 201 | * Address: 0x60 | ||
| 202 | * SCT: yes | ||
| 203 | */ | ||
| 204 | #define HW_AUDIOIN_MICLINE (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x0)) | ||
| 205 | #define HW_AUDIOIN_MICLINE_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x4)) | ||
| 206 | #define HW_AUDIOIN_MICLINE_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x8)) | ||
| 207 | #define HW_AUDIOIN_MICLINE_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0xc)) | ||
| 208 | #define BP_AUDIOIN_MICLINE_ATTEN_LINE 30 | ||
| 209 | #define BM_AUDIOIN_MICLINE_ATTEN_LINE 0x40000000 | ||
| 210 | #define BF_AUDIOIN_MICLINE_ATTEN_LINE(v) (((v) << 30) & 0x40000000) | ||
| 211 | #define BP_AUDIOIN_MICLINE_DIVIDE_LINE1 29 | ||
| 212 | #define BM_AUDIOIN_MICLINE_DIVIDE_LINE1 0x20000000 | ||
| 213 | #define BF_AUDIOIN_MICLINE_DIVIDE_LINE1(v) (((v) << 29) & 0x20000000) | ||
| 214 | #define BP_AUDIOIN_MICLINE_DIVIDE_LINE2 28 | ||
| 215 | #define BM_AUDIOIN_MICLINE_DIVIDE_LINE2 0x10000000 | ||
| 216 | #define BF_AUDIOIN_MICLINE_DIVIDE_LINE2(v) (((v) << 28) & 0x10000000) | ||
| 217 | #define BP_AUDIOIN_MICLINE_MIC_SELECT 24 | ||
| 218 | #define BM_AUDIOIN_MICLINE_MIC_SELECT 0x1000000 | ||
| 219 | #define BF_AUDIOIN_MICLINE_MIC_SELECT(v) (((v) << 24) & 0x1000000) | ||
| 220 | #define BP_AUDIOIN_MICLINE_MIC_RESISTOR 20 | ||
| 221 | #define BM_AUDIOIN_MICLINE_MIC_RESISTOR 0x300000 | ||
| 222 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__Off 0x0 | ||
| 223 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__2KOhm 0x1 | ||
| 224 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__4KOhm 0x2 | ||
| 225 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__8KOhm 0x3 | ||
| 226 | #define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v) (((v) << 20) & 0x300000) | ||
| 227 | #define BF_AUDIOIN_MICLINE_MIC_RESISTOR_V(v) ((BV_AUDIOIN_MICLINE_MIC_RESISTOR__##v << 20) & 0x300000) | ||
| 228 | #define BP_AUDIOIN_MICLINE_MIC_BIAS 16 | ||
| 229 | #define BM_AUDIOIN_MICLINE_MIC_BIAS 0x70000 | ||
| 230 | #define BF_AUDIOIN_MICLINE_MIC_BIAS(v) (((v) << 16) & 0x70000) | ||
| 231 | #define BP_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP 8 | ||
| 232 | #define BM_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP 0x100 | ||
| 233 | #define BF_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP(v) (((v) << 8) & 0x100) | ||
| 234 | #define BP_AUDIOIN_MICLINE_MIC_GAIN 0 | ||
| 235 | #define BM_AUDIOIN_MICLINE_MIC_GAIN 0x3 | ||
| 236 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__0dB 0x0 | ||
| 237 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__20dB 0x1 | ||
| 238 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__30dB 0x2 | ||
| 239 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__40dB 0x3 | ||
| 240 | #define BF_AUDIOIN_MICLINE_MIC_GAIN(v) (((v) << 0) & 0x3) | ||
| 241 | #define BF_AUDIOIN_MICLINE_MIC_GAIN_V(v) ((BV_AUDIOIN_MICLINE_MIC_GAIN__##v << 0) & 0x3) | ||
| 242 | |||
| 243 | /** | ||
| 244 | * Register: HW_AUDIOIN_ANACLKCTRL | ||
| 245 | * Address: 0x70 | ||
| 246 | * SCT: yes | ||
| 247 | */ | ||
| 248 | #define HW_AUDIOIN_ANACLKCTRL (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x0)) | ||
| 249 | #define HW_AUDIOIN_ANACLKCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x4)) | ||
| 250 | #define HW_AUDIOIN_ANACLKCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x8)) | ||
| 251 | #define HW_AUDIOIN_ANACLKCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0xc)) | ||
| 252 | #define BP_AUDIOIN_ANACLKCTRL_CLKGATE 31 | ||
| 253 | #define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 | ||
| 254 | #define BF_AUDIOIN_ANACLKCTRL_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 255 | #define BP_AUDIOIN_ANACLKCTRL_DITHER_ENABLE 6 | ||
| 256 | #define BM_AUDIOIN_ANACLKCTRL_DITHER_ENABLE 0x40 | ||
| 257 | #define BF_AUDIOIN_ANACLKCTRL_DITHER_ENABLE(v) (((v) << 6) & 0x40) | ||
| 258 | #define BP_AUDIOIN_ANACLKCTRL_SLOW_DITHER 5 | ||
| 259 | #define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER 0x20 | ||
| 260 | #define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v) (((v) << 5) & 0x20) | ||
| 261 | #define BP_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 4 | ||
| 262 | #define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 0x10 | ||
| 263 | #define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v) (((v) << 4) & 0x10) | ||
| 264 | #define BP_AUDIOIN_ANACLKCTRL_ADCDIV 0 | ||
| 265 | #define BM_AUDIOIN_ANACLKCTRL_ADCDIV 0x7 | ||
| 266 | #define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v) (((v) << 0) & 0x7) | ||
| 267 | |||
| 268 | /** | ||
| 269 | * Register: HW_AUDIOIN_DATA | ||
| 270 | * Address: 0x80 | ||
| 271 | * SCT: no | ||
| 272 | */ | ||
| 273 | #define HW_AUDIOIN_DATA (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80)) | ||
| 274 | #define BP_AUDIOIN_DATA_HIGH 16 | ||
| 275 | #define BM_AUDIOIN_DATA_HIGH 0xffff0000 | ||
| 276 | #define BF_AUDIOIN_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
| 277 | #define BP_AUDIOIN_DATA_LOW 0 | ||
| 278 | #define BM_AUDIOIN_DATA_LOW 0xffff | ||
| 279 | #define BF_AUDIOIN_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
| 280 | |||
| 281 | #endif /* __HEADERGEN__STMP3600__AUDIOIN__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-audioout.h b/firmware/target/arm/imx233/regs/stmp3600/regs-audioout.h new file mode 100644 index 0000000000..20e639c6dd --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-audioout.h | |||
| @@ -0,0 +1,473 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__AUDIOOUT__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__AUDIOOUT__H__ | ||
| 25 | |||
| 26 | #define REGS_AUDIOOUT_BASE (0x80048000) | ||
| 27 | |||
| 28 | #define REGS_AUDIOOUT_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_AUDIOOUT_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_AUDIOOUT_CTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_AUDIOOUT_CTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_AUDIOOUT_CTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_AUDIOOUT_CTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_AUDIOOUT_CTRL_SFTRST 31 | ||
| 40 | #define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_AUDIOOUT_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_AUDIOOUT_CTRL_CLKGATE 30 | ||
| 43 | #define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_AUDIOOUT_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT 16 | ||
| 46 | #define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
| 47 | #define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
| 48 | #define BP_AUDIOOUT_CTRL_LR_SWAP 14 | ||
| 49 | #define BM_AUDIOOUT_CTRL_LR_SWAP 0x4000 | ||
| 50 | #define BF_AUDIOOUT_CTRL_LR_SWAP(v) (((v) << 14) & 0x4000) | ||
| 51 | #define BP_AUDIOOUT_CTRL_EDGE_SYNC 13 | ||
| 52 | #define BM_AUDIOOUT_CTRL_EDGE_SYNC 0x2000 | ||
| 53 | #define BF_AUDIOOUT_CTRL_EDGE_SYNC(v) (((v) << 13) & 0x2000) | ||
| 54 | #define BP_AUDIOOUT_CTRL_INVERT_1BIT 12 | ||
| 55 | #define BM_AUDIOOUT_CTRL_INVERT_1BIT 0x1000 | ||
| 56 | #define BF_AUDIOOUT_CTRL_INVERT_1BIT(v) (((v) << 12) & 0x1000) | ||
| 57 | #define BP_AUDIOOUT_CTRL_SS3D_EFFECT 8 | ||
| 58 | #define BM_AUDIOOUT_CTRL_SS3D_EFFECT 0x300 | ||
| 59 | #define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v) (((v) << 8) & 0x300) | ||
| 60 | #define BP_AUDIOOUT_CTRL_WORD_LENGTH 6 | ||
| 61 | #define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x40 | ||
| 62 | #define BF_AUDIOOUT_CTRL_WORD_LENGTH(v) (((v) << 6) & 0x40) | ||
| 63 | #define BP_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 5 | ||
| 64 | #define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 0x20 | ||
| 65 | #define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v) (((v) << 5) & 0x20) | ||
| 66 | #define BP_AUDIOOUT_CTRL_LOOPBACK 4 | ||
| 67 | #define BM_AUDIOOUT_CTRL_LOOPBACK 0x10 | ||
| 68 | #define BF_AUDIOOUT_CTRL_LOOPBACK(v) (((v) << 4) & 0x10) | ||
| 69 | #define BP_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 3 | ||
| 70 | #define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x8 | ||
| 71 | #define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
| 72 | #define BP_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 2 | ||
| 73 | #define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x4 | ||
| 74 | #define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) | ||
| 75 | #define BP_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 1 | ||
| 76 | #define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x2 | ||
| 77 | #define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
| 78 | #define BP_AUDIOOUT_CTRL_RUN 0 | ||
| 79 | #define BM_AUDIOOUT_CTRL_RUN 0x1 | ||
| 80 | #define BF_AUDIOOUT_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
| 81 | |||
| 82 | /** | ||
| 83 | * Register: HW_AUDIOOUT_STAT | ||
| 84 | * Address: 0x10 | ||
| 85 | * SCT: no | ||
| 86 | */ | ||
| 87 | #define HW_AUDIOOUT_STAT (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10)) | ||
| 88 | #define BP_AUDIOOUT_STAT_DAC_PRESENT 31 | ||
| 89 | #define BM_AUDIOOUT_STAT_DAC_PRESENT 0x80000000 | ||
| 90 | #define BF_AUDIOOUT_STAT_DAC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 91 | |||
| 92 | /** | ||
| 93 | * Register: HW_AUDIOOUT_DACSRR | ||
| 94 | * Address: 0x20 | ||
| 95 | * SCT: yes | ||
| 96 | */ | ||
| 97 | #define HW_AUDIOOUT_DACSRR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x0)) | ||
| 98 | #define HW_AUDIOOUT_DACSRR_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x4)) | ||
| 99 | #define HW_AUDIOOUT_DACSRR_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x8)) | ||
| 100 | #define HW_AUDIOOUT_DACSRR_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0xc)) | ||
| 101 | #define BP_AUDIOOUT_DACSRR_OSR 31 | ||
| 102 | #define BM_AUDIOOUT_DACSRR_OSR 0x80000000 | ||
| 103 | #define BV_AUDIOOUT_DACSRR_OSR__OSR6 0x0 | ||
| 104 | #define BV_AUDIOOUT_DACSRR_OSR__OSR12 0x1 | ||
| 105 | #define BF_AUDIOOUT_DACSRR_OSR(v) (((v) << 31) & 0x80000000) | ||
| 106 | #define BF_AUDIOOUT_DACSRR_OSR_V(v) ((BV_AUDIOOUT_DACSRR_OSR__##v << 31) & 0x80000000) | ||
| 107 | #define BP_AUDIOOUT_DACSRR_BASEMULT 28 | ||
| 108 | #define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 | ||
| 109 | #define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE 0x1 | ||
| 110 | #define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE 0x2 | ||
| 111 | #define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE 0x4 | ||
| 112 | #define BF_AUDIOOUT_DACSRR_BASEMULT(v) (((v) << 28) & 0x70000000) | ||
| 113 | #define BF_AUDIOOUT_DACSRR_BASEMULT_V(v) ((BV_AUDIOOUT_DACSRR_BASEMULT__##v << 28) & 0x70000000) | ||
| 114 | #define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 | ||
| 115 | #define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x7000000 | ||
| 116 | #define BF_AUDIOOUT_DACSRR_SRC_HOLD(v) (((v) << 24) & 0x7000000) | ||
| 117 | #define BP_AUDIOOUT_DACSRR_SRC_INT 16 | ||
| 118 | #define BM_AUDIOOUT_DACSRR_SRC_INT 0x1f0000 | ||
| 119 | #define BF_AUDIOOUT_DACSRR_SRC_INT(v) (((v) << 16) & 0x1f0000) | ||
| 120 | #define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 | ||
| 121 | #define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x1fff | ||
| 122 | #define BF_AUDIOOUT_DACSRR_SRC_FRAC(v) (((v) << 0) & 0x1fff) | ||
| 123 | |||
| 124 | /** | ||
| 125 | * Register: HW_AUDIOOUT_DACVOLUME | ||
| 126 | * Address: 0x30 | ||
| 127 | * SCT: yes | ||
| 128 | */ | ||
| 129 | #define HW_AUDIOOUT_DACVOLUME (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x0)) | ||
| 130 | #define HW_AUDIOOUT_DACVOLUME_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x4)) | ||
| 131 | #define HW_AUDIOOUT_DACVOLUME_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x8)) | ||
| 132 | #define HW_AUDIOOUT_DACVOLUME_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0xc)) | ||
| 133 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 28 | ||
| 134 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 0x10000000 | ||
| 135 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v) (((v) << 28) & 0x10000000) | ||
| 136 | #define BP_AUDIOOUT_DACVOLUME_EN_ZCD 25 | ||
| 137 | #define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x2000000 | ||
| 138 | #define BF_AUDIOOUT_DACVOLUME_EN_ZCD(v) (((v) << 25) & 0x2000000) | ||
| 139 | #define BP_AUDIOOUT_DACVOLUME_MUTE_LEFT 24 | ||
| 140 | #define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x1000000 | ||
| 141 | #define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(v) (((v) << 24) & 0x1000000) | ||
| 142 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT 16 | ||
| 143 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT 0xff0000 | ||
| 144 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v) (((v) << 16) & 0xff0000) | ||
| 145 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 12 | ||
| 146 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 0x1000 | ||
| 147 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000) | ||
| 148 | #define BP_AUDIOOUT_DACVOLUME_MUTE_RIGHT 8 | ||
| 149 | #define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x100 | ||
| 150 | #define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v) (((v) << 8) & 0x100) | ||
| 151 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0 | ||
| 152 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0xff | ||
| 153 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v) (((v) << 0) & 0xff) | ||
| 154 | |||
| 155 | /** | ||
| 156 | * Register: HW_AUDIOOUT_DACDEBUG | ||
| 157 | * Address: 0x40 | ||
| 158 | * SCT: yes | ||
| 159 | */ | ||
| 160 | #define HW_AUDIOOUT_DACDEBUG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x0)) | ||
| 161 | #define HW_AUDIOOUT_DACDEBUG_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x4)) | ||
| 162 | #define HW_AUDIOOUT_DACDEBUG_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x8)) | ||
| 163 | #define HW_AUDIOOUT_DACDEBUG_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0xc)) | ||
| 164 | #define BP_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 31 | ||
| 165 | #define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 0x80000000 | ||
| 166 | #define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v) (((v) << 31) & 0x80000000) | ||
| 167 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 5 | ||
| 168 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 0x20 | ||
| 169 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v) (((v) << 5) & 0x20) | ||
| 170 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 4 | ||
| 171 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 0x10 | ||
| 172 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v) (((v) << 4) & 0x10) | ||
| 173 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 3 | ||
| 174 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 0x8 | ||
| 175 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v) (((v) << 3) & 0x8) | ||
| 176 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 2 | ||
| 177 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 0x4 | ||
| 178 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v) (((v) << 2) & 0x4) | ||
| 179 | #define BP_AUDIOOUT_DACDEBUG_DMA_PREQ 1 | ||
| 180 | #define BM_AUDIOOUT_DACDEBUG_DMA_PREQ 0x2 | ||
| 181 | #define BF_AUDIOOUT_DACDEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) | ||
| 182 | #define BP_AUDIOOUT_DACDEBUG_FIFO_STATUS 0 | ||
| 183 | #define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS 0x1 | ||
| 184 | #define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) | ||
| 185 | |||
| 186 | /** | ||
| 187 | * Register: HW_AUDIOOUT_HPVOL | ||
| 188 | * Address: 0x50 | ||
| 189 | * SCT: yes | ||
| 190 | */ | ||
| 191 | #define HW_AUDIOOUT_HPVOL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x0)) | ||
| 192 | #define HW_AUDIOOUT_HPVOL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x4)) | ||
| 193 | #define HW_AUDIOOUT_HPVOL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x8)) | ||
| 194 | #define HW_AUDIOOUT_HPVOL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0xc)) | ||
| 195 | #define BP_AUDIOOUT_HPVOL_SELECT 24 | ||
| 196 | #define BM_AUDIOOUT_HPVOL_SELECT 0x3000000 | ||
| 197 | #define BF_AUDIOOUT_HPVOL_SELECT(v) (((v) << 24) & 0x3000000) | ||
| 198 | #define BP_AUDIOOUT_HPVOL_MUTE 16 | ||
| 199 | #define BM_AUDIOOUT_HPVOL_MUTE 0x10000 | ||
| 200 | #define BF_AUDIOOUT_HPVOL_MUTE(v) (((v) << 16) & 0x10000) | ||
| 201 | #define BP_AUDIOOUT_HPVOL_VOL_LEFT 8 | ||
| 202 | #define BM_AUDIOOUT_HPVOL_VOL_LEFT 0x1f00 | ||
| 203 | #define BF_AUDIOOUT_HPVOL_VOL_LEFT(v) (((v) << 8) & 0x1f00) | ||
| 204 | #define BP_AUDIOOUT_HPVOL_VOL_RIGHT 0 | ||
| 205 | #define BM_AUDIOOUT_HPVOL_VOL_RIGHT 0x1f | ||
| 206 | #define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v) (((v) << 0) & 0x1f) | ||
| 207 | |||
| 208 | /** | ||
| 209 | * Register: HW_AUDIOOUT_SPKRVOL | ||
| 210 | * Address: 0x60 | ||
| 211 | * SCT: yes | ||
| 212 | */ | ||
| 213 | #define HW_AUDIOOUT_SPKRVOL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x0)) | ||
| 214 | #define HW_AUDIOOUT_SPKRVOL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x4)) | ||
| 215 | #define HW_AUDIOOUT_SPKRVOL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x8)) | ||
| 216 | #define HW_AUDIOOUT_SPKRVOL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0xc)) | ||
| 217 | #define BP_AUDIOOUT_SPKRVOL_MUTE 16 | ||
| 218 | #define BM_AUDIOOUT_SPKRVOL_MUTE 0x10000 | ||
| 219 | #define BF_AUDIOOUT_SPKRVOL_MUTE(v) (((v) << 16) & 0x10000) | ||
| 220 | #define BP_AUDIOOUT_SPKRVOL_VOL 0 | ||
| 221 | #define BM_AUDIOOUT_SPKRVOL_VOL 0xf | ||
| 222 | #define BF_AUDIOOUT_SPKRVOL_VOL(v) (((v) << 0) & 0xf) | ||
| 223 | |||
| 224 | /** | ||
| 225 | * Register: HW_AUDIOOUT_PWRDN | ||
| 226 | * Address: 0x70 | ||
| 227 | * SCT: yes | ||
| 228 | */ | ||
| 229 | #define HW_AUDIOOUT_PWRDN (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x0)) | ||
| 230 | #define HW_AUDIOOUT_PWRDN_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x4)) | ||
| 231 | #define HW_AUDIOOUT_PWRDN_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x8)) | ||
| 232 | #define HW_AUDIOOUT_PWRDN_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0xc)) | ||
| 233 | #define BP_AUDIOOUT_PWRDN_SPEAKER 24 | ||
| 234 | #define BM_AUDIOOUT_PWRDN_SPEAKER 0x1000000 | ||
| 235 | #define BF_AUDIOOUT_PWRDN_SPEAKER(v) (((v) << 24) & 0x1000000) | ||
| 236 | #define BP_AUDIOOUT_PWRDN_SELFBIAS 20 | ||
| 237 | #define BM_AUDIOOUT_PWRDN_SELFBIAS 0x100000 | ||
| 238 | #define BF_AUDIOOUT_PWRDN_SELFBIAS(v) (((v) << 20) & 0x100000) | ||
| 239 | #define BP_AUDIOOUT_PWRDN_RIGHT_ADC 16 | ||
| 240 | #define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x10000 | ||
| 241 | #define BF_AUDIOOUT_PWRDN_RIGHT_ADC(v) (((v) << 16) & 0x10000) | ||
| 242 | #define BP_AUDIOOUT_PWRDN_DAC 12 | ||
| 243 | #define BM_AUDIOOUT_PWRDN_DAC 0x1000 | ||
| 244 | #define BF_AUDIOOUT_PWRDN_DAC(v) (((v) << 12) & 0x1000) | ||
| 245 | #define BP_AUDIOOUT_PWRDN_ADC 8 | ||
| 246 | #define BM_AUDIOOUT_PWRDN_ADC 0x100 | ||
| 247 | #define BF_AUDIOOUT_PWRDN_ADC(v) (((v) << 8) & 0x100) | ||
| 248 | #define BP_AUDIOOUT_PWRDN_CAPLESS 4 | ||
| 249 | #define BM_AUDIOOUT_PWRDN_CAPLESS 0x10 | ||
| 250 | #define BF_AUDIOOUT_PWRDN_CAPLESS(v) (((v) << 4) & 0x10) | ||
| 251 | #define BP_AUDIOOUT_PWRDN_HEADPHONE 0 | ||
| 252 | #define BM_AUDIOOUT_PWRDN_HEADPHONE 0x1 | ||
| 253 | #define BF_AUDIOOUT_PWRDN_HEADPHONE(v) (((v) << 0) & 0x1) | ||
| 254 | |||
| 255 | /** | ||
| 256 | * Register: HW_AUDIOOUT_REFCTRL | ||
| 257 | * Address: 0x80 | ||
| 258 | * SCT: yes | ||
| 259 | */ | ||
| 260 | #define HW_AUDIOOUT_REFCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x0)) | ||
| 261 | #define HW_AUDIOOUT_REFCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x4)) | ||
| 262 | #define HW_AUDIOOUT_REFCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x8)) | ||
| 263 | #define HW_AUDIOOUT_REFCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0xc)) | ||
| 264 | #define BP_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 24 | ||
| 265 | #define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x1000000 | ||
| 266 | #define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v) (((v) << 24) & 0x1000000) | ||
| 267 | #define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 | ||
| 268 | #define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x700000 | ||
| 269 | #define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v) (((v) << 20) & 0x700000) | ||
| 270 | #define BP_AUDIOOUT_REFCTRL_LOW_PWR 19 | ||
| 271 | #define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x80000 | ||
| 272 | #define BF_AUDIOOUT_REFCTRL_LOW_PWR(v) (((v) << 19) & 0x80000) | ||
| 273 | #define BP_AUDIOOUT_REFCTRL_LW_REF 18 | ||
| 274 | #define BM_AUDIOOUT_REFCTRL_LW_REF 0x40000 | ||
| 275 | #define BF_AUDIOOUT_REFCTRL_LW_REF(v) (((v) << 18) & 0x40000) | ||
| 276 | #define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 | ||
| 277 | #define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x30000 | ||
| 278 | #define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v) (((v) << 16) & 0x30000) | ||
| 279 | #define BP_AUDIOOUT_REFCTRL_ADJ_ADC 13 | ||
| 280 | #define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x2000 | ||
| 281 | #define BF_AUDIOOUT_REFCTRL_ADJ_ADC(v) (((v) << 13) & 0x2000) | ||
| 282 | #define BP_AUDIOOUT_REFCTRL_ADJ_VAG 12 | ||
| 283 | #define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x1000 | ||
| 284 | #define BF_AUDIOOUT_REFCTRL_ADJ_VAG(v) (((v) << 12) & 0x1000) | ||
| 285 | #define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 | ||
| 286 | #define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0xf00 | ||
| 287 | #define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v) (((v) << 8) & 0xf00) | ||
| 288 | #define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 | ||
| 289 | #define BM_AUDIOOUT_REFCTRL_VAG_VAL 0xf0 | ||
| 290 | #define BF_AUDIOOUT_REFCTRL_VAG_VAL(v) (((v) << 4) & 0xf0) | ||
| 291 | #define BP_AUDIOOUT_REFCTRL_DAC_ADJ 0 | ||
| 292 | #define BM_AUDIOOUT_REFCTRL_DAC_ADJ 0x7 | ||
| 293 | #define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v) (((v) << 0) & 0x7) | ||
| 294 | |||
| 295 | /** | ||
| 296 | * Register: HW_AUDIOOUT_ANACTRL | ||
| 297 | * Address: 0x90 | ||
| 298 | * SCT: yes | ||
| 299 | */ | ||
| 300 | #define HW_AUDIOOUT_ANACTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x0)) | ||
| 301 | #define HW_AUDIOOUT_ANACTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x4)) | ||
| 302 | #define HW_AUDIOOUT_ANACTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x8)) | ||
| 303 | #define HW_AUDIOOUT_ANACTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0xc)) | ||
| 304 | #define BP_AUDIOOUT_ANACTRL_SHORT_CM_STS 28 | ||
| 305 | #define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS 0x10000000 | ||
| 306 | #define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(v) (((v) << 28) & 0x10000000) | ||
| 307 | #define BP_AUDIOOUT_ANACTRL_SHORT_LR_STS 24 | ||
| 308 | #define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS 0x1000000 | ||
| 309 | #define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(v) (((v) << 24) & 0x1000000) | ||
| 310 | #define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM 20 | ||
| 311 | #define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM 0x300000 | ||
| 312 | #define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v) (((v) << 20) & 0x300000) | ||
| 313 | #define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR 17 | ||
| 314 | #define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR 0x60000 | ||
| 315 | #define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v) (((v) << 17) & 0x60000) | ||
| 316 | #define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL 12 | ||
| 317 | #define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL 0x7000 | ||
| 318 | #define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v) (((v) << 12) & 0x7000) | ||
| 319 | #define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR 8 | ||
| 320 | #define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR 0x700 | ||
| 321 | #define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v) (((v) << 8) & 0x700) | ||
| 322 | #define BP_AUDIOOUT_ANACTRL_HP_HOLD_GND 5 | ||
| 323 | #define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x20 | ||
| 324 | #define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(v) (((v) << 5) & 0x20) | ||
| 325 | #define BP_AUDIOOUT_ANACTRL_HP_CLASSAB 4 | ||
| 326 | #define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x10 | ||
| 327 | #define BF_AUDIOOUT_ANACTRL_HP_CLASSAB(v) (((v) << 4) & 0x10) | ||
| 328 | #define BP_AUDIOOUT_ANACTRL_EN_SPKR_ZCD 2 | ||
| 329 | #define BM_AUDIOOUT_ANACTRL_EN_SPKR_ZCD 0x4 | ||
| 330 | #define BF_AUDIOOUT_ANACTRL_EN_SPKR_ZCD(v) (((v) << 2) & 0x4) | ||
| 331 | #define BP_AUDIOOUT_ANACTRL_ZCD_SELECTADC 1 | ||
| 332 | #define BM_AUDIOOUT_ANACTRL_ZCD_SELECTADC 0x2 | ||
| 333 | #define BF_AUDIOOUT_ANACTRL_ZCD_SELECTADC(v) (((v) << 1) & 0x2) | ||
| 334 | #define BP_AUDIOOUT_ANACTRL_EN_ZCD 0 | ||
| 335 | #define BM_AUDIOOUT_ANACTRL_EN_ZCD 0x1 | ||
| 336 | #define BF_AUDIOOUT_ANACTRL_EN_ZCD(v) (((v) << 0) & 0x1) | ||
| 337 | |||
| 338 | /** | ||
| 339 | * Register: HW_AUDIOOUT_TEST | ||
| 340 | * Address: 0xa0 | ||
| 341 | * SCT: yes | ||
| 342 | */ | ||
| 343 | #define HW_AUDIOOUT_TEST (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x0)) | ||
| 344 | #define HW_AUDIOOUT_TEST_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x4)) | ||
| 345 | #define HW_AUDIOOUT_TEST_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x8)) | ||
| 346 | #define HW_AUDIOOUT_TEST_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0xc)) | ||
| 347 | #define BP_AUDIOOUT_TEST_HP_ANTIPOP 28 | ||
| 348 | #define BM_AUDIOOUT_TEST_HP_ANTIPOP 0x70000000 | ||
| 349 | #define BF_AUDIOOUT_TEST_HP_ANTIPOP(v) (((v) << 28) & 0x70000000) | ||
| 350 | #define BP_AUDIOOUT_TEST_TM_ADCIN_TOHP 26 | ||
| 351 | #define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP 0x4000000 | ||
| 352 | #define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(v) (((v) << 26) & 0x4000000) | ||
| 353 | #define BP_AUDIOOUT_TEST_TM_SPEAKER 25 | ||
| 354 | #define BM_AUDIOOUT_TEST_TM_SPEAKER 0x2000000 | ||
| 355 | #define BF_AUDIOOUT_TEST_TM_SPEAKER(v) (((v) << 25) & 0x2000000) | ||
| 356 | #define BP_AUDIOOUT_TEST_TM_HPCOMMON 24 | ||
| 357 | #define BM_AUDIOOUT_TEST_TM_HPCOMMON 0x1000000 | ||
| 358 | #define BF_AUDIOOUT_TEST_TM_HPCOMMON(v) (((v) << 24) & 0x1000000) | ||
| 359 | #define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 | ||
| 360 | #define BM_AUDIOOUT_TEST_HP_I1_ADJ 0xc00000 | ||
| 361 | #define BF_AUDIOOUT_TEST_HP_I1_ADJ(v) (((v) << 22) & 0xc00000) | ||
| 362 | #define BP_AUDIOOUT_TEST_HP_IALL_ADJ 20 | ||
| 363 | #define BM_AUDIOOUT_TEST_HP_IALL_ADJ 0x300000 | ||
| 364 | #define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v) (((v) << 20) & 0x300000) | ||
| 365 | #define BP_AUDIOOUT_TEST_SPKR_I1_ADJ 18 | ||
| 366 | #define BM_AUDIOOUT_TEST_SPKR_I1_ADJ 0xc0000 | ||
| 367 | #define BF_AUDIOOUT_TEST_SPKR_I1_ADJ(v) (((v) << 18) & 0xc0000) | ||
| 368 | #define BP_AUDIOOUT_TEST_SPKR_IALL_ADJ 16 | ||
| 369 | #define BM_AUDIOOUT_TEST_SPKR_IALL_ADJ 0x30000 | ||
| 370 | #define BF_AUDIOOUT_TEST_SPKR_IALL_ADJ(v) (((v) << 16) & 0x30000) | ||
| 371 | #define BP_AUDIOOUT_TEST_VAG_CLASSA 13 | ||
| 372 | #define BM_AUDIOOUT_TEST_VAG_CLASSA 0x2000 | ||
| 373 | #define BF_AUDIOOUT_TEST_VAG_CLASSA(v) (((v) << 13) & 0x2000) | ||
| 374 | #define BP_AUDIOOUT_TEST_VAG_DOUBLE_I 12 | ||
| 375 | #define BM_AUDIOOUT_TEST_VAG_DOUBLE_I 0x1000 | ||
| 376 | #define BF_AUDIOOUT_TEST_VAG_DOUBLE_I(v) (((v) << 12) & 0x1000) | ||
| 377 | #define BP_AUDIOOUT_TEST_HP_CHOPCLK 8 | ||
| 378 | #define BM_AUDIOOUT_TEST_HP_CHOPCLK 0x300 | ||
| 379 | #define BF_AUDIOOUT_TEST_HP_CHOPCLK(v) (((v) << 8) & 0x300) | ||
| 380 | #define BP_AUDIOOUT_TEST_DAC_CHOPCLK 4 | ||
| 381 | #define BM_AUDIOOUT_TEST_DAC_CHOPCLK 0x30 | ||
| 382 | #define BF_AUDIOOUT_TEST_DAC_CHOPCLK(v) (((v) << 4) & 0x30) | ||
| 383 | #define BP_AUDIOOUT_TEST_DAC_CLASSA 2 | ||
| 384 | #define BM_AUDIOOUT_TEST_DAC_CLASSA 0x4 | ||
| 385 | #define BF_AUDIOOUT_TEST_DAC_CLASSA(v) (((v) << 2) & 0x4) | ||
| 386 | #define BP_AUDIOOUT_TEST_DAC_DOUBLE_I 1 | ||
| 387 | #define BM_AUDIOOUT_TEST_DAC_DOUBLE_I 0x2 | ||
| 388 | #define BF_AUDIOOUT_TEST_DAC_DOUBLE_I(v) (((v) << 1) & 0x2) | ||
| 389 | #define BP_AUDIOOUT_TEST_DAC_DIS_RTZ 0 | ||
| 390 | #define BM_AUDIOOUT_TEST_DAC_DIS_RTZ 0x1 | ||
| 391 | #define BF_AUDIOOUT_TEST_DAC_DIS_RTZ(v) (((v) << 0) & 0x1) | ||
| 392 | |||
| 393 | /** | ||
| 394 | * Register: HW_AUDIOOUT_BISTCTRL | ||
| 395 | * Address: 0xb0 | ||
| 396 | * SCT: yes | ||
| 397 | */ | ||
| 398 | #define HW_AUDIOOUT_BISTCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x0)) | ||
| 399 | #define HW_AUDIOOUT_BISTCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x4)) | ||
| 400 | #define HW_AUDIOOUT_BISTCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x8)) | ||
| 401 | #define HW_AUDIOOUT_BISTCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0xc)) | ||
| 402 | #define BP_AUDIOOUT_BISTCTRL_FAIL 3 | ||
| 403 | #define BM_AUDIOOUT_BISTCTRL_FAIL 0x8 | ||
| 404 | #define BF_AUDIOOUT_BISTCTRL_FAIL(v) (((v) << 3) & 0x8) | ||
| 405 | #define BP_AUDIOOUT_BISTCTRL_PASS 2 | ||
| 406 | #define BM_AUDIOOUT_BISTCTRL_PASS 0x4 | ||
| 407 | #define BF_AUDIOOUT_BISTCTRL_PASS(v) (((v) << 2) & 0x4) | ||
| 408 | #define BP_AUDIOOUT_BISTCTRL_DONE 1 | ||
| 409 | #define BM_AUDIOOUT_BISTCTRL_DONE 0x2 | ||
| 410 | #define BF_AUDIOOUT_BISTCTRL_DONE(v) (((v) << 1) & 0x2) | ||
| 411 | #define BP_AUDIOOUT_BISTCTRL_START 0 | ||
| 412 | #define BM_AUDIOOUT_BISTCTRL_START 0x1 | ||
| 413 | #define BF_AUDIOOUT_BISTCTRL_START(v) (((v) << 0) & 0x1) | ||
| 414 | |||
| 415 | /** | ||
| 416 | * Register: HW_AUDIOOUT_BISTSTAT0 | ||
| 417 | * Address: 0xc0 | ||
| 418 | * SCT: no | ||
| 419 | */ | ||
| 420 | #define HW_AUDIOOUT_BISTSTAT0 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0)) | ||
| 421 | #define BP_AUDIOOUT_BISTSTAT0_DATA 0 | ||
| 422 | #define BM_AUDIOOUT_BISTSTAT0_DATA 0xffffff | ||
| 423 | #define BF_AUDIOOUT_BISTSTAT0_DATA(v) (((v) << 0) & 0xffffff) | ||
| 424 | |||
| 425 | /** | ||
| 426 | * Register: HW_AUDIOOUT_BISTSTAT1 | ||
| 427 | * Address: 0xd0 | ||
| 428 | * SCT: no | ||
| 429 | */ | ||
| 430 | #define HW_AUDIOOUT_BISTSTAT1 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0)) | ||
| 431 | #define BP_AUDIOOUT_BISTSTAT1_STATE 24 | ||
| 432 | #define BM_AUDIOOUT_BISTSTAT1_STATE 0x1f000000 | ||
| 433 | #define BF_AUDIOOUT_BISTSTAT1_STATE(v) (((v) << 24) & 0x1f000000) | ||
| 434 | #define BP_AUDIOOUT_BISTSTAT1_ADDR 0 | ||
| 435 | #define BM_AUDIOOUT_BISTSTAT1_ADDR 0xff | ||
| 436 | #define BF_AUDIOOUT_BISTSTAT1_ADDR(v) (((v) << 0) & 0xff) | ||
| 437 | |||
| 438 | /** | ||
| 439 | * Register: HW_AUDIOOUT_ANACLKCTRL | ||
| 440 | * Address: 0xe0 | ||
| 441 | * SCT: yes | ||
| 442 | */ | ||
| 443 | #define HW_AUDIOOUT_ANACLKCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x0)) | ||
| 444 | #define HW_AUDIOOUT_ANACLKCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x4)) | ||
| 445 | #define HW_AUDIOOUT_ANACLKCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x8)) | ||
| 446 | #define HW_AUDIOOUT_ANACLKCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0xc)) | ||
| 447 | #define BP_AUDIOOUT_ANACLKCTRL_CLKGATE 31 | ||
| 448 | #define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 | ||
| 449 | #define BF_AUDIOOUT_ANACLKCTRL_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 450 | #define BP_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 4 | ||
| 451 | #define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 0x10 | ||
| 452 | #define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v) (((v) << 4) & 0x10) | ||
| 453 | #define BP_AUDIOOUT_ANACLKCTRL_DACDIV 0 | ||
| 454 | #define BM_AUDIOOUT_ANACLKCTRL_DACDIV 0x7 | ||
| 455 | #define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v) (((v) << 0) & 0x7) | ||
| 456 | |||
| 457 | /** | ||
| 458 | * Register: HW_AUDIOOUT_DATA | ||
| 459 | * Address: 0xf0 | ||
| 460 | * SCT: yes | ||
| 461 | */ | ||
| 462 | #define HW_AUDIOOUT_DATA (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x0)) | ||
| 463 | #define HW_AUDIOOUT_DATA_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x4)) | ||
| 464 | #define HW_AUDIOOUT_DATA_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x8)) | ||
| 465 | #define HW_AUDIOOUT_DATA_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0xc)) | ||
| 466 | #define BP_AUDIOOUT_DATA_HIGH 16 | ||
| 467 | #define BM_AUDIOOUT_DATA_HIGH 0xffff0000 | ||
| 468 | #define BF_AUDIOOUT_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
| 469 | #define BP_AUDIOOUT_DATA_LOW 0 | ||
| 470 | #define BM_AUDIOOUT_DATA_LOW 0xffff | ||
| 471 | #define BF_AUDIOOUT_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
| 472 | |||
| 473 | #endif /* __HEADERGEN__STMP3600__AUDIOOUT__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-brazoiocsr.h b/firmware/target/arm/imx233/regs/stmp3600/regs-brazoiocsr.h new file mode 100644 index 0000000000..903cf09878 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-brazoiocsr.h | |||
| @@ -0,0 +1,30 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__BRAZOIOCSR__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__BRAZOIOCSR__H__ | ||
| 25 | |||
| 26 | #define REGS_BRAZOIOCSR_BASE (0x80038000) | ||
| 27 | |||
| 28 | #define REGS_BRAZOIOCSR_VERSION "2.3.0" | ||
| 29 | |||
| 30 | #endif /* __HEADERGEN__STMP3600__BRAZOIOCSR__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h new file mode 100644 index 0000000000..218298b69d --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h | |||
| @@ -0,0 +1,344 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.4.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__CLKCTRL__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__CLKCTRL__H__ | ||
| 25 | |||
| 26 | #define REGS_CLKCTRL_BASE (0x80040000) | ||
| 27 | |||
| 28 | #define REGS_CLKCTRL_VERSION "2.4.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_CLKCTRL_PLLCTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_CLKCTRL_PLLCTRL0 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_CLKCTRL_PLLCTRL0_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_CLKCTRL_PLLCTRL0_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_CLKCTRL_PLLCTRL0_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_CLKCTRL_PLLCTRL0_PLLVCOKSTART 30 | ||
| 40 | #define BM_CLKCTRL_PLLCTRL0_PLLVCOKSTART 0x40000000 | ||
| 41 | #define BF_CLKCTRL_PLLCTRL0_PLLVCOKSTART(v) (((v) << 30) & 0x40000000) | ||
| 42 | #define BP_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR 29 | ||
| 43 | #define BM_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR 0x20000000 | ||
| 44 | #define BF_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR(v) (((v) << 29) & 0x20000000) | ||
| 45 | #define BP_CLKCTRL_PLLCTRL0_PLLCPDBLIP 28 | ||
| 46 | #define BM_CLKCTRL_PLLCTRL0_PLLCPDBLIP 0x10000000 | ||
| 47 | #define BF_CLKCTRL_PLLCTRL0_PLLCPDBLIP(v) (((v) << 28) & 0x10000000) | ||
| 48 | #define BP_CLKCTRL_PLLCTRL0_PLLCPNSEL 24 | ||
| 49 | #define BM_CLKCTRL_PLLCTRL0_PLLCPNSEL 0x7000000 | ||
| 50 | #define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__DEFAULT 0x0 | ||
| 51 | #define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_15 0x2 | ||
| 52 | #define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_075 0x3 | ||
| 53 | #define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_05 0x4 | ||
| 54 | #define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_04 0x7 | ||
| 55 | #define BF_CLKCTRL_PLLCTRL0_PLLCPNSEL(v) (((v) << 24) & 0x7000000) | ||
| 56 | #define BF_CLKCTRL_PLLCTRL0_PLLCPNSEL_V(v) ((BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__##v << 24) & 0x7000000) | ||
| 57 | #define BP_CLKCTRL_PLLCTRL0_PLLV2ISEL 20 | ||
| 58 | #define BM_CLKCTRL_PLLCTRL0_PLLV2ISEL 0x300000 | ||
| 59 | #define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__NORMAL 0x0 | ||
| 60 | #define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__LOWER 0x1 | ||
| 61 | #define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__LOWEST 0x2 | ||
| 62 | #define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__HIGHEST 0x3 | ||
| 63 | #define BF_CLKCTRL_PLLCTRL0_PLLV2ISEL(v) (((v) << 20) & 0x300000) | ||
| 64 | #define BF_CLKCTRL_PLLCTRL0_PLLV2ISEL_V(v) ((BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__##v << 20) & 0x300000) | ||
| 65 | #define BP_CLKCTRL_PLLCTRL0_FORCE_FREQ 19 | ||
| 66 | #define BM_CLKCTRL_PLLCTRL0_FORCE_FREQ 0x80000 | ||
| 67 | #define BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__FORCE_SAME_FREQ 0x1 | ||
| 68 | #define BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__HONOR_SAME_FREQ_RULE 0x0 | ||
| 69 | #define BF_CLKCTRL_PLLCTRL0_FORCE_FREQ(v) (((v) << 19) & 0x80000) | ||
| 70 | #define BF_CLKCTRL_PLLCTRL0_FORCE_FREQ_V(v) ((BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__##v << 19) & 0x80000) | ||
| 71 | #define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS 18 | ||
| 72 | #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x40000 | ||
| 73 | #define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v) (((v) << 18) & 0x40000) | ||
| 74 | #define BP_CLKCTRL_PLLCTRL0_BYPASS 17 | ||
| 75 | #define BM_CLKCTRL_PLLCTRL0_BYPASS 0x20000 | ||
| 76 | #define BF_CLKCTRL_PLLCTRL0_BYPASS(v) (((v) << 17) & 0x20000) | ||
| 77 | #define BP_CLKCTRL_PLLCTRL0_POWER 16 | ||
| 78 | #define BM_CLKCTRL_PLLCTRL0_POWER 0x10000 | ||
| 79 | #define BF_CLKCTRL_PLLCTRL0_POWER(v) (((v) << 16) & 0x10000) | ||
| 80 | #define BP_CLKCTRL_PLLCTRL0_FREQ 0 | ||
| 81 | #define BM_CLKCTRL_PLLCTRL0_FREQ 0x1ff | ||
| 82 | #define BF_CLKCTRL_PLLCTRL0_FREQ(v) (((v) << 0) & 0x1ff) | ||
| 83 | |||
| 84 | /** | ||
| 85 | * Register: HW_CLKCTRL_PLLCTRL1 | ||
| 86 | * Address: 0x10 | ||
| 87 | * SCT: yes | ||
| 88 | */ | ||
| 89 | #define HW_CLKCTRL_PLLCTRL1 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0x0)) | ||
| 90 | #define HW_CLKCTRL_PLLCTRL1_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0x4)) | ||
| 91 | #define HW_CLKCTRL_PLLCTRL1_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0x8)) | ||
| 92 | #define HW_CLKCTRL_PLLCTRL1_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0xc)) | ||
| 93 | #define BP_CLKCTRL_PLLCTRL1_LOCK 31 | ||
| 94 | #define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 | ||
| 95 | #define BF_CLKCTRL_PLLCTRL1_LOCK(v) (((v) << 31) & 0x80000000) | ||
| 96 | #define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK 30 | ||
| 97 | #define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 | ||
| 98 | #define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v) (((v) << 30) & 0x40000000) | ||
| 99 | #define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 | ||
| 100 | #define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0xffff | ||
| 101 | #define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) (((v) << 0) & 0xffff) | ||
| 102 | |||
| 103 | /** | ||
| 104 | * Register: HW_CLKCTRL_CPU | ||
| 105 | * Address: 0x20 | ||
| 106 | * SCT: no | ||
| 107 | */ | ||
| 108 | #define HW_CLKCTRL_CPU (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20)) | ||
| 109 | #define BP_CLKCTRL_CPU_WAIT_PLL_LOCK 30 | ||
| 110 | #define BM_CLKCTRL_CPU_WAIT_PLL_LOCK 0x40000000 | ||
| 111 | #define BF_CLKCTRL_CPU_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
| 112 | #define BP_CLKCTRL_CPU_BUSY 29 | ||
| 113 | #define BM_CLKCTRL_CPU_BUSY 0x20000000 | ||
| 114 | #define BF_CLKCTRL_CPU_BUSY(v) (((v) << 29) & 0x20000000) | ||
| 115 | #define BP_CLKCTRL_CPU_INTERRUPT_WAIT 12 | ||
| 116 | #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x1000 | ||
| 117 | #define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v) (((v) << 12) & 0x1000) | ||
| 118 | #define BP_CLKCTRL_CPU_DIV 0 | ||
| 119 | #define BM_CLKCTRL_CPU_DIV 0x3ff | ||
| 120 | #define BF_CLKCTRL_CPU_DIV(v) (((v) << 0) & 0x3ff) | ||
| 121 | |||
| 122 | /** | ||
| 123 | * Register: HW_CLKCTRL_HBUS | ||
| 124 | * Address: 0x30 | ||
| 125 | * SCT: no | ||
| 126 | */ | ||
| 127 | #define HW_CLKCTRL_HBUS (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30)) | ||
| 128 | #define BP_CLKCTRL_HBUS_WAIT_PLL_LOCK 30 | ||
| 129 | #define BM_CLKCTRL_HBUS_WAIT_PLL_LOCK 0x40000000 | ||
| 130 | #define BF_CLKCTRL_HBUS_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
| 131 | #define BP_CLKCTRL_HBUS_BUSY 29 | ||
| 132 | #define BM_CLKCTRL_HBUS_BUSY 0x20000000 | ||
| 133 | #define BF_CLKCTRL_HBUS_BUSY(v) (((v) << 29) & 0x20000000) | ||
| 134 | #define BP_CLKCTRL_HBUS_EMI_BUSY_FAST 27 | ||
| 135 | #define BM_CLKCTRL_HBUS_EMI_BUSY_FAST 0x8000000 | ||
| 136 | #define BF_CLKCTRL_HBUS_EMI_BUSY_FAST(v) (((v) << 27) & 0x8000000) | ||
| 137 | #define BP_CLKCTRL_HBUS_APBHDMA_BUSY_FAST 26 | ||
| 138 | #define BM_CLKCTRL_HBUS_APBHDMA_BUSY_FAST 0x4000000 | ||
| 139 | #define BF_CLKCTRL_HBUS_APBHDMA_BUSY_FAST(v) (((v) << 26) & 0x4000000) | ||
| 140 | #define BP_CLKCTRL_HBUS_APBXDMA_BUSY_FAST 25 | ||
| 141 | #define BM_CLKCTRL_HBUS_APBXDMA_BUSY_FAST 0x2000000 | ||
| 142 | #define BF_CLKCTRL_HBUS_APBXDMA_BUSY_FAST(v) (((v) << 25) & 0x2000000) | ||
| 143 | #define BP_CLKCTRL_HBUS_TRAFFIC_JAM_FAST 24 | ||
| 144 | #define BM_CLKCTRL_HBUS_TRAFFIC_JAM_FAST 0x1000000 | ||
| 145 | #define BF_CLKCTRL_HBUS_TRAFFIC_JAM_FAST(v) (((v) << 24) & 0x1000000) | ||
| 146 | #define BP_CLKCTRL_HBUS_TRAFFIC_FAST 23 | ||
| 147 | #define BM_CLKCTRL_HBUS_TRAFFIC_FAST 0x800000 | ||
| 148 | #define BF_CLKCTRL_HBUS_TRAFFIC_FAST(v) (((v) << 23) & 0x800000) | ||
| 149 | #define BP_CLKCTRL_HBUS_CPU_DATA_FAST 22 | ||
| 150 | #define BM_CLKCTRL_HBUS_CPU_DATA_FAST 0x400000 | ||
| 151 | #define BF_CLKCTRL_HBUS_CPU_DATA_FAST(v) (((v) << 22) & 0x400000) | ||
| 152 | #define BP_CLKCTRL_HBUS_CPU_INSTR_FAST 21 | ||
| 153 | #define BM_CLKCTRL_HBUS_CPU_INSTR_FAST 0x200000 | ||
| 154 | #define BF_CLKCTRL_HBUS_CPU_INSTR_FAST(v) (((v) << 21) & 0x200000) | ||
| 155 | #define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE 20 | ||
| 156 | #define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x100000 | ||
| 157 | #define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v) (((v) << 20) & 0x100000) | ||
| 158 | #define BP_CLKCTRL_HBUS_SLOW_DIV 16 | ||
| 159 | #define BM_CLKCTRL_HBUS_SLOW_DIV 0x30000 | ||
| 160 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 | ||
| 161 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 | ||
| 162 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 | ||
| 163 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 | ||
| 164 | #define BF_CLKCTRL_HBUS_SLOW_DIV(v) (((v) << 16) & 0x30000) | ||
| 165 | #define BF_CLKCTRL_HBUS_SLOW_DIV_V(v) ((BV_CLKCTRL_HBUS_SLOW_DIV__##v << 16) & 0x30000) | ||
| 166 | #define BP_CLKCTRL_HBUS_DIV 0 | ||
| 167 | #define BM_CLKCTRL_HBUS_DIV 0x1f | ||
| 168 | #define BF_CLKCTRL_HBUS_DIV(v) (((v) << 0) & 0x1f) | ||
| 169 | |||
| 170 | /** | ||
| 171 | * Register: HW_CLKCTRL_XBUS | ||
| 172 | * Address: 0x40 | ||
| 173 | * SCT: no | ||
| 174 | */ | ||
| 175 | #define HW_CLKCTRL_XBUS (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x40)) | ||
| 176 | #define BP_CLKCTRL_XBUS_BUSY 31 | ||
| 177 | #define BM_CLKCTRL_XBUS_BUSY 0x80000000 | ||
| 178 | #define BF_CLKCTRL_XBUS_BUSY(v) (((v) << 31) & 0x80000000) | ||
| 179 | #define BP_CLKCTRL_XBUS_DIV 0 | ||
| 180 | #define BM_CLKCTRL_XBUS_DIV 0x3ff | ||
| 181 | #define BF_CLKCTRL_XBUS_DIV(v) (((v) << 0) & 0x3ff) | ||
| 182 | |||
| 183 | /** | ||
| 184 | * Register: HW_CLKCTRL_XTAL | ||
| 185 | * Address: 0x50 | ||
| 186 | * SCT: no | ||
| 187 | */ | ||
| 188 | #define HW_CLKCTRL_XTAL (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50)) | ||
| 189 | #define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 | ||
| 190 | #define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 | ||
| 191 | #define BF_CLKCTRL_XTAL_UART_CLK_GATE(v) (((v) << 31) & 0x80000000) | ||
| 192 | #define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30 | ||
| 193 | #define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 | ||
| 194 | #define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v) (((v) << 30) & 0x40000000) | ||
| 195 | #define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 | ||
| 196 | #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 | ||
| 197 | #define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v) (((v) << 29) & 0x20000000) | ||
| 198 | #define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE 28 | ||
| 199 | #define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 | ||
| 200 | #define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v) (((v) << 28) & 0x10000000) | ||
| 201 | #define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 27 | ||
| 202 | #define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x8000000 | ||
| 203 | #define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v) (((v) << 27) & 0x8000000) | ||
| 204 | #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 | ||
| 205 | #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x4000000 | ||
| 206 | #define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v) (((v) << 26) & 0x4000000) | ||
| 207 | #define BP_CLKCTRL_XTAL_EXRAM_CLK16K_GATE 25 | ||
| 208 | #define BM_CLKCTRL_XTAL_EXRAM_CLK16K_GATE 0x2000000 | ||
| 209 | #define BF_CLKCTRL_XTAL_EXRAM_CLK16K_GATE(v) (((v) << 25) & 0x2000000) | ||
| 210 | #define BP_CLKCTRL_XTAL_LRADC_CLK2K_GATE 24 | ||
| 211 | #define BM_CLKCTRL_XTAL_LRADC_CLK2K_GATE 0x1000000 | ||
| 212 | #define BF_CLKCTRL_XTAL_LRADC_CLK2K_GATE(v) (((v) << 24) & 0x1000000) | ||
| 213 | |||
| 214 | /** | ||
| 215 | * Register: HW_CLKCTRL_OCRAM | ||
| 216 | * Address: 0x60 | ||
| 217 | * SCT: no | ||
| 218 | */ | ||
| 219 | #define HW_CLKCTRL_OCRAM (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x60)) | ||
| 220 | #define BP_CLKCTRL_OCRAM_CLKGATE 31 | ||
| 221 | #define BM_CLKCTRL_OCRAM_CLKGATE 0x80000000 | ||
| 222 | #define BF_CLKCTRL_OCRAM_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 223 | #define BP_CLKCTRL_OCRAM_BUSY 30 | ||
| 224 | #define BM_CLKCTRL_OCRAM_BUSY 0x40000000 | ||
| 225 | #define BF_CLKCTRL_OCRAM_BUSY(v) (((v) << 30) & 0x40000000) | ||
| 226 | #define BP_CLKCTRL_OCRAM_DIV 0 | ||
| 227 | #define BM_CLKCTRL_OCRAM_DIV 0x3ff | ||
| 228 | #define BF_CLKCTRL_OCRAM_DIV(v) (((v) << 0) & 0x3ff) | ||
| 229 | |||
| 230 | /** | ||
| 231 | * Register: HW_CLKCTRL_UTMI | ||
| 232 | * Address: 0x70 | ||
| 233 | * SCT: no | ||
| 234 | */ | ||
| 235 | #define HW_CLKCTRL_UTMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x70)) | ||
| 236 | #define BP_CLKCTRL_UTMI_UTMI_CLK120M_GATE 31 | ||
| 237 | #define BM_CLKCTRL_UTMI_UTMI_CLK120M_GATE 0x80000000 | ||
| 238 | #define BF_CLKCTRL_UTMI_UTMI_CLK120M_GATE(v) (((v) << 31) & 0x80000000) | ||
| 239 | #define BP_CLKCTRL_UTMI_UTMI_CLK30M_GATE 30 | ||
| 240 | #define BM_CLKCTRL_UTMI_UTMI_CLK30M_GATE 0x40000000 | ||
| 241 | #define BF_CLKCTRL_UTMI_UTMI_CLK30M_GATE(v) (((v) << 30) & 0x40000000) | ||
| 242 | |||
| 243 | /** | ||
| 244 | * Register: HW_CLKCTRL_SSP | ||
| 245 | * Address: 0x80 | ||
| 246 | * SCT: no | ||
| 247 | */ | ||
| 248 | #define HW_CLKCTRL_SSP (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x80)) | ||
| 249 | #define BP_CLKCTRL_SSP_CLKGATE 31 | ||
| 250 | #define BM_CLKCTRL_SSP_CLKGATE 0x80000000 | ||
| 251 | #define BF_CLKCTRL_SSP_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 252 | #define BP_CLKCTRL_SSP_WAIT_PLL_LOCK 30 | ||
| 253 | #define BM_CLKCTRL_SSP_WAIT_PLL_LOCK 0x40000000 | ||
| 254 | #define BF_CLKCTRL_SSP_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
| 255 | #define BP_CLKCTRL_SSP_BUSY 29 | ||
| 256 | #define BM_CLKCTRL_SSP_BUSY 0x20000000 | ||
| 257 | #define BF_CLKCTRL_SSP_BUSY(v) (((v) << 29) & 0x20000000) | ||
| 258 | #define BP_CLKCTRL_SSP_DIV 0 | ||
| 259 | #define BM_CLKCTRL_SSP_DIV 0x1ff | ||
| 260 | #define BF_CLKCTRL_SSP_DIV(v) (((v) << 0) & 0x1ff) | ||
| 261 | |||
| 262 | /** | ||
| 263 | * Register: HW_CLKCTRL_GPMI | ||
| 264 | * Address: 0x90 | ||
| 265 | * SCT: no | ||
| 266 | */ | ||
| 267 | #define HW_CLKCTRL_GPMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x90)) | ||
| 268 | #define BP_CLKCTRL_GPMI_CLKGATE 31 | ||
| 269 | #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 | ||
| 270 | #define BF_CLKCTRL_GPMI_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 271 | #define BP_CLKCTRL_GPMI_WAIT_PLL_LOCK 30 | ||
| 272 | #define BM_CLKCTRL_GPMI_WAIT_PLL_LOCK 0x40000000 | ||
| 273 | #define BF_CLKCTRL_GPMI_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
| 274 | #define BP_CLKCTRL_GPMI_BUSY 29 | ||
| 275 | #define BM_CLKCTRL_GPMI_BUSY 0x20000000 | ||
| 276 | #define BF_CLKCTRL_GPMI_BUSY(v) (((v) << 29) & 0x20000000) | ||
| 277 | #define BP_CLKCTRL_GPMI_DIV 0 | ||
| 278 | #define BM_CLKCTRL_GPMI_DIV 0x3ff | ||
| 279 | #define BF_CLKCTRL_GPMI_DIV(v) (((v) << 0) & 0x3ff) | ||
| 280 | |||
| 281 | /** | ||
| 282 | * Register: HW_CLKCTRL_SPDIF | ||
| 283 | * Address: 0xa0 | ||
| 284 | * SCT: no | ||
| 285 | */ | ||
| 286 | #define HW_CLKCTRL_SPDIF (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xa0)) | ||
| 287 | #define BP_CLKCTRL_SPDIF_CLKGATE 31 | ||
| 288 | #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 | ||
| 289 | #define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 290 | #define BP_CLKCTRL_SPDIF_BUSY 30 | ||
| 291 | #define BM_CLKCTRL_SPDIF_BUSY 0x40000000 | ||
| 292 | #define BF_CLKCTRL_SPDIF_BUSY(v) (((v) << 30) & 0x40000000) | ||
| 293 | #define BP_CLKCTRL_SPDIF_DIV 0 | ||
| 294 | #define BM_CLKCTRL_SPDIF_DIV 0x7 | ||
| 295 | #define BF_CLKCTRL_SPDIF_DIV(v) (((v) << 0) & 0x7) | ||
| 296 | |||
| 297 | /** | ||
| 298 | * Register: HW_CLKCTRL_EMI | ||
| 299 | * Address: 0xb0 | ||
| 300 | * SCT: no | ||
| 301 | */ | ||
| 302 | #define HW_CLKCTRL_EMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xb0)) | ||
| 303 | #define BP_CLKCTRL_EMI_CLKGATE 31 | ||
| 304 | #define BM_CLKCTRL_EMI_CLKGATE 0x80000000 | ||
| 305 | #define BF_CLKCTRL_EMI_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 306 | #define BP_CLKCTRL_EMI_WAIT_PLL_LOCK 30 | ||
| 307 | #define BM_CLKCTRL_EMI_WAIT_PLL_LOCK 0x40000000 | ||
| 308 | #define BF_CLKCTRL_EMI_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
| 309 | #define BP_CLKCTRL_EMI_BUSY 29 | ||
| 310 | #define BM_CLKCTRL_EMI_BUSY 0x20000000 | ||
| 311 | #define BF_CLKCTRL_EMI_BUSY(v) (((v) << 29) & 0x20000000) | ||
| 312 | #define BP_CLKCTRL_EMI_DIV 0 | ||
| 313 | #define BM_CLKCTRL_EMI_DIV 0x7 | ||
| 314 | #define BF_CLKCTRL_EMI_DIV(v) (((v) << 0) & 0x7) | ||
| 315 | |||
| 316 | /** | ||
| 317 | * Register: HW_CLKCTRL_IR | ||
| 318 | * Address: 0xc0 | ||
| 319 | * SCT: no | ||
| 320 | */ | ||
| 321 | #define HW_CLKCTRL_IR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xc0)) | ||
| 322 | #define BP_CLKCTRL_IR_CLKGATE 31 | ||
| 323 | #define BM_CLKCTRL_IR_CLKGATE 0x80000000 | ||
| 324 | #define BF_CLKCTRL_IR_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 325 | #define BP_CLKCTRL_IR_WAIT_PLL_LOCK 30 | ||
| 326 | #define BM_CLKCTRL_IR_WAIT_PLL_LOCK 0x40000000 | ||
| 327 | #define BF_CLKCTRL_IR_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
| 328 | #define BP_CLKCTRL_IR_AUTO_DIV 29 | ||
| 329 | #define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 | ||
| 330 | #define BF_CLKCTRL_IR_AUTO_DIV(v) (((v) << 29) & 0x20000000) | ||
| 331 | #define BP_CLKCTRL_IR_IR_BUSY 28 | ||
| 332 | #define BM_CLKCTRL_IR_IR_BUSY 0x10000000 | ||
| 333 | #define BF_CLKCTRL_IR_IR_BUSY(v) (((v) << 28) & 0x10000000) | ||
| 334 | #define BP_CLKCTRL_IR_IROV_BUSY 27 | ||
| 335 | #define BM_CLKCTRL_IR_IROV_BUSY 0x8000000 | ||
| 336 | #define BF_CLKCTRL_IR_IROV_BUSY(v) (((v) << 27) & 0x8000000) | ||
| 337 | #define BP_CLKCTRL_IR_IROV_DIV 16 | ||
| 338 | #define BM_CLKCTRL_IR_IROV_DIV 0x1ff0000 | ||
| 339 | #define BF_CLKCTRL_IR_IROV_DIV(v) (((v) << 16) & 0x1ff0000) | ||
| 340 | #define BP_CLKCTRL_IR_IR_DIV 0 | ||
| 341 | #define BM_CLKCTRL_IR_IR_DIV 0x3ff | ||
| 342 | #define BF_CLKCTRL_IR_IR_DIV(v) (((v) << 0) & 0x3ff) | ||
| 343 | |||
| 344 | #endif /* __HEADERGEN__STMP3600__CLKCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-dacdma.h b/firmware/target/arm/imx233/regs/stmp3600/regs-dacdma.h new file mode 100644 index 0000000000..5d2fe44fb1 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-dacdma.h | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__DACDMA__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__DACDMA__H__ | ||
| 25 | |||
| 26 | #define REGS_DACDMA_BASE (0x8004c000) | ||
| 27 | |||
| 28 | #define REGS_DACDMA_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_DACDMA_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_DACDMA_CTRL (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_DACDMA_CTRL_SET (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_DACDMA_CTRL_CLR (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_DACDMA_CTRL_TOG (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_DACDMA_CTRL_SFTRST 31 | ||
| 40 | #define BM_DACDMA_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_DACDMA_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_DACDMA_CTRL_CLKGATE 30 | ||
| 43 | #define BM_DACDMA_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_DACDMA_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_DACDMA_CTRL_RUN 0 | ||
| 46 | #define BM_DACDMA_CTRL_RUN 0x1 | ||
| 47 | #define BF_DACDMA_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
| 48 | |||
| 49 | /** | ||
| 50 | * Register: HW_DACDMA_DATA | ||
| 51 | * Address: 0x80 | ||
| 52 | * SCT: no | ||
| 53 | */ | ||
| 54 | #define HW_DACDMA_DATA (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x80)) | ||
| 55 | #define BP_DACDMA_DATA_HIGH 16 | ||
| 56 | #define BM_DACDMA_DATA_HIGH 0xffff0000 | ||
| 57 | #define BF_DACDMA_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
| 58 | #define BP_DACDMA_DATA_LOW 0 | ||
| 59 | #define BM_DACDMA_DATA_LOW 0xffff | ||
| 60 | #define BF_DACDMA_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
| 61 | |||
| 62 | #endif /* __HEADERGEN__STMP3600__DACDMA__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h new file mode 100644 index 0000000000..a7b45a7ca9 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h | |||
| @@ -0,0 +1,595 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__DIGCTL__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__DIGCTL__H__ | ||
| 25 | |||
| 26 | #define REGS_DIGCTL_BASE (0x8001c000) | ||
| 27 | |||
| 28 | #define REGS_DIGCTL_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_DIGCTL_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_DIGCTL_CTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_DIGCTL_CTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_DIGCTL_CTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_DIGCTL_CTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_DIGCTL_CTRL_MASTER_SELECT 24 | ||
| 40 | #define BM_DIGCTL_CTRL_MASTER_SELECT 0x1f000000 | ||
| 41 | #define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_I 0x1 | ||
| 42 | #define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_D 0x2 | ||
| 43 | #define BV_DIGCTL_CTRL_MASTER_SELECT__USB 0x4 | ||
| 44 | #define BV_DIGCTL_CTRL_MASTER_SELECT__APBH 0x8 | ||
| 45 | #define BV_DIGCTL_CTRL_MASTER_SELECT__APBX 0x10 | ||
| 46 | #define BF_DIGCTL_CTRL_MASTER_SELECT(v) (((v) << 24) & 0x1f000000) | ||
| 47 | #define BF_DIGCTL_CTRL_MASTER_SELECT_V(v) ((BV_DIGCTL_CTRL_MASTER_SELECT__##v << 24) & 0x1f000000) | ||
| 48 | #define BP_DIGCTL_CTRL_USB_TESTMODE 20 | ||
| 49 | #define BM_DIGCTL_CTRL_USB_TESTMODE 0x100000 | ||
| 50 | #define BF_DIGCTL_CTRL_USB_TESTMODE(v) (((v) << 20) & 0x100000) | ||
| 51 | #define BP_DIGCTL_CTRL_ANALOG_TESTMODE 19 | ||
| 52 | #define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x80000 | ||
| 53 | #define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v) (((v) << 19) & 0x80000) | ||
| 54 | #define BP_DIGCTL_CTRL_DIGITAL_TESTMODE 18 | ||
| 55 | #define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x40000 | ||
| 56 | #define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v) (((v) << 18) & 0x40000) | ||
| 57 | #define BP_DIGCTL_CTRL_UTMI_TESTMODE 17 | ||
| 58 | #define BM_DIGCTL_CTRL_UTMI_TESTMODE 0x20000 | ||
| 59 | #define BF_DIGCTL_CTRL_UTMI_TESTMODE(v) (((v) << 17) & 0x20000) | ||
| 60 | #define BP_DIGCTL_CTRL_UART_LOOPBACK 16 | ||
| 61 | #define BM_DIGCTL_CTRL_UART_LOOPBACK 0x10000 | ||
| 62 | #define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0 | ||
| 63 | #define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1 | ||
| 64 | #define BF_DIGCTL_CTRL_UART_LOOPBACK(v) (((v) << 16) & 0x10000) | ||
| 65 | #define BF_DIGCTL_CTRL_UART_LOOPBACK_V(v) ((BV_DIGCTL_CTRL_UART_LOOPBACK__##v << 16) & 0x10000) | ||
| 66 | #define BP_DIGCTL_CTRL_DEBUG_DISABLE 3 | ||
| 67 | #define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x8 | ||
| 68 | #define BF_DIGCTL_CTRL_DEBUG_DISABLE(v) (((v) << 3) & 0x8) | ||
| 69 | #define BP_DIGCTL_CTRL_USB_CLKGATE 2 | ||
| 70 | #define BM_DIGCTL_CTRL_USB_CLKGATE 0x4 | ||
| 71 | #define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0 | ||
| 72 | #define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1 | ||
| 73 | #define BF_DIGCTL_CTRL_USB_CLKGATE(v) (((v) << 2) & 0x4) | ||
| 74 | #define BF_DIGCTL_CTRL_USB_CLKGATE_V(v) ((BV_DIGCTL_CTRL_USB_CLKGATE__##v << 2) & 0x4) | ||
| 75 | #define BP_DIGCTL_CTRL_JTAG_SHIELD 1 | ||
| 76 | #define BM_DIGCTL_CTRL_JTAG_SHIELD 0x2 | ||
| 77 | #define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 | ||
| 78 | #define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 | ||
| 79 | #define BF_DIGCTL_CTRL_JTAG_SHIELD(v) (((v) << 1) & 0x2) | ||
| 80 | #define BF_DIGCTL_CTRL_JTAG_SHIELD_V(v) ((BV_DIGCTL_CTRL_JTAG_SHIELD__##v << 1) & 0x2) | ||
| 81 | #define BP_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE 0 | ||
| 82 | #define BM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE 0x1 | ||
| 83 | #define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__DISABLE 0x0 | ||
| 84 | #define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__ENABLE 0x1 | ||
| 85 | #define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE(v) (((v) << 0) & 0x1) | ||
| 86 | #define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE_V(v) ((BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__##v << 0) & 0x1) | ||
| 87 | |||
| 88 | /** | ||
| 89 | * Register: HW_DIGCTL_STATUS | ||
| 90 | * Address: 0x10 | ||
| 91 | * SCT: no | ||
| 92 | */ | ||
| 93 | #define HW_DIGCTL_STATUS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10)) | ||
| 94 | #define BP_DIGCTL_STATUS_ROM_KEYS_PRESENT 31 | ||
| 95 | #define BM_DIGCTL_STATUS_ROM_KEYS_PRESENT 0x80000000 | ||
| 96 | #define BF_DIGCTL_STATUS_ROM_KEYS_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 97 | #define BP_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT 6 | ||
| 98 | #define BM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT 0x40 | ||
| 99 | #define BF_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT(v) (((v) << 6) & 0x40) | ||
| 100 | #define BP_DIGCTL_STATUS_ROM_SHIELDED 5 | ||
| 101 | #define BM_DIGCTL_STATUS_ROM_SHIELDED 0x20 | ||
| 102 | #define BF_DIGCTL_STATUS_ROM_SHIELDED(v) (((v) << 5) & 0x20) | ||
| 103 | #define BP_DIGCTL_STATUS_JTAG_IN_USE 4 | ||
| 104 | #define BM_DIGCTL_STATUS_JTAG_IN_USE 0x10 | ||
| 105 | #define BF_DIGCTL_STATUS_JTAG_IN_USE(v) (((v) << 4) & 0x10) | ||
| 106 | #define BP_DIGCTL_STATUS_PSWITCH 2 | ||
| 107 | #define BM_DIGCTL_STATUS_PSWITCH 0xc | ||
| 108 | #define BF_DIGCTL_STATUS_PSWITCH(v) (((v) << 2) & 0xc) | ||
| 109 | #define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 | ||
| 110 | #define BM_DIGCTL_STATUS_PACKAGE_TYPE 0x2 | ||
| 111 | #define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) (((v) << 1) & 0x2) | ||
| 112 | #define BP_DIGCTL_STATUS_WRITTEN 0 | ||
| 113 | #define BM_DIGCTL_STATUS_WRITTEN 0x1 | ||
| 114 | #define BF_DIGCTL_STATUS_WRITTEN(v) (((v) << 0) & 0x1) | ||
| 115 | |||
| 116 | /** | ||
| 117 | * Register: HW_DIGCTL_HCLKCOUNT | ||
| 118 | * Address: 0x20 | ||
| 119 | * SCT: no | ||
| 120 | */ | ||
| 121 | #define HW_DIGCTL_HCLKCOUNT (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20)) | ||
| 122 | #define BP_DIGCTL_HCLKCOUNT_COUNT 0 | ||
| 123 | #define BM_DIGCTL_HCLKCOUNT_COUNT 0xffffffff | ||
| 124 | #define BF_DIGCTL_HCLKCOUNT_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 125 | |||
| 126 | /** | ||
| 127 | * Register: HW_DIGCTL_RAMCTRL | ||
| 128 | * Address: 0x30 | ||
| 129 | * SCT: yes | ||
| 130 | */ | ||
| 131 | #define HW_DIGCTL_RAMCTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x0)) | ||
| 132 | #define HW_DIGCTL_RAMCTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x4)) | ||
| 133 | #define HW_DIGCTL_RAMCTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x8)) | ||
| 134 | #define HW_DIGCTL_RAMCTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0xc)) | ||
| 135 | #define BP_DIGCTL_RAMCTRL_TEST_MARGIN 28 | ||
| 136 | #define BM_DIGCTL_RAMCTRL_TEST_MARGIN 0x70000000 | ||
| 137 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__NORMAL 0x0 | ||
| 138 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL1 0x1 | ||
| 139 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL2 0x2 | ||
| 140 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL3 0x3 | ||
| 141 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL4 0x4 | ||
| 142 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL5 0x5 | ||
| 143 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL6 0x6 | ||
| 144 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL7 0x7 | ||
| 145 | #define BF_DIGCTL_RAMCTRL_TEST_MARGIN(v) (((v) << 28) & 0x70000000) | ||
| 146 | #define BF_DIGCTL_RAMCTRL_TEST_MARGIN_V(v) ((BV_DIGCTL_RAMCTRL_TEST_MARGIN__##v << 28) & 0x70000000) | ||
| 147 | #define BP_DIGCTL_RAMCTRL_PWDN_BANKS 24 | ||
| 148 | #define BM_DIGCTL_RAMCTRL_PWDN_BANKS 0xf000000 | ||
| 149 | #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK3 0x8 | ||
| 150 | #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK2 0x4 | ||
| 151 | #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK1 0x2 | ||
| 152 | #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK0 0x1 | ||
| 153 | #define BF_DIGCTL_RAMCTRL_PWDN_BANKS(v) (((v) << 24) & 0xf000000) | ||
| 154 | #define BF_DIGCTL_RAMCTRL_PWDN_BANKS_V(v) ((BV_DIGCTL_RAMCTRL_PWDN_BANKS__##v << 24) & 0xf000000) | ||
| 155 | #define BP_DIGCTL_RAMCTRL_TEMP_SENSOR 20 | ||
| 156 | #define BM_DIGCTL_RAMCTRL_TEMP_SENSOR 0x700000 | ||
| 157 | #define BF_DIGCTL_RAMCTRL_TEMP_SENSOR(v) (((v) << 20) & 0x700000) | ||
| 158 | #define BP_DIGCTL_RAMCTRL_TEST_TEMP_COMP 16 | ||
| 159 | #define BM_DIGCTL_RAMCTRL_TEST_TEMP_COMP 0x70000 | ||
| 160 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__LOW_TEMP 0x1 | ||
| 161 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_A 0x2 | ||
| 162 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_B 0x3 | ||
| 163 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_C 0x4 | ||
| 164 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_D 0x5 | ||
| 165 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_E 0x6 | ||
| 166 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_F 0x7 | ||
| 167 | #define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP(v) (((v) << 16) & 0x70000) | ||
| 168 | #define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP_V(v) ((BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__##v << 16) & 0x70000) | ||
| 169 | #define BP_DIGCTL_RAMCTRL_SHIFT_COUNT 8 | ||
| 170 | #define BM_DIGCTL_RAMCTRL_SHIFT_COUNT 0x7f00 | ||
| 171 | #define BF_DIGCTL_RAMCTRL_SHIFT_COUNT(v) (((v) << 8) & 0x7f00) | ||
| 172 | #define BP_DIGCTL_RAMCTRL_FLIP_CLK 7 | ||
| 173 | #define BM_DIGCTL_RAMCTRL_FLIP_CLK 0x80 | ||
| 174 | #define BV_DIGCTL_RAMCTRL_FLIP_CLK__NORMAL 0x0 | ||
| 175 | #define BV_DIGCTL_RAMCTRL_FLIP_CLK__INVERT 0x1 | ||
| 176 | #define BF_DIGCTL_RAMCTRL_FLIP_CLK(v) (((v) << 7) & 0x80) | ||
| 177 | #define BF_DIGCTL_RAMCTRL_FLIP_CLK_V(v) ((BV_DIGCTL_RAMCTRL_FLIP_CLK__##v << 7) & 0x80) | ||
| 178 | #define BP_DIGCTL_RAMCTRL_OVER_RIDE_TEMP 3 | ||
| 179 | #define BM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP 0x8 | ||
| 180 | #define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__NORMAL 0x0 | ||
| 181 | #define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__OVER_RIDE 0x1 | ||
| 182 | #define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP(v) (((v) << 3) & 0x8) | ||
| 183 | #define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP_V(v) ((BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__##v << 3) & 0x8) | ||
| 184 | #define BP_DIGCTL_RAMCTRL_REF_CLK_GATE 2 | ||
| 185 | #define BM_DIGCTL_RAMCTRL_REF_CLK_GATE 0x4 | ||
| 186 | #define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__NORMAL 0x0 | ||
| 187 | #define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__OFF 0x1 | ||
| 188 | #define BF_DIGCTL_RAMCTRL_REF_CLK_GATE(v) (((v) << 2) & 0x4) | ||
| 189 | #define BF_DIGCTL_RAMCTRL_REF_CLK_GATE_V(v) ((BV_DIGCTL_RAMCTRL_REF_CLK_GATE__##v << 2) & 0x4) | ||
| 190 | #define BP_DIGCTL_RAMCTRL_REPAIR_STATUS 1 | ||
| 191 | #define BM_DIGCTL_RAMCTRL_REPAIR_STATUS 0x2 | ||
| 192 | #define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__IDLE 0x0 | ||
| 193 | #define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__BUSY 0x1 | ||
| 194 | #define BF_DIGCTL_RAMCTRL_REPAIR_STATUS(v) (((v) << 1) & 0x2) | ||
| 195 | #define BF_DIGCTL_RAMCTRL_REPAIR_STATUS_V(v) ((BV_DIGCTL_RAMCTRL_REPAIR_STATUS__##v << 1) & 0x2) | ||
| 196 | #define BP_DIGCTL_RAMCTRL_REPAIR_TRANSMIT 0 | ||
| 197 | #define BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT 0x1 | ||
| 198 | #define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__IDLE 0x0 | ||
| 199 | #define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__SEND 0x1 | ||
| 200 | #define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT(v) (((v) << 0) & 0x1) | ||
| 201 | #define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT_V(v) ((BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__##v << 0) & 0x1) | ||
| 202 | |||
| 203 | /** | ||
| 204 | * Register: HW_DIGCTL_RAMREPAIR0 | ||
| 205 | * Address: 0x40 | ||
| 206 | * SCT: yes | ||
| 207 | */ | ||
| 208 | #define HW_DIGCTL_RAMREPAIR0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x0)) | ||
| 209 | #define HW_DIGCTL_RAMREPAIR0_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x4)) | ||
| 210 | #define HW_DIGCTL_RAMREPAIR0_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x8)) | ||
| 211 | #define HW_DIGCTL_RAMREPAIR0_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0xc)) | ||
| 212 | #define BP_DIGCTL_RAMREPAIR0_EFUSE3 24 | ||
| 213 | #define BM_DIGCTL_RAMREPAIR0_EFUSE3 0x7f000000 | ||
| 214 | #define BF_DIGCTL_RAMREPAIR0_EFUSE3(v) (((v) << 24) & 0x7f000000) | ||
| 215 | #define BP_DIGCTL_RAMREPAIR0_EFUSE2 16 | ||
| 216 | #define BM_DIGCTL_RAMREPAIR0_EFUSE2 0x7f0000 | ||
| 217 | #define BF_DIGCTL_RAMREPAIR0_EFUSE2(v) (((v) << 16) & 0x7f0000) | ||
| 218 | #define BP_DIGCTL_RAMREPAIR0_EFUSE1 8 | ||
| 219 | #define BM_DIGCTL_RAMREPAIR0_EFUSE1 0x7f00 | ||
| 220 | #define BF_DIGCTL_RAMREPAIR0_EFUSE1(v) (((v) << 8) & 0x7f00) | ||
| 221 | #define BP_DIGCTL_RAMREPAIR0_EFUSE0 0 | ||
| 222 | #define BM_DIGCTL_RAMREPAIR0_EFUSE0 0x7f | ||
| 223 | #define BF_DIGCTL_RAMREPAIR0_EFUSE0(v) (((v) << 0) & 0x7f) | ||
| 224 | |||
| 225 | /** | ||
| 226 | * Register: HW_DIGCTL_RAMREPAIR1 | ||
| 227 | * Address: 0x50 | ||
| 228 | * SCT: yes | ||
| 229 | */ | ||
| 230 | #define HW_DIGCTL_RAMREPAIR1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x0)) | ||
| 231 | #define HW_DIGCTL_RAMREPAIR1_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x4)) | ||
| 232 | #define HW_DIGCTL_RAMREPAIR1_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x8)) | ||
| 233 | #define HW_DIGCTL_RAMREPAIR1_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0xc)) | ||
| 234 | #define BP_DIGCTL_RAMREPAIR1_EFUSE3 24 | ||
| 235 | #define BM_DIGCTL_RAMREPAIR1_EFUSE3 0x7f000000 | ||
| 236 | #define BF_DIGCTL_RAMREPAIR1_EFUSE3(v) (((v) << 24) & 0x7f000000) | ||
| 237 | #define BP_DIGCTL_RAMREPAIR1_EFUSE2 16 | ||
| 238 | #define BM_DIGCTL_RAMREPAIR1_EFUSE2 0x7f0000 | ||
| 239 | #define BF_DIGCTL_RAMREPAIR1_EFUSE2(v) (((v) << 16) & 0x7f0000) | ||
| 240 | #define BP_DIGCTL_RAMREPAIR1_EFUSE1 8 | ||
| 241 | #define BM_DIGCTL_RAMREPAIR1_EFUSE1 0x7f00 | ||
| 242 | #define BF_DIGCTL_RAMREPAIR1_EFUSE1(v) (((v) << 8) & 0x7f00) | ||
| 243 | #define BP_DIGCTL_RAMREPAIR1_EFUSE0 0 | ||
| 244 | #define BM_DIGCTL_RAMREPAIR1_EFUSE0 0x7f | ||
| 245 | #define BF_DIGCTL_RAMREPAIR1_EFUSE0(v) (((v) << 0) & 0x7f) | ||
| 246 | |||
| 247 | /** | ||
| 248 | * Register: HW_DIGCTL_WRITEONCE | ||
| 249 | * Address: 0x60 | ||
| 250 | * SCT: no | ||
| 251 | */ | ||
| 252 | #define HW_DIGCTL_WRITEONCE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x60)) | ||
| 253 | #define BP_DIGCTL_WRITEONCE_BITS 0 | ||
| 254 | #define BM_DIGCTL_WRITEONCE_BITS 0xffffffff | ||
| 255 | #define BF_DIGCTL_WRITEONCE_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 256 | |||
| 257 | /** | ||
| 258 | * Register: HW_DIGCTL_AHBCYCLES | ||
| 259 | * Address: 0x70 | ||
| 260 | * SCT: no | ||
| 261 | */ | ||
| 262 | #define HW_DIGCTL_AHBCYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x70)) | ||
| 263 | #define BP_DIGCTL_AHBCYCLES_COUNT 0 | ||
| 264 | #define BM_DIGCTL_AHBCYCLES_COUNT 0xffffffff | ||
| 265 | #define BF_DIGCTL_AHBCYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 266 | |||
| 267 | /** | ||
| 268 | * Register: HW_DIGCTL_AHBSTALLED | ||
| 269 | * Address: 0x80 | ||
| 270 | * SCT: no | ||
| 271 | */ | ||
| 272 | #define HW_DIGCTL_AHBSTALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x80)) | ||
| 273 | #define BP_DIGCTL_AHBSTALLED_COUNT 0 | ||
| 274 | #define BM_DIGCTL_AHBSTALLED_COUNT 0xffffffff | ||
| 275 | #define BF_DIGCTL_AHBSTALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 276 | |||
| 277 | /** | ||
| 278 | * Register: HW_DIGCTL_ENTROPY | ||
| 279 | * Address: 0x90 | ||
| 280 | * SCT: no | ||
| 281 | */ | ||
| 282 | #define HW_DIGCTL_ENTROPY (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x90)) | ||
| 283 | #define BP_DIGCTL_ENTROPY_VALUE 0 | ||
| 284 | #define BM_DIGCTL_ENTROPY_VALUE 0xffffffff | ||
| 285 | #define BF_DIGCTL_ENTROPY_VALUE(v) (((v) << 0) & 0xffffffff) | ||
| 286 | |||
| 287 | /** | ||
| 288 | * Register: HW_DIGCTL_ROMSHIELD | ||
| 289 | * Address: 0xa0 | ||
| 290 | * SCT: no | ||
| 291 | */ | ||
| 292 | #define HW_DIGCTL_ROMSHIELD (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xa0)) | ||
| 293 | #define BP_DIGCTL_ROMSHIELD_WRITE_ONCE 0 | ||
| 294 | #define BM_DIGCTL_ROMSHIELD_WRITE_ONCE 0x1 | ||
| 295 | #define BF_DIGCTL_ROMSHIELD_WRITE_ONCE(v) (((v) << 0) & 0x1) | ||
| 296 | |||
| 297 | /** | ||
| 298 | * Register: HW_DIGCTL_MICROSECONDS | ||
| 299 | * Address: 0xb0 | ||
| 300 | * SCT: yes | ||
| 301 | */ | ||
| 302 | #define HW_DIGCTL_MICROSECONDS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x0)) | ||
| 303 | #define HW_DIGCTL_MICROSECONDS_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x4)) | ||
| 304 | #define HW_DIGCTL_MICROSECONDS_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x8)) | ||
| 305 | #define HW_DIGCTL_MICROSECONDS_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0xc)) | ||
| 306 | #define BP_DIGCTL_MICROSECONDS_VALUE 0 | ||
| 307 | #define BM_DIGCTL_MICROSECONDS_VALUE 0xffffffff | ||
| 308 | #define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) << 0) & 0xffffffff) | ||
| 309 | |||
| 310 | /** | ||
| 311 | * Register: HW_DIGCTL_DBGRD | ||
| 312 | * Address: 0xc0 | ||
| 313 | * SCT: no | ||
| 314 | */ | ||
| 315 | #define HW_DIGCTL_DBGRD (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0)) | ||
| 316 | #define BP_DIGCTL_DBGRD_COMPLEMENT 0 | ||
| 317 | #define BM_DIGCTL_DBGRD_COMPLEMENT 0xffffffff | ||
| 318 | #define BF_DIGCTL_DBGRD_COMPLEMENT(v) (((v) << 0) & 0xffffffff) | ||
| 319 | |||
| 320 | /** | ||
| 321 | * Register: HW_DIGCTL_DBG | ||
| 322 | * Address: 0xd0 | ||
| 323 | * SCT: no | ||
| 324 | */ | ||
| 325 | #define HW_DIGCTL_DBG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xd0)) | ||
| 326 | #define BP_DIGCTL_DBG_VALUE 0 | ||
| 327 | #define BM_DIGCTL_DBG_VALUE 0xffffffff | ||
| 328 | #define BF_DIGCTL_DBG_VALUE(v) (((v) << 0) & 0xffffffff) | ||
| 329 | |||
| 330 | /** | ||
| 331 | * Register: HW_DIGCTL_1TRAM_BIST_CSR | ||
| 332 | * Address: 0xe0 | ||
| 333 | * SCT: yes | ||
| 334 | */ | ||
| 335 | #define HW_DIGCTL_1TRAM_BIST_CSR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x0)) | ||
| 336 | #define HW_DIGCTL_1TRAM_BIST_CSR_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x4)) | ||
| 337 | #define HW_DIGCTL_1TRAM_BIST_CSR_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x8)) | ||
| 338 | #define HW_DIGCTL_1TRAM_BIST_CSR_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0xc)) | ||
| 339 | #define BP_DIGCTL_1TRAM_BIST_CSR_FAIL 3 | ||
| 340 | #define BM_DIGCTL_1TRAM_BIST_CSR_FAIL 0x8 | ||
| 341 | #define BF_DIGCTL_1TRAM_BIST_CSR_FAIL(v) (((v) << 3) & 0x8) | ||
| 342 | #define BP_DIGCTL_1TRAM_BIST_CSR_PASS 2 | ||
| 343 | #define BM_DIGCTL_1TRAM_BIST_CSR_PASS 0x4 | ||
| 344 | #define BF_DIGCTL_1TRAM_BIST_CSR_PASS(v) (((v) << 2) & 0x4) | ||
| 345 | #define BP_DIGCTL_1TRAM_BIST_CSR_DONE 1 | ||
| 346 | #define BM_DIGCTL_1TRAM_BIST_CSR_DONE 0x2 | ||
| 347 | #define BF_DIGCTL_1TRAM_BIST_CSR_DONE(v) (((v) << 1) & 0x2) | ||
| 348 | #define BP_DIGCTL_1TRAM_BIST_CSR_START 0 | ||
| 349 | #define BM_DIGCTL_1TRAM_BIST_CSR_START 0x1 | ||
| 350 | #define BF_DIGCTL_1TRAM_BIST_CSR_START(v) (((v) << 0) & 0x1) | ||
| 351 | |||
| 352 | /** | ||
| 353 | * Register: HW_DIGCTL_1TRAM_BIST_REPAIR0 | ||
| 354 | * Address: 0xf0 | ||
| 355 | * SCT: no | ||
| 356 | */ | ||
| 357 | #define HW_DIGCTL_1TRAM_BIST_REPAIR0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0)) | ||
| 358 | |||
| 359 | /** | ||
| 360 | * Register: HW_DIGCTL_1TRAM_BIST_REPAIR1 | ||
| 361 | * Address: 0x100 | ||
| 362 | * SCT: no | ||
| 363 | */ | ||
| 364 | #define HW_DIGCTL_1TRAM_BIST_REPAIR1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x100)) | ||
| 365 | |||
| 366 | /** | ||
| 367 | * Register: HW_DIGCTL_1TRAM_STATUS0 | ||
| 368 | * Address: 0x110 | ||
| 369 | * SCT: no | ||
| 370 | */ | ||
| 371 | #define HW_DIGCTL_1TRAM_STATUS0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110)) | ||
| 372 | #define BP_DIGCTL_1TRAM_STATUS0_FAILDATA00 0 | ||
| 373 | #define BM_DIGCTL_1TRAM_STATUS0_FAILDATA00 0xffffffff | ||
| 374 | #define BF_DIGCTL_1TRAM_STATUS0_FAILDATA00(v) (((v) << 0) & 0xffffffff) | ||
| 375 | |||
| 376 | /** | ||
| 377 | * Register: HW_DIGCTL_1TRAM_STATUS1 | ||
| 378 | * Address: 0x120 | ||
| 379 | * SCT: no | ||
| 380 | */ | ||
| 381 | #define HW_DIGCTL_1TRAM_STATUS1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120)) | ||
| 382 | #define BP_DIGCTL_1TRAM_STATUS1_FAILDATA01 0 | ||
| 383 | #define BM_DIGCTL_1TRAM_STATUS1_FAILDATA01 0xffffffff | ||
| 384 | #define BF_DIGCTL_1TRAM_STATUS1_FAILDATA01(v) (((v) << 0) & 0xffffffff) | ||
| 385 | |||
| 386 | /** | ||
| 387 | * Register: HW_DIGCTL_1TRAM_STATUS2 | ||
| 388 | * Address: 0x130 | ||
| 389 | * SCT: no | ||
| 390 | */ | ||
| 391 | #define HW_DIGCTL_1TRAM_STATUS2 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130)) | ||
| 392 | #define BP_DIGCTL_1TRAM_STATUS2_FAILDATA10 0 | ||
| 393 | #define BM_DIGCTL_1TRAM_STATUS2_FAILDATA10 0xffffffff | ||
| 394 | #define BF_DIGCTL_1TRAM_STATUS2_FAILDATA10(v) (((v) << 0) & 0xffffffff) | ||
| 395 | |||
| 396 | /** | ||
| 397 | * Register: HW_DIGCTL_1TRAM_STATUS3 | ||
| 398 | * Address: 0x140 | ||
| 399 | * SCT: no | ||
| 400 | */ | ||
| 401 | #define HW_DIGCTL_1TRAM_STATUS3 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140)) | ||
| 402 | #define BP_DIGCTL_1TRAM_STATUS3_FAILDATA11 0 | ||
| 403 | #define BM_DIGCTL_1TRAM_STATUS3_FAILDATA11 0xffffffff | ||
| 404 | #define BF_DIGCTL_1TRAM_STATUS3_FAILDATA11(v) (((v) << 0) & 0xffffffff) | ||
| 405 | |||
| 406 | /** | ||
| 407 | * Register: HW_DIGCTL_1TRAM_STATUS4 | ||
| 408 | * Address: 0x150 | ||
| 409 | * SCT: no | ||
| 410 | */ | ||
| 411 | #define HW_DIGCTL_1TRAM_STATUS4 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150)) | ||
| 412 | #define BP_DIGCTL_1TRAM_STATUS4_FAILDATA20 0 | ||
| 413 | #define BM_DIGCTL_1TRAM_STATUS4_FAILDATA20 0xffffffff | ||
| 414 | #define BF_DIGCTL_1TRAM_STATUS4_FAILDATA20(v) (((v) << 0) & 0xffffffff) | ||
| 415 | |||
| 416 | /** | ||
| 417 | * Register: HW_DIGCTL_1TRAM_STATUS5 | ||
| 418 | * Address: 0x160 | ||
| 419 | * SCT: no | ||
| 420 | */ | ||
| 421 | #define HW_DIGCTL_1TRAM_STATUS5 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160)) | ||
| 422 | #define BP_DIGCTL_1TRAM_STATUS5_FAILDATA21 0 | ||
| 423 | #define BM_DIGCTL_1TRAM_STATUS5_FAILDATA21 0xffffffff | ||
| 424 | #define BF_DIGCTL_1TRAM_STATUS5_FAILDATA21(v) (((v) << 0) & 0xffffffff) | ||
| 425 | |||
| 426 | /** | ||
| 427 | * Register: HW_DIGCTL_1TRAM_STATUS6 | ||
| 428 | * Address: 0x170 | ||
| 429 | * SCT: no | ||
| 430 | */ | ||
| 431 | #define HW_DIGCTL_1TRAM_STATUS6 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170)) | ||
| 432 | #define BP_DIGCTL_1TRAM_STATUS6_FAILDATA30 0 | ||
| 433 | #define BM_DIGCTL_1TRAM_STATUS6_FAILDATA30 0xffffffff | ||
| 434 | #define BF_DIGCTL_1TRAM_STATUS6_FAILDATA30(v) (((v) << 0) & 0xffffffff) | ||
| 435 | |||
| 436 | /** | ||
| 437 | * Register: HW_DIGCTL_1TRAM_STATUS7 | ||
| 438 | * Address: 0x180 | ||
| 439 | * SCT: no | ||
| 440 | */ | ||
| 441 | #define HW_DIGCTL_1TRAM_STATUS7 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180)) | ||
| 442 | #define BP_DIGCTL_1TRAM_STATUS7_FAILDATA31 0 | ||
| 443 | #define BM_DIGCTL_1TRAM_STATUS7_FAILDATA31 0xffffffff | ||
| 444 | #define BF_DIGCTL_1TRAM_STATUS7_FAILDATA31(v) (((v) << 0) & 0xffffffff) | ||
| 445 | |||
| 446 | /** | ||
| 447 | * Register: HW_DIGCTL_1TRAM_STATUS8 | ||
| 448 | * Address: 0x190 | ||
| 449 | * SCT: no | ||
| 450 | */ | ||
| 451 | #define HW_DIGCTL_1TRAM_STATUS8 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190)) | ||
| 452 | #define BP_DIGCTL_1TRAM_STATUS8_FAILADDR01 16 | ||
| 453 | #define BM_DIGCTL_1TRAM_STATUS8_FAILADDR01 0xffff0000 | ||
| 454 | #define BF_DIGCTL_1TRAM_STATUS8_FAILADDR01(v) (((v) << 16) & 0xffff0000) | ||
| 455 | #define BP_DIGCTL_1TRAM_STATUS8_FAILADDR00 0 | ||
| 456 | #define BM_DIGCTL_1TRAM_STATUS8_FAILADDR00 0xffff | ||
| 457 | #define BF_DIGCTL_1TRAM_STATUS8_FAILADDR00(v) (((v) << 0) & 0xffff) | ||
| 458 | |||
| 459 | /** | ||
| 460 | * Register: HW_DIGCTL_1TRAM_STATUS9 | ||
| 461 | * Address: 0x1a0 | ||
| 462 | * SCT: no | ||
| 463 | */ | ||
| 464 | #define HW_DIGCTL_1TRAM_STATUS9 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0)) | ||
| 465 | #define BP_DIGCTL_1TRAM_STATUS9_FAILADDR11 16 | ||
| 466 | #define BM_DIGCTL_1TRAM_STATUS9_FAILADDR11 0xffff0000 | ||
| 467 | #define BF_DIGCTL_1TRAM_STATUS9_FAILADDR11(v) (((v) << 16) & 0xffff0000) | ||
| 468 | #define BP_DIGCTL_1TRAM_STATUS9_FAILADDR10 0 | ||
| 469 | #define BM_DIGCTL_1TRAM_STATUS9_FAILADDR10 0xffff | ||
| 470 | #define BF_DIGCTL_1TRAM_STATUS9_FAILADDR10(v) (((v) << 0) & 0xffff) | ||
| 471 | |||
| 472 | /** | ||
| 473 | * Register: HW_DIGCTL_1TRAM_STATUS10 | ||
| 474 | * Address: 0x1b0 | ||
| 475 | * SCT: no | ||
| 476 | */ | ||
| 477 | #define HW_DIGCTL_1TRAM_STATUS10 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0)) | ||
| 478 | #define BP_DIGCTL_1TRAM_STATUS10_FAILADDR21 16 | ||
| 479 | #define BM_DIGCTL_1TRAM_STATUS10_FAILADDR21 0xffff0000 | ||
| 480 | #define BF_DIGCTL_1TRAM_STATUS10_FAILADDR21(v) (((v) << 16) & 0xffff0000) | ||
| 481 | #define BP_DIGCTL_1TRAM_STATUS10_FAILADDR20 0 | ||
| 482 | #define BM_DIGCTL_1TRAM_STATUS10_FAILADDR20 0xffff | ||
| 483 | #define BF_DIGCTL_1TRAM_STATUS10_FAILADDR20(v) (((v) << 0) & 0xffff) | ||
| 484 | |||
| 485 | /** | ||
| 486 | * Register: HW_DIGCTL_1TRAM_STATUS11 | ||
| 487 | * Address: 0x1c0 | ||
| 488 | * SCT: no | ||
| 489 | */ | ||
| 490 | #define HW_DIGCTL_1TRAM_STATUS11 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0)) | ||
| 491 | #define BP_DIGCTL_1TRAM_STATUS11_FAILADDR31 16 | ||
| 492 | #define BM_DIGCTL_1TRAM_STATUS11_FAILADDR31 0xffff0000 | ||
| 493 | #define BF_DIGCTL_1TRAM_STATUS11_FAILADDR31(v) (((v) << 16) & 0xffff0000) | ||
| 494 | #define BP_DIGCTL_1TRAM_STATUS11_FAILADDR30 0 | ||
| 495 | #define BM_DIGCTL_1TRAM_STATUS11_FAILADDR30 0xffff | ||
| 496 | #define BF_DIGCTL_1TRAM_STATUS11_FAILADDR30(v) (((v) << 0) & 0xffff) | ||
| 497 | |||
| 498 | /** | ||
| 499 | * Register: HW_DIGCTL_1TRAM_STATUS12 | ||
| 500 | * Address: 0x1d0 | ||
| 501 | * SCT: no | ||
| 502 | */ | ||
| 503 | #define HW_DIGCTL_1TRAM_STATUS12 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0)) | ||
| 504 | #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE11 24 | ||
| 505 | #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE11 0x1f000000 | ||
| 506 | #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE11(v) (((v) << 24) & 0x1f000000) | ||
| 507 | #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE10 16 | ||
| 508 | #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE10 0x1f0000 | ||
| 509 | #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE10(v) (((v) << 16) & 0x1f0000) | ||
| 510 | #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE01 8 | ||
| 511 | #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE01 0x1f00 | ||
| 512 | #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE01(v) (((v) << 8) & 0x1f00) | ||
| 513 | #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE00 0 | ||
| 514 | #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE00 0x1f | ||
| 515 | #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE00(v) (((v) << 0) & 0x1f) | ||
| 516 | |||
| 517 | /** | ||
| 518 | * Register: HW_DIGCTL_1TRAM_STATUS13 | ||
| 519 | * Address: 0x1e0 | ||
| 520 | * SCT: no | ||
| 521 | */ | ||
| 522 | #define HW_DIGCTL_1TRAM_STATUS13 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0)) | ||
| 523 | #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE31 24 | ||
| 524 | #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE31 0x1f000000 | ||
| 525 | #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE31(v) (((v) << 24) & 0x1f000000) | ||
| 526 | #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE30 16 | ||
| 527 | #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE30 0x1f0000 | ||
| 528 | #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE30(v) (((v) << 16) & 0x1f0000) | ||
| 529 | #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE21 8 | ||
| 530 | #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE21 0x1f00 | ||
| 531 | #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE21(v) (((v) << 8) & 0x1f00) | ||
| 532 | #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE20 0 | ||
| 533 | #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE20 0x1f | ||
| 534 | #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE20(v) (((v) << 0) & 0x1f) | ||
| 535 | |||
| 536 | /** | ||
| 537 | * Register: HW_DIGCTL_SCRATCH0 | ||
| 538 | * Address: 0x290 | ||
| 539 | * SCT: no | ||
| 540 | */ | ||
| 541 | #define HW_DIGCTL_SCRATCH0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x290)) | ||
| 542 | #define BP_DIGCTL_SCRATCH0_PTR 0 | ||
| 543 | #define BM_DIGCTL_SCRATCH0_PTR 0xffffffff | ||
| 544 | #define BF_DIGCTL_SCRATCH0_PTR(v) (((v) << 0) & 0xffffffff) | ||
| 545 | |||
| 546 | /** | ||
| 547 | * Register: HW_DIGCTL_SCRATCH1 | ||
| 548 | * Address: 0x2a0 | ||
| 549 | * SCT: no | ||
| 550 | */ | ||
| 551 | #define HW_DIGCTL_SCRATCH1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2a0)) | ||
| 552 | #define BP_DIGCTL_SCRATCH1_PTR 0 | ||
| 553 | #define BM_DIGCTL_SCRATCH1_PTR 0xffffffff | ||
| 554 | #define BF_DIGCTL_SCRATCH1_PTR(v) (((v) << 0) & 0xffffffff) | ||
| 555 | |||
| 556 | /** | ||
| 557 | * Register: HW_DIGCTL_ARMCACHE | ||
| 558 | * Address: 0x2b0 | ||
| 559 | * SCT: no | ||
| 560 | */ | ||
| 561 | #define HW_DIGCTL_ARMCACHE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2b0)) | ||
| 562 | #define BP_DIGCTL_ARMCACHE_CACHE_SS 8 | ||
| 563 | #define BM_DIGCTL_ARMCACHE_CACHE_SS 0x300 | ||
| 564 | #define BF_DIGCTL_ARMCACHE_CACHE_SS(v) (((v) << 8) & 0x300) | ||
| 565 | #define BP_DIGCTL_ARMCACHE_DTAG_SS 4 | ||
| 566 | #define BM_DIGCTL_ARMCACHE_DTAG_SS 0x30 | ||
| 567 | #define BF_DIGCTL_ARMCACHE_DTAG_SS(v) (((v) << 4) & 0x30) | ||
| 568 | #define BP_DIGCTL_ARMCACHE_ITAG_SS 0 | ||
| 569 | #define BM_DIGCTL_ARMCACHE_ITAG_SS 0x3 | ||
| 570 | #define BF_DIGCTL_ARMCACHE_ITAG_SS(v) (((v) << 0) & 0x3) | ||
| 571 | |||
| 572 | /** | ||
| 573 | * Register: HW_DIGCTL_SGTL | ||
| 574 | * Address: 0x300 | ||
| 575 | * SCT: no | ||
| 576 | */ | ||
| 577 | #define HW_DIGCTL_SGTL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x300)) | ||
| 578 | #define BP_DIGCTL_SGTL_COPYRIGHT 0 | ||
| 579 | #define BM_DIGCTL_SGTL_COPYRIGHT 0xffffffff | ||
| 580 | #define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) << 0) & 0xffffffff) | ||
| 581 | |||
| 582 | /** | ||
| 583 | * Register: HW_DIGCTL_CHIPID | ||
| 584 | * Address: 0x310 | ||
| 585 | * SCT: no | ||
| 586 | */ | ||
| 587 | #define HW_DIGCTL_CHIPID (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x310)) | ||
| 588 | #define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 | ||
| 589 | #define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xffff0000 | ||
| 590 | #define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) (((v) << 16) & 0xffff0000) | ||
| 591 | #define BP_DIGCTL_CHIPID_REVISION 0 | ||
| 592 | #define BM_DIGCTL_CHIPID_REVISION 0xff | ||
| 593 | #define BF_DIGCTL_CHIPID_REVISION(v) (((v) << 0) & 0xff) | ||
| 594 | |||
| 595 | #endif /* __HEADERGEN__STMP3600__DIGCTL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-dri.h b/firmware/target/arm/imx233/regs/stmp3600/regs-dri.h new file mode 100644 index 0000000000..2d2624a953 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-dri.h | |||
| @@ -0,0 +1,258 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__DRI__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__DRI__H__ | ||
| 25 | |||
| 26 | #define REGS_DRI_BASE (0x80074000) | ||
| 27 | |||
| 28 | #define REGS_DRI_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_DRI_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_DRI_CTRL (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_DRI_CTRL_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_DRI_CTRL_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_DRI_CTRL_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_DRI_CTRL_SFTRST 31 | ||
| 40 | #define BM_DRI_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BV_DRI_CTRL_SFTRST__RUN 0x0 | ||
| 42 | #define BV_DRI_CTRL_SFTRST__RESET 0x1 | ||
| 43 | #define BF_DRI_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 44 | #define BF_DRI_CTRL_SFTRST_V(v) ((BV_DRI_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
| 45 | #define BP_DRI_CTRL_CLKGATE 30 | ||
| 46 | #define BM_DRI_CTRL_CLKGATE 0x40000000 | ||
| 47 | #define BV_DRI_CTRL_CLKGATE__RUN 0x0 | ||
| 48 | #define BV_DRI_CTRL_CLKGATE__NO_CLKS 0x1 | ||
| 49 | #define BF_DRI_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 50 | #define BF_DRI_CTRL_CLKGATE_V(v) ((BV_DRI_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
| 51 | #define BP_DRI_CTRL_ENABLE_INPUTS 29 | ||
| 52 | #define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000 | ||
| 53 | #define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN 0x0 | ||
| 54 | #define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN 0x1 | ||
| 55 | #define BF_DRI_CTRL_ENABLE_INPUTS(v) (((v) << 29) & 0x20000000) | ||
| 56 | #define BF_DRI_CTRL_ENABLE_INPUTS_V(v) ((BV_DRI_CTRL_ENABLE_INPUTS__##v << 29) & 0x20000000) | ||
| 57 | #define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR 26 | ||
| 58 | #define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x4000000 | ||
| 59 | #define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE 0x0 | ||
| 60 | #define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP 0x1 | ||
| 61 | #define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v) (((v) << 26) & 0x4000000) | ||
| 62 | #define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##v << 26) & 0x4000000) | ||
| 63 | #define BP_DRI_CTRL_STOP_ON_PILOT_ERROR 25 | ||
| 64 | #define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x2000000 | ||
| 65 | #define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE 0x0 | ||
| 66 | #define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP 0x1 | ||
| 67 | #define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v) (((v) << 25) & 0x2000000) | ||
| 68 | #define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##v << 25) & 0x2000000) | ||
| 69 | #define BP_DRI_CTRL_DMA_DELAY_COUNT 16 | ||
| 70 | #define BM_DRI_CTRL_DMA_DELAY_COUNT 0x1f0000 | ||
| 71 | #define BF_DRI_CTRL_DMA_DELAY_COUNT(v) (((v) << 16) & 0x1f0000) | ||
| 72 | #define BP_DRI_CTRL_REACQUIRE_PHASE 15 | ||
| 73 | #define BM_DRI_CTRL_REACQUIRE_PHASE 0x8000 | ||
| 74 | #define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL 0x0 | ||
| 75 | #define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE 0x1 | ||
| 76 | #define BF_DRI_CTRL_REACQUIRE_PHASE(v) (((v) << 15) & 0x8000) | ||
| 77 | #define BF_DRI_CTRL_REACQUIRE_PHASE_V(v) ((BV_DRI_CTRL_REACQUIRE_PHASE__##v << 15) & 0x8000) | ||
| 78 | #define BP_DRI_CTRL_OVERFLOW_IRQ_EN 11 | ||
| 79 | #define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x800 | ||
| 80 | #define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED 0x0 | ||
| 81 | #define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED 0x1 | ||
| 82 | #define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v) (((v) << 11) & 0x800) | ||
| 83 | #define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ_EN__##v << 11) & 0x800) | ||
| 84 | #define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 10 | ||
| 85 | #define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x400 | ||
| 86 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED 0x0 | ||
| 87 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED 0x1 | ||
| 88 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v) (((v) << 10) & 0x400) | ||
| 89 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##v << 10) & 0x400) | ||
| 90 | #define BP_DRI_CTRL_ATTENTION_IRQ_EN 9 | ||
| 91 | #define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x200 | ||
| 92 | #define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED 0x0 | ||
| 93 | #define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED 0x1 | ||
| 94 | #define BF_DRI_CTRL_ATTENTION_IRQ_EN(v) (((v) << 9) & 0x200) | ||
| 95 | #define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ_EN__##v << 9) & 0x200) | ||
| 96 | #define BP_DRI_CTRL_OVERFLOW_IRQ 3 | ||
| 97 | #define BM_DRI_CTRL_OVERFLOW_IRQ 0x8 | ||
| 98 | #define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST 0x0 | ||
| 99 | #define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST 0x1 | ||
| 100 | #define BF_DRI_CTRL_OVERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
| 101 | #define BF_DRI_CTRL_OVERFLOW_IRQ_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ__##v << 3) & 0x8) | ||
| 102 | #define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 2 | ||
| 103 | #define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x4 | ||
| 104 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST 0x0 | ||
| 105 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST 0x1 | ||
| 106 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v) (((v) << 2) & 0x4) | ||
| 107 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##v << 2) & 0x4) | ||
| 108 | #define BP_DRI_CTRL_ATTENTION_IRQ 1 | ||
| 109 | #define BM_DRI_CTRL_ATTENTION_IRQ 0x2 | ||
| 110 | #define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST 0x0 | ||
| 111 | #define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST 0x1 | ||
| 112 | #define BF_DRI_CTRL_ATTENTION_IRQ(v) (((v) << 1) & 0x2) | ||
| 113 | #define BF_DRI_CTRL_ATTENTION_IRQ_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ__##v << 1) & 0x2) | ||
| 114 | #define BP_DRI_CTRL_RUN 0 | ||
| 115 | #define BM_DRI_CTRL_RUN 0x1 | ||
| 116 | #define BV_DRI_CTRL_RUN__HALT 0x0 | ||
| 117 | #define BV_DRI_CTRL_RUN__RUN 0x1 | ||
| 118 | #define BF_DRI_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
| 119 | #define BF_DRI_CTRL_RUN_V(v) ((BV_DRI_CTRL_RUN__##v << 0) & 0x1) | ||
| 120 | |||
| 121 | /** | ||
| 122 | * Register: HW_DRI_TIMING | ||
| 123 | * Address: 0x10 | ||
| 124 | * SCT: no | ||
| 125 | */ | ||
| 126 | #define HW_DRI_TIMING (*(volatile unsigned long *)(REGS_DRI_BASE + 0x10)) | ||
| 127 | #define BP_DRI_TIMING_PILOT_REP_RATE 16 | ||
| 128 | #define BM_DRI_TIMING_PILOT_REP_RATE 0xf0000 | ||
| 129 | #define BF_DRI_TIMING_PILOT_REP_RATE(v) (((v) << 16) & 0xf0000) | ||
| 130 | #define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0 | ||
| 131 | #define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0xff | ||
| 132 | #define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v) (((v) << 0) & 0xff) | ||
| 133 | |||
| 134 | /** | ||
| 135 | * Register: HW_DRI_STAT | ||
| 136 | * Address: 0x20 | ||
| 137 | * SCT: no | ||
| 138 | */ | ||
| 139 | #define HW_DRI_STAT (*(volatile unsigned long *)(REGS_DRI_BASE + 0x20)) | ||
| 140 | #define BP_DRI_STAT_DRI_PRESENT 31 | ||
| 141 | #define BM_DRI_STAT_DRI_PRESENT 0x80000000 | ||
| 142 | #define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE 0x0 | ||
| 143 | #define BV_DRI_STAT_DRI_PRESENT__AVAILABLE 0x1 | ||
| 144 | #define BF_DRI_STAT_DRI_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 145 | #define BF_DRI_STAT_DRI_PRESENT_V(v) ((BV_DRI_STAT_DRI_PRESENT__##v << 31) & 0x80000000) | ||
| 146 | #define BP_DRI_STAT_PILOT_PHASE 16 | ||
| 147 | #define BM_DRI_STAT_PILOT_PHASE 0xf0000 | ||
| 148 | #define BF_DRI_STAT_PILOT_PHASE(v) (((v) << 16) & 0xf0000) | ||
| 149 | #define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY 3 | ||
| 150 | #define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY 0x8 | ||
| 151 | #define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 152 | #define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST 0x1 | ||
| 153 | #define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v) (((v) << 3) & 0x8) | ||
| 154 | #define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##v << 3) & 0x8) | ||
| 155 | #define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 2 | ||
| 156 | #define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 0x4 | ||
| 157 | #define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 158 | #define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST 0x1 | ||
| 159 | #define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v) (((v) << 2) & 0x4) | ||
| 160 | #define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##v << 2) & 0x4) | ||
| 161 | #define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY 1 | ||
| 162 | #define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY 0x2 | ||
| 163 | #define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 164 | #define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST 0x1 | ||
| 165 | #define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v) (((v) << 1) & 0x2) | ||
| 166 | #define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##v << 1) & 0x2) | ||
| 167 | |||
| 168 | /** | ||
| 169 | * Register: HW_DRI_DATA | ||
| 170 | * Address: 0x30 | ||
| 171 | * SCT: no | ||
| 172 | */ | ||
| 173 | #define HW_DRI_DATA (*(volatile unsigned long *)(REGS_DRI_BASE + 0x30)) | ||
| 174 | #define BP_DRI_DATA_DATA 0 | ||
| 175 | #define BM_DRI_DATA_DATA 0xffffffff | ||
| 176 | #define BF_DRI_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 177 | |||
| 178 | /** | ||
| 179 | * Register: HW_DRI_DEBUG0 | ||
| 180 | * Address: 0x40 | ||
| 181 | * SCT: yes | ||
| 182 | */ | ||
| 183 | #define HW_DRI_DEBUG0 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x0)) | ||
| 184 | #define HW_DRI_DEBUG0_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x4)) | ||
| 185 | #define HW_DRI_DEBUG0_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x8)) | ||
| 186 | #define HW_DRI_DEBUG0_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0xc)) | ||
| 187 | #define BP_DRI_DEBUG0_DMAREQ 31 | ||
| 188 | #define BM_DRI_DEBUG0_DMAREQ 0x80000000 | ||
| 189 | #define BF_DRI_DEBUG0_DMAREQ(v) (((v) << 31) & 0x80000000) | ||
| 190 | #define BP_DRI_DEBUG0_DMACMDKICK 30 | ||
| 191 | #define BM_DRI_DEBUG0_DMACMDKICK 0x40000000 | ||
| 192 | #define BF_DRI_DEBUG0_DMACMDKICK(v) (((v) << 30) & 0x40000000) | ||
| 193 | #define BP_DRI_DEBUG0_DRI_CLK_INPUT 29 | ||
| 194 | #define BM_DRI_DEBUG0_DRI_CLK_INPUT 0x20000000 | ||
| 195 | #define BF_DRI_DEBUG0_DRI_CLK_INPUT(v) (((v) << 29) & 0x20000000) | ||
| 196 | #define BP_DRI_DEBUG0_DRI_DATA_INPUT 28 | ||
| 197 | #define BM_DRI_DEBUG0_DRI_DATA_INPUT 0x10000000 | ||
| 198 | #define BF_DRI_DEBUG0_DRI_DATA_INPUT(v) (((v) << 28) & 0x10000000) | ||
| 199 | #define BP_DRI_DEBUG0_TEST_MODE 27 | ||
| 200 | #define BM_DRI_DEBUG0_TEST_MODE 0x8000000 | ||
| 201 | #define BF_DRI_DEBUG0_TEST_MODE(v) (((v) << 27) & 0x8000000) | ||
| 202 | #define BP_DRI_DEBUG0_PILOT_REP_RATE 26 | ||
| 203 | #define BM_DRI_DEBUG0_PILOT_REP_RATE 0x4000000 | ||
| 204 | #define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ 0x0 | ||
| 205 | #define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ 0x1 | ||
| 206 | #define BF_DRI_DEBUG0_PILOT_REP_RATE(v) (((v) << 26) & 0x4000000) | ||
| 207 | #define BF_DRI_DEBUG0_PILOT_REP_RATE_V(v) ((BV_DRI_DEBUG0_PILOT_REP_RATE__##v << 26) & 0x4000000) | ||
| 208 | #define BP_DRI_DEBUG0_SPARE 18 | ||
| 209 | #define BM_DRI_DEBUG0_SPARE 0x3fc0000 | ||
| 210 | #define BF_DRI_DEBUG0_SPARE(v) (((v) << 18) & 0x3fc0000) | ||
| 211 | #define BP_DRI_DEBUG0_FRAME 0 | ||
| 212 | #define BM_DRI_DEBUG0_FRAME 0x3ffff | ||
| 213 | #define BF_DRI_DEBUG0_FRAME(v) (((v) << 0) & 0x3ffff) | ||
| 214 | |||
| 215 | /** | ||
| 216 | * Register: HW_DRI_DEBUG1 | ||
| 217 | * Address: 0x50 | ||
| 218 | * SCT: yes | ||
| 219 | */ | ||
| 220 | #define HW_DRI_DEBUG1 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x0)) | ||
| 221 | #define HW_DRI_DEBUG1_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x4)) | ||
| 222 | #define HW_DRI_DEBUG1_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x8)) | ||
| 223 | #define HW_DRI_DEBUG1_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0xc)) | ||
| 224 | #define BP_DRI_DEBUG1_INVERT_PILOT 31 | ||
| 225 | #define BM_DRI_DEBUG1_INVERT_PILOT 0x80000000 | ||
| 226 | #define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL 0x0 | ||
| 227 | #define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED 0x1 | ||
| 228 | #define BF_DRI_DEBUG1_INVERT_PILOT(v) (((v) << 31) & 0x80000000) | ||
| 229 | #define BF_DRI_DEBUG1_INVERT_PILOT_V(v) ((BV_DRI_DEBUG1_INVERT_PILOT__##v << 31) & 0x80000000) | ||
| 230 | #define BP_DRI_DEBUG1_INVERT_ATTENTION 30 | ||
| 231 | #define BM_DRI_DEBUG1_INVERT_ATTENTION 0x40000000 | ||
| 232 | #define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL 0x0 | ||
| 233 | #define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED 0x1 | ||
| 234 | #define BF_DRI_DEBUG1_INVERT_ATTENTION(v) (((v) << 30) & 0x40000000) | ||
| 235 | #define BF_DRI_DEBUG1_INVERT_ATTENTION_V(v) ((BV_DRI_DEBUG1_INVERT_ATTENTION__##v << 30) & 0x40000000) | ||
| 236 | #define BP_DRI_DEBUG1_INVERT_DRI_DATA 29 | ||
| 237 | #define BM_DRI_DEBUG1_INVERT_DRI_DATA 0x20000000 | ||
| 238 | #define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL 0x0 | ||
| 239 | #define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED 0x1 | ||
| 240 | #define BF_DRI_DEBUG1_INVERT_DRI_DATA(v) (((v) << 29) & 0x20000000) | ||
| 241 | #define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_DATA__##v << 29) & 0x20000000) | ||
| 242 | #define BP_DRI_DEBUG1_INVERT_DRI_CLOCK 28 | ||
| 243 | #define BM_DRI_DEBUG1_INVERT_DRI_CLOCK 0x10000000 | ||
| 244 | #define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL 0x0 | ||
| 245 | #define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED 0x1 | ||
| 246 | #define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v) (((v) << 28) & 0x10000000) | ||
| 247 | #define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##v << 28) & 0x10000000) | ||
| 248 | #define BP_DRI_DEBUG1_REVERSE_FRAME 27 | ||
| 249 | #define BM_DRI_DEBUG1_REVERSE_FRAME 0x8000000 | ||
| 250 | #define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL 0x0 | ||
| 251 | #define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED 0x1 | ||
| 252 | #define BF_DRI_DEBUG1_REVERSE_FRAME(v) (((v) << 27) & 0x8000000) | ||
| 253 | #define BF_DRI_DEBUG1_REVERSE_FRAME_V(v) ((BV_DRI_DEBUG1_REVERSE_FRAME__##v << 27) & 0x8000000) | ||
| 254 | #define BP_DRI_DEBUG1_SWIZZLED_FRAME 0 | ||
| 255 | #define BM_DRI_DEBUG1_SWIZZLED_FRAME 0x3ffff | ||
| 256 | #define BF_DRI_DEBUG1_SWIZZLED_FRAME(v) (((v) << 0) & 0x3ffff) | ||
| 257 | |||
| 258 | #endif /* __HEADERGEN__STMP3600__DRI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-emictrl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-emictrl.h new file mode 100644 index 0000000000..88a94f977b --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-emictrl.h | |||
| @@ -0,0 +1,30 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__EMICTRL__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__EMICTRL__H__ | ||
| 25 | |||
| 26 | #define REGS_EMICTRL_BASE (0x80020000) | ||
| 27 | |||
| 28 | #define REGS_EMICTRL_VERSION "2.3.0" | ||
| 29 | |||
| 30 | #endif /* __HEADERGEN__STMP3600__EMICTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h b/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h new file mode 100644 index 0000000000..bdf52c9308 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h | |||
| @@ -0,0 +1,372 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__GPMI__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__GPMI__H__ | ||
| 25 | |||
| 26 | #define REGS_GPMI_BASE (0x8000c000) | ||
| 27 | |||
| 28 | #define REGS_GPMI_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_GPMI_CTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_GPMI_CTRL0 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_GPMI_CTRL0_SET (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_GPMI_CTRL0_CLR (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_GPMI_CTRL0_TOG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_GPMI_CTRL0_SFTRST 31 | ||
| 40 | #define BM_GPMI_CTRL0_SFTRST 0x80000000 | ||
| 41 | #define BV_GPMI_CTRL0_SFTRST__RUN 0x0 | ||
| 42 | #define BV_GPMI_CTRL0_SFTRST__RESET 0x1 | ||
| 43 | #define BF_GPMI_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 44 | #define BF_GPMI_CTRL0_SFTRST_V(v) ((BV_GPMI_CTRL0_SFTRST__##v << 31) & 0x80000000) | ||
| 45 | #define BP_GPMI_CTRL0_CLKGATE 30 | ||
| 46 | #define BM_GPMI_CTRL0_CLKGATE 0x40000000 | ||
| 47 | #define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 | ||
| 48 | #define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 | ||
| 49 | #define BF_GPMI_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 50 | #define BF_GPMI_CTRL0_CLKGATE_V(v) ((BV_GPMI_CTRL0_CLKGATE__##v << 30) & 0x40000000) | ||
| 51 | #define BP_GPMI_CTRL0_RUN 29 | ||
| 52 | #define BM_GPMI_CTRL0_RUN 0x20000000 | ||
| 53 | #define BV_GPMI_CTRL0_RUN__IDLE 0x0 | ||
| 54 | #define BV_GPMI_CTRL0_RUN__BUSY 0x1 | ||
| 55 | #define BF_GPMI_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
| 56 | #define BF_GPMI_CTRL0_RUN_V(v) ((BV_GPMI_CTRL0_RUN__##v << 29) & 0x20000000) | ||
| 57 | #define BP_GPMI_CTRL0_DEV_IRQ_EN 28 | ||
| 58 | #define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000 | ||
| 59 | #define BF_GPMI_CTRL0_DEV_IRQ_EN(v) (((v) << 28) & 0x10000000) | ||
| 60 | #define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN 27 | ||
| 61 | #define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x8000000 | ||
| 62 | #define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v) (((v) << 27) & 0x8000000) | ||
| 63 | #define BP_GPMI_CTRL0_UDMA 26 | ||
| 64 | #define BM_GPMI_CTRL0_UDMA 0x4000000 | ||
| 65 | #define BV_GPMI_CTRL0_UDMA__DISABLED 0x0 | ||
| 66 | #define BV_GPMI_CTRL0_UDMA__ENABLED 0x1 | ||
| 67 | #define BF_GPMI_CTRL0_UDMA(v) (((v) << 26) & 0x4000000) | ||
| 68 | #define BF_GPMI_CTRL0_UDMA_V(v) ((BV_GPMI_CTRL0_UDMA__##v << 26) & 0x4000000) | ||
| 69 | #define BP_GPMI_CTRL0_COMMAND_MODE 24 | ||
| 70 | #define BM_GPMI_CTRL0_COMMAND_MODE 0x3000000 | ||
| 71 | #define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 | ||
| 72 | #define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 | ||
| 73 | #define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 | ||
| 74 | #define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 | ||
| 75 | #define BF_GPMI_CTRL0_COMMAND_MODE(v) (((v) << 24) & 0x3000000) | ||
| 76 | #define BF_GPMI_CTRL0_COMMAND_MODE_V(v) ((BV_GPMI_CTRL0_COMMAND_MODE__##v << 24) & 0x3000000) | ||
| 77 | #define BP_GPMI_CTRL0_WORD_LENGTH 23 | ||
| 78 | #define BM_GPMI_CTRL0_WORD_LENGTH 0x800000 | ||
| 79 | #define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 | ||
| 80 | #define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 | ||
| 81 | #define BF_GPMI_CTRL0_WORD_LENGTH(v) (((v) << 23) & 0x800000) | ||
| 82 | #define BF_GPMI_CTRL0_WORD_LENGTH_V(v) ((BV_GPMI_CTRL0_WORD_LENGTH__##v << 23) & 0x800000) | ||
| 83 | #define BP_GPMI_CTRL0_LOCK_CS 22 | ||
| 84 | #define BM_GPMI_CTRL0_LOCK_CS 0x400000 | ||
| 85 | #define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0 | ||
| 86 | #define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1 | ||
| 87 | #define BF_GPMI_CTRL0_LOCK_CS(v) (((v) << 22) & 0x400000) | ||
| 88 | #define BF_GPMI_CTRL0_LOCK_CS_V(v) ((BV_GPMI_CTRL0_LOCK_CS__##v << 22) & 0x400000) | ||
| 89 | #define BP_GPMI_CTRL0_CS 20 | ||
| 90 | #define BM_GPMI_CTRL0_CS 0x300000 | ||
| 91 | #define BF_GPMI_CTRL0_CS(v) (((v) << 20) & 0x300000) | ||
| 92 | #define BP_GPMI_CTRL0_ADDRESS 17 | ||
| 93 | #define BM_GPMI_CTRL0_ADDRESS 0xe0000 | ||
| 94 | #define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 | ||
| 95 | #define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 | ||
| 96 | #define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 | ||
| 97 | #define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & 0xe0000) | ||
| 98 | #define BF_GPMI_CTRL0_ADDRESS_V(v) ((BV_GPMI_CTRL0_ADDRESS__##v << 17) & 0xe0000) | ||
| 99 | #define BP_GPMI_CTRL0_ADDRESS_INCREMENT 16 | ||
| 100 | #define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x10000 | ||
| 101 | #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 | ||
| 102 | #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 | ||
| 103 | #define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v) (((v) << 16) & 0x10000) | ||
| 104 | #define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(v) ((BV_GPMI_CTRL0_ADDRESS_INCREMENT__##v << 16) & 0x10000) | ||
| 105 | #define BP_GPMI_CTRL0_XFER_COUNT 0 | ||
| 106 | #define BM_GPMI_CTRL0_XFER_COUNT 0xffff | ||
| 107 | #define BF_GPMI_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
| 108 | |||
| 109 | /** | ||
| 110 | * Register: HW_GPMI_COMPARE | ||
| 111 | * Address: 0x10 | ||
| 112 | * SCT: no | ||
| 113 | */ | ||
| 114 | #define HW_GPMI_COMPARE (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x10)) | ||
| 115 | #define BP_GPMI_COMPARE_MASK 16 | ||
| 116 | #define BM_GPMI_COMPARE_MASK 0xffff0000 | ||
| 117 | #define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & 0xffff0000) | ||
| 118 | #define BP_GPMI_COMPARE_REFERENCE 0 | ||
| 119 | #define BM_GPMI_COMPARE_REFERENCE 0xffff | ||
| 120 | #define BF_GPMI_COMPARE_REFERENCE(v) (((v) << 0) & 0xffff) | ||
| 121 | |||
| 122 | /** | ||
| 123 | * Register: HW_GPMI_CTRL1 | ||
| 124 | * Address: 0x20 | ||
| 125 | * SCT: yes | ||
| 126 | */ | ||
| 127 | #define HW_GPMI_CTRL1 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x0)) | ||
| 128 | #define HW_GPMI_CTRL1_SET (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x4)) | ||
| 129 | #define HW_GPMI_CTRL1_CLR (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x8)) | ||
| 130 | #define HW_GPMI_CTRL1_TOG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0xc)) | ||
| 131 | #define BP_GPMI_CTRL1_DSAMPLE_TIME 12 | ||
| 132 | #define BM_GPMI_CTRL1_DSAMPLE_TIME 0x3000 | ||
| 133 | #define BF_GPMI_CTRL1_DSAMPLE_TIME(v) (((v) << 12) & 0x3000) | ||
| 134 | #define BP_GPMI_CTRL1_DEV_IRQ 10 | ||
| 135 | #define BM_GPMI_CTRL1_DEV_IRQ 0x400 | ||
| 136 | #define BF_GPMI_CTRL1_DEV_IRQ(v) (((v) << 10) & 0x400) | ||
| 137 | #define BP_GPMI_CTRL1_TIMEOUT_IRQ 9 | ||
| 138 | #define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x200 | ||
| 139 | #define BF_GPMI_CTRL1_TIMEOUT_IRQ(v) (((v) << 9) & 0x200) | ||
| 140 | #define BP_GPMI_CTRL1_BURST_EN 8 | ||
| 141 | #define BM_GPMI_CTRL1_BURST_EN 0x100 | ||
| 142 | #define BF_GPMI_CTRL1_BURST_EN(v) (((v) << 8) & 0x100) | ||
| 143 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 7 | ||
| 144 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 0x80 | ||
| 145 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v) (((v) << 7) & 0x80) | ||
| 146 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 6 | ||
| 147 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 0x40 | ||
| 148 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v) (((v) << 6) & 0x40) | ||
| 149 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 5 | ||
| 150 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 0x20 | ||
| 151 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v) (((v) << 5) & 0x20) | ||
| 152 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 4 | ||
| 153 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 0x10 | ||
| 154 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v) (((v) << 4) & 0x10) | ||
| 155 | #define BP_GPMI_CTRL1_DEV_RESET 3 | ||
| 156 | #define BM_GPMI_CTRL1_DEV_RESET 0x8 | ||
| 157 | #define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 | ||
| 158 | #define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 | ||
| 159 | #define BF_GPMI_CTRL1_DEV_RESET(v) (((v) << 3) & 0x8) | ||
| 160 | #define BF_GPMI_CTRL1_DEV_RESET_V(v) ((BV_GPMI_CTRL1_DEV_RESET__##v << 3) & 0x8) | ||
| 161 | #define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY 2 | ||
| 162 | #define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x4 | ||
| 163 | #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 | ||
| 164 | #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 | ||
| 165 | #define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v) (((v) << 2) & 0x4) | ||
| 166 | #define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v) ((BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##v << 2) & 0x4) | ||
| 167 | #define BP_GPMI_CTRL1_CAMERA_MODE 1 | ||
| 168 | #define BM_GPMI_CTRL1_CAMERA_MODE 0x2 | ||
| 169 | #define BF_GPMI_CTRL1_CAMERA_MODE(v) (((v) << 1) & 0x2) | ||
| 170 | #define BP_GPMI_CTRL1_GPMI_MODE 0 | ||
| 171 | #define BM_GPMI_CTRL1_GPMI_MODE 0x1 | ||
| 172 | #define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 | ||
| 173 | #define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 | ||
| 174 | #define BF_GPMI_CTRL1_GPMI_MODE(v) (((v) << 0) & 0x1) | ||
| 175 | #define BF_GPMI_CTRL1_GPMI_MODE_V(v) ((BV_GPMI_CTRL1_GPMI_MODE__##v << 0) & 0x1) | ||
| 176 | |||
| 177 | /** | ||
| 178 | * Register: HW_GPMI_TIMING0 | ||
| 179 | * Address: 0x30 | ||
| 180 | * SCT: no | ||
| 181 | */ | ||
| 182 | #define HW_GPMI_TIMING0 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x30)) | ||
| 183 | #define BP_GPMI_TIMING0_ADDRESS_SETUP 16 | ||
| 184 | #define BM_GPMI_TIMING0_ADDRESS_SETUP 0xff0000 | ||
| 185 | #define BF_GPMI_TIMING0_ADDRESS_SETUP(v) (((v) << 16) & 0xff0000) | ||
| 186 | #define BP_GPMI_TIMING0_DATA_HOLD 8 | ||
| 187 | #define BM_GPMI_TIMING0_DATA_HOLD 0xff00 | ||
| 188 | #define BF_GPMI_TIMING0_DATA_HOLD(v) (((v) << 8) & 0xff00) | ||
| 189 | #define BP_GPMI_TIMING0_DATA_SETUP 0 | ||
| 190 | #define BM_GPMI_TIMING0_DATA_SETUP 0xff | ||
| 191 | #define BF_GPMI_TIMING0_DATA_SETUP(v) (((v) << 0) & 0xff) | ||
| 192 | |||
| 193 | /** | ||
| 194 | * Register: HW_GPMI_TIMING1 | ||
| 195 | * Address: 0x40 | ||
| 196 | * SCT: no | ||
| 197 | */ | ||
| 198 | #define HW_GPMI_TIMING1 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x40)) | ||
| 199 | #define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 | ||
| 200 | #define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xffff0000 | ||
| 201 | #define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) (((v) << 16) & 0xffff0000) | ||
| 202 | #define BP_GPMI_TIMING1_ATA_READY_TIMEOUT 0 | ||
| 203 | #define BM_GPMI_TIMING1_ATA_READY_TIMEOUT 0xffff | ||
| 204 | #define BF_GPMI_TIMING1_ATA_READY_TIMEOUT(v) (((v) << 0) & 0xffff) | ||
| 205 | |||
| 206 | /** | ||
| 207 | * Register: HW_GPMI_TIMING2 | ||
| 208 | * Address: 0x50 | ||
| 209 | * SCT: no | ||
| 210 | */ | ||
| 211 | #define HW_GPMI_TIMING2 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x50)) | ||
| 212 | #define BP_GPMI_TIMING2_UDMA_TRP 24 | ||
| 213 | #define BM_GPMI_TIMING2_UDMA_TRP 0xff000000 | ||
| 214 | #define BF_GPMI_TIMING2_UDMA_TRP(v) (((v) << 24) & 0xff000000) | ||
| 215 | #define BP_GPMI_TIMING2_UDMA_ENV 16 | ||
| 216 | #define BM_GPMI_TIMING2_UDMA_ENV 0xff0000 | ||
| 217 | #define BF_GPMI_TIMING2_UDMA_ENV(v) (((v) << 16) & 0xff0000) | ||
| 218 | #define BP_GPMI_TIMING2_UDMA_HOLD 8 | ||
| 219 | #define BM_GPMI_TIMING2_UDMA_HOLD 0xff00 | ||
| 220 | #define BF_GPMI_TIMING2_UDMA_HOLD(v) (((v) << 8) & 0xff00) | ||
| 221 | #define BP_GPMI_TIMING2_UDMA_SETUP 0 | ||
| 222 | #define BM_GPMI_TIMING2_UDMA_SETUP 0xff | ||
| 223 | #define BF_GPMI_TIMING2_UDMA_SETUP(v) (((v) << 0) & 0xff) | ||
| 224 | |||
| 225 | /** | ||
| 226 | * Register: HW_GPMI_DATA | ||
| 227 | * Address: 0x60 | ||
| 228 | * SCT: no | ||
| 229 | */ | ||
| 230 | #define HW_GPMI_DATA (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60)) | ||
| 231 | #define BP_GPMI_DATA_DATA 0 | ||
| 232 | #define BM_GPMI_DATA_DATA 0xffffffff | ||
| 233 | #define BF_GPMI_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 234 | |||
| 235 | /** | ||
| 236 | * Register: HW_GPMI_STAT | ||
| 237 | * Address: 0x70 | ||
| 238 | * SCT: no | ||
| 239 | */ | ||
| 240 | #define HW_GPMI_STAT (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x70)) | ||
| 241 | #define BP_GPMI_STAT_PRESENT 31 | ||
| 242 | #define BM_GPMI_STAT_PRESENT 0x80000000 | ||
| 243 | #define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0 | ||
| 244 | #define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1 | ||
| 245 | #define BF_GPMI_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 246 | #define BF_GPMI_STAT_PRESENT_V(v) ((BV_GPMI_STAT_PRESENT__##v << 31) & 0x80000000) | ||
| 247 | #define BP_GPMI_STAT_RDY_TIMEOUT 8 | ||
| 248 | #define BM_GPMI_STAT_RDY_TIMEOUT 0xf00 | ||
| 249 | #define BF_GPMI_STAT_RDY_TIMEOUT(v) (((v) << 8) & 0xf00) | ||
| 250 | #define BP_GPMI_STAT_ATA_IRQ 7 | ||
| 251 | #define BM_GPMI_STAT_ATA_IRQ 0x80 | ||
| 252 | #define BF_GPMI_STAT_ATA_IRQ(v) (((v) << 7) & 0x80) | ||
| 253 | #define BP_GPMI_STAT_FIFO_EMPTY 5 | ||
| 254 | #define BM_GPMI_STAT_FIFO_EMPTY 0x20 | ||
| 255 | #define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0 | ||
| 256 | #define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1 | ||
| 257 | #define BF_GPMI_STAT_FIFO_EMPTY(v) (((v) << 5) & 0x20) | ||
| 258 | #define BF_GPMI_STAT_FIFO_EMPTY_V(v) ((BV_GPMI_STAT_FIFO_EMPTY__##v << 5) & 0x20) | ||
| 259 | #define BP_GPMI_STAT_FIFO_FULL 4 | ||
| 260 | #define BM_GPMI_STAT_FIFO_FULL 0x10 | ||
| 261 | #define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0 | ||
| 262 | #define BV_GPMI_STAT_FIFO_FULL__FULL 0x1 | ||
| 263 | #define BF_GPMI_STAT_FIFO_FULL(v) (((v) << 4) & 0x10) | ||
| 264 | #define BF_GPMI_STAT_FIFO_FULL_V(v) ((BV_GPMI_STAT_FIFO_FULL__##v << 4) & 0x10) | ||
| 265 | #define BP_GPMI_STAT_DEV3_ERROR 3 | ||
| 266 | #define BM_GPMI_STAT_DEV3_ERROR 0x8 | ||
| 267 | #define BF_GPMI_STAT_DEV3_ERROR(v) (((v) << 3) & 0x8) | ||
| 268 | #define BP_GPMI_STAT_DEV2_ERROR 2 | ||
| 269 | #define BM_GPMI_STAT_DEV2_ERROR 0x4 | ||
| 270 | #define BF_GPMI_STAT_DEV2_ERROR(v) (((v) << 2) & 0x4) | ||
| 271 | #define BP_GPMI_STAT_DEV1_ERROR 1 | ||
| 272 | #define BM_GPMI_STAT_DEV1_ERROR 0x2 | ||
| 273 | #define BF_GPMI_STAT_DEV1_ERROR(v) (((v) << 1) & 0x2) | ||
| 274 | #define BP_GPMI_STAT_DEV0_ERROR 0 | ||
| 275 | #define BM_GPMI_STAT_DEV0_ERROR 0x1 | ||
| 276 | #define BF_GPMI_STAT_DEV0_ERROR(v) (((v) << 0) & 0x1) | ||
| 277 | |||
| 278 | /** | ||
| 279 | * Register: HW_GPMI_DEBUG | ||
| 280 | * Address: 0x80 | ||
| 281 | * SCT: no | ||
| 282 | */ | ||
| 283 | #define HW_GPMI_DEBUG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x80)) | ||
| 284 | #define BP_GPMI_DEBUG_READY3 31 | ||
| 285 | #define BM_GPMI_DEBUG_READY3 0x80000000 | ||
| 286 | #define BF_GPMI_DEBUG_READY3(v) (((v) << 31) & 0x80000000) | ||
| 287 | #define BP_GPMI_DEBUG_READY2 30 | ||
| 288 | #define BM_GPMI_DEBUG_READY2 0x40000000 | ||
| 289 | #define BF_GPMI_DEBUG_READY2(v) (((v) << 30) & 0x40000000) | ||
| 290 | #define BP_GPMI_DEBUG_READY1 29 | ||
| 291 | #define BM_GPMI_DEBUG_READY1 0x20000000 | ||
| 292 | #define BF_GPMI_DEBUG_READY1(v) (((v) << 29) & 0x20000000) | ||
| 293 | #define BP_GPMI_DEBUG_READY0 28 | ||
| 294 | #define BM_GPMI_DEBUG_READY0 0x10000000 | ||
| 295 | #define BF_GPMI_DEBUG_READY0(v) (((v) << 28) & 0x10000000) | ||
| 296 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END3 27 | ||
| 297 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 0x8000000 | ||
| 298 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v) (((v) << 27) & 0x8000000) | ||
| 299 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END2 26 | ||
| 300 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 0x4000000 | ||
| 301 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v) (((v) << 26) & 0x4000000) | ||
| 302 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END1 25 | ||
| 303 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 0x2000000 | ||
| 304 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v) (((v) << 25) & 0x2000000) | ||
| 305 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END0 24 | ||
| 306 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 0x1000000 | ||
| 307 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v) (((v) << 24) & 0x1000000) | ||
| 308 | #define BP_GPMI_DEBUG_SENSE3 23 | ||
| 309 | #define BM_GPMI_DEBUG_SENSE3 0x800000 | ||
| 310 | #define BF_GPMI_DEBUG_SENSE3(v) (((v) << 23) & 0x800000) | ||
| 311 | #define BP_GPMI_DEBUG_SENSE2 22 | ||
| 312 | #define BM_GPMI_DEBUG_SENSE2 0x400000 | ||
| 313 | #define BF_GPMI_DEBUG_SENSE2(v) (((v) << 22) & 0x400000) | ||
| 314 | #define BP_GPMI_DEBUG_SENSE1 21 | ||
| 315 | #define BM_GPMI_DEBUG_SENSE1 0x200000 | ||
| 316 | #define BF_GPMI_DEBUG_SENSE1(v) (((v) << 21) & 0x200000) | ||
| 317 | #define BP_GPMI_DEBUG_SENSE0 20 | ||
| 318 | #define BM_GPMI_DEBUG_SENSE0 0x100000 | ||
| 319 | #define BF_GPMI_DEBUG_SENSE0(v) (((v) << 20) & 0x100000) | ||
| 320 | #define BP_GPMI_DEBUG_DMAREQ3 19 | ||
| 321 | #define BM_GPMI_DEBUG_DMAREQ3 0x80000 | ||
| 322 | #define BF_GPMI_DEBUG_DMAREQ3(v) (((v) << 19) & 0x80000) | ||
| 323 | #define BP_GPMI_DEBUG_DMAREQ2 18 | ||
| 324 | #define BM_GPMI_DEBUG_DMAREQ2 0x40000 | ||
| 325 | #define BF_GPMI_DEBUG_DMAREQ2(v) (((v) << 18) & 0x40000) | ||
| 326 | #define BP_GPMI_DEBUG_DMAREQ1 17 | ||
| 327 | #define BM_GPMI_DEBUG_DMAREQ1 0x20000 | ||
| 328 | #define BF_GPMI_DEBUG_DMAREQ1(v) (((v) << 17) & 0x20000) | ||
| 329 | #define BP_GPMI_DEBUG_DMAREQ0 16 | ||
| 330 | #define BM_GPMI_DEBUG_DMAREQ0 0x10000 | ||
| 331 | #define BF_GPMI_DEBUG_DMAREQ0(v) (((v) << 16) & 0x10000) | ||
| 332 | #define BP_GPMI_DEBUG_CMD_END 12 | ||
| 333 | #define BM_GPMI_DEBUG_CMD_END 0xf000 | ||
| 334 | #define BF_GPMI_DEBUG_CMD_END(v) (((v) << 12) & 0xf000) | ||
| 335 | #define BP_GPMI_DEBUG_UDMA_STATE 8 | ||
| 336 | #define BM_GPMI_DEBUG_UDMA_STATE 0xf00 | ||
| 337 | #define BF_GPMI_DEBUG_UDMA_STATE(v) (((v) << 8) & 0xf00) | ||
| 338 | #define BP_GPMI_DEBUG_BUSY 7 | ||
| 339 | #define BM_GPMI_DEBUG_BUSY 0x80 | ||
| 340 | #define BV_GPMI_DEBUG_BUSY__DISABLED 0x0 | ||
| 341 | #define BV_GPMI_DEBUG_BUSY__ENABLED 0x1 | ||
| 342 | #define BF_GPMI_DEBUG_BUSY(v) (((v) << 7) & 0x80) | ||
| 343 | #define BF_GPMI_DEBUG_BUSY_V(v) ((BV_GPMI_DEBUG_BUSY__##v << 7) & 0x80) | ||
| 344 | #define BP_GPMI_DEBUG_PIN_STATE 4 | ||
| 345 | #define BM_GPMI_DEBUG_PIN_STATE 0x70 | ||
| 346 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0 | ||
| 347 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1 | ||
| 348 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2 | ||
| 349 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3 | ||
| 350 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4 | ||
| 351 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5 | ||
| 352 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6 | ||
| 353 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7 | ||
| 354 | #define BF_GPMI_DEBUG_PIN_STATE(v) (((v) << 4) & 0x70) | ||
| 355 | #define BF_GPMI_DEBUG_PIN_STATE_V(v) ((BV_GPMI_DEBUG_PIN_STATE__##v << 4) & 0x70) | ||
| 356 | #define BP_GPMI_DEBUG_MAIN_STATE 0 | ||
| 357 | #define BM_GPMI_DEBUG_MAIN_STATE 0xf | ||
| 358 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0 | ||
| 359 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1 | ||
| 360 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2 | ||
| 361 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3 | ||
| 362 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4 | ||
| 363 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5 | ||
| 364 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6 | ||
| 365 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7 | ||
| 366 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8 | ||
| 367 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9 | ||
| 368 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xa | ||
| 369 | #define BF_GPMI_DEBUG_MAIN_STATE(v) (((v) << 0) & 0xf) | ||
| 370 | #define BF_GPMI_DEBUG_MAIN_STATE_V(v) ((BV_GPMI_DEBUG_MAIN_STATE__##v << 0) & 0xf) | ||
| 371 | |||
| 372 | #endif /* __HEADERGEN__STMP3600__GPMI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h new file mode 100644 index 0000000000..b6e5ead2ba --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h | |||
| @@ -0,0 +1,223 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__HWECC__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__HWECC__H__ | ||
| 25 | |||
| 26 | #define REGS_HWECC_BASE (0x80008000) | ||
| 27 | |||
| 28 | #define REGS_HWECC_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_HWECC_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_HWECC_CTRL (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_HWECC_CTRL_SET (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_HWECC_CTRL_CLR (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_HWECC_CTRL_TOG (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_HWECC_CTRL_SFTRST 31 | ||
| 40 | #define BM_HWECC_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_HWECC_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_HWECC_CTRL_CLKGATE 30 | ||
| 43 | #define BM_HWECC_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_HWECC_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_HWECC_CTRL_NUM_SYMBOLS 16 | ||
| 46 | #define BM_HWECC_CTRL_NUM_SYMBOLS 0x1ff0000 | ||
| 47 | #define BF_HWECC_CTRL_NUM_SYMBOLS(v) (((v) << 16) & 0x1ff0000) | ||
| 48 | #define BP_HWECC_CTRL_DMAWAIT_COUNT 8 | ||
| 49 | #define BM_HWECC_CTRL_DMAWAIT_COUNT 0x1f00 | ||
| 50 | #define BF_HWECC_CTRL_DMAWAIT_COUNT(v) (((v) << 8) & 0x1f00) | ||
| 51 | #define BP_HWECC_CTRL_BYTE_ENABLE 6 | ||
| 52 | #define BM_HWECC_CTRL_BYTE_ENABLE 0x40 | ||
| 53 | #define BF_HWECC_CTRL_BYTE_ENABLE(v) (((v) << 6) & 0x40) | ||
| 54 | #define BP_HWECC_CTRL_ECC_SEL 5 | ||
| 55 | #define BM_HWECC_CTRL_ECC_SEL 0x20 | ||
| 56 | #define BF_HWECC_CTRL_ECC_SEL(v) (((v) << 5) & 0x20) | ||
| 57 | #define BP_HWECC_CTRL_ENC_SEL 4 | ||
| 58 | #define BM_HWECC_CTRL_ENC_SEL 0x10 | ||
| 59 | #define BF_HWECC_CTRL_ENC_SEL(v) (((v) << 4) & 0x10) | ||
| 60 | #define BP_HWECC_CTRL_UNCORR_IRQ 2 | ||
| 61 | #define BM_HWECC_CTRL_UNCORR_IRQ 0x4 | ||
| 62 | #define BF_HWECC_CTRL_UNCORR_IRQ(v) (((v) << 2) & 0x4) | ||
| 63 | #define BP_HWECC_CTRL_UNCORR_IRQ_EN 1 | ||
| 64 | #define BM_HWECC_CTRL_UNCORR_IRQ_EN 0x2 | ||
| 65 | #define BF_HWECC_CTRL_UNCORR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
| 66 | #define BP_HWECC_CTRL_RUN 0 | ||
| 67 | #define BM_HWECC_CTRL_RUN 0x1 | ||
| 68 | #define BF_HWECC_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
| 69 | |||
| 70 | /** | ||
| 71 | * Register: HW_HWECC_STAT | ||
| 72 | * Address: 0x10 | ||
| 73 | * SCT: no | ||
| 74 | */ | ||
| 75 | #define HW_HWECC_STAT (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x10)) | ||
| 76 | #define BP_HWECC_STAT_RSDEC_PRESENT 31 | ||
| 77 | #define BM_HWECC_STAT_RSDEC_PRESENT 0x80000000 | ||
| 78 | #define BF_HWECC_STAT_RSDEC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 79 | #define BP_HWECC_STAT_RSENC_PRESENT 30 | ||
| 80 | #define BM_HWECC_STAT_RSENC_PRESENT 0x40000000 | ||
| 81 | #define BF_HWECC_STAT_RSENC_PRESENT(v) (((v) << 30) & 0x40000000) | ||
| 82 | #define BP_HWECC_STAT_SSDEC_PRESENT 29 | ||
| 83 | #define BM_HWECC_STAT_SSDEC_PRESENT 0x20000000 | ||
| 84 | #define BF_HWECC_STAT_SSDEC_PRESENT(v) (((v) << 29) & 0x20000000) | ||
| 85 | #define BP_HWECC_STAT_SSENC_PRESENT 28 | ||
| 86 | #define BM_HWECC_STAT_SSENC_PRESENT 0x10000000 | ||
| 87 | #define BF_HWECC_STAT_SSENC_PRESENT(v) (((v) << 28) & 0x10000000) | ||
| 88 | |||
| 89 | /** | ||
| 90 | * Register: HW_HWECC_DEBUG0 | ||
| 91 | * Address: 0x20 | ||
| 92 | * SCT: no | ||
| 93 | */ | ||
| 94 | #define HW_HWECC_DEBUG0 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x20)) | ||
| 95 | #define BP_HWECC_DEBUG0_DMA_PENDCMD 29 | ||
| 96 | #define BM_HWECC_DEBUG0_DMA_PENDCMD 0x20000000 | ||
| 97 | #define BF_HWECC_DEBUG0_DMA_PENDCMD(v) (((v) << 29) & 0x20000000) | ||
| 98 | #define BP_HWECC_DEBUG0_DMA_PREQ 28 | ||
| 99 | #define BM_HWECC_DEBUG0_DMA_PREQ 0x10000000 | ||
| 100 | #define BF_HWECC_DEBUG0_DMA_PREQ(v) (((v) << 28) & 0x10000000) | ||
| 101 | #define BP_HWECC_DEBUG0_SYMBOL_STATE 24 | ||
| 102 | #define BM_HWECC_DEBUG0_SYMBOL_STATE 0xf000000 | ||
| 103 | #define BF_HWECC_DEBUG0_SYMBOL_STATE(v) (((v) << 24) & 0xf000000) | ||
| 104 | #define BP_HWECC_DEBUG0_CTRL_STATE 16 | ||
| 105 | #define BM_HWECC_DEBUG0_CTRL_STATE 0x3f0000 | ||
| 106 | #define BF_HWECC_DEBUG0_CTRL_STATE(v) (((v) << 16) & 0x3f0000) | ||
| 107 | #define BP_HWECC_DEBUG0_ECC_EXCEPTION 12 | ||
| 108 | #define BM_HWECC_DEBUG0_ECC_EXCEPTION 0xf000 | ||
| 109 | #define BF_HWECC_DEBUG0_ECC_EXCEPTION(v) (((v) << 12) & 0xf000) | ||
| 110 | #define BP_HWECC_DEBUG0_NUM_BIT_ERRORS 4 | ||
| 111 | #define BM_HWECC_DEBUG0_NUM_BIT_ERRORS 0x3f0 | ||
| 112 | #define BF_HWECC_DEBUG0_NUM_BIT_ERRORS(v) (((v) << 4) & 0x3f0) | ||
| 113 | #define BP_HWECC_DEBUG0_NUM_SYMBOL_ERRORS 0 | ||
| 114 | #define BM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS 0x7 | ||
| 115 | #define BF_HWECC_DEBUG0_NUM_SYMBOL_ERRORS(v) (((v) << 0) & 0x7) | ||
| 116 | |||
| 117 | /** | ||
| 118 | * Register: HW_HWECC_DEBUG1 | ||
| 119 | * Address: 0x30 | ||
| 120 | * SCT: no | ||
| 121 | */ | ||
| 122 | #define HW_HWECC_DEBUG1 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x30)) | ||
| 123 | #define BP_HWECC_DEBUG1_SYNDROME2 18 | ||
| 124 | #define BM_HWECC_DEBUG1_SYNDROME2 0x7fc0000 | ||
| 125 | #define BF_HWECC_DEBUG1_SYNDROME2(v) (((v) << 18) & 0x7fc0000) | ||
| 126 | #define BP_HWECC_DEBUG1_SYNDROME1 9 | ||
| 127 | #define BM_HWECC_DEBUG1_SYNDROME1 0x3fe00 | ||
| 128 | #define BF_HWECC_DEBUG1_SYNDROME1(v) (((v) << 9) & 0x3fe00) | ||
| 129 | #define BP_HWECC_DEBUG1_SYNDROME0 0 | ||
| 130 | #define BM_HWECC_DEBUG1_SYNDROME0 0x1ff | ||
| 131 | #define BF_HWECC_DEBUG1_SYNDROME0(v) (((v) << 0) & 0x1ff) | ||
| 132 | |||
| 133 | /** | ||
| 134 | * Register: HW_HWECC_DEBUG2 | ||
| 135 | * Address: 0x40 | ||
| 136 | * SCT: no | ||
| 137 | */ | ||
| 138 | #define HW_HWECC_DEBUG2 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x40)) | ||
| 139 | #define BP_HWECC_DEBUG2_SYNDROME5 18 | ||
| 140 | #define BM_HWECC_DEBUG2_SYNDROME5 0x7fc0000 | ||
| 141 | #define BF_HWECC_DEBUG2_SYNDROME5(v) (((v) << 18) & 0x7fc0000) | ||
| 142 | #define BP_HWECC_DEBUG2_SYNDROME4 9 | ||
| 143 | #define BM_HWECC_DEBUG2_SYNDROME4 0x3fe00 | ||
| 144 | #define BF_HWECC_DEBUG2_SYNDROME4(v) (((v) << 9) & 0x3fe00) | ||
| 145 | #define BP_HWECC_DEBUG2_SYNDROME3 0 | ||
| 146 | #define BM_HWECC_DEBUG2_SYNDROME3 0x1ff | ||
| 147 | #define BF_HWECC_DEBUG2_SYNDROME3(v) (((v) << 0) & 0x1ff) | ||
| 148 | |||
| 149 | /** | ||
| 150 | * Register: HW_HWECC_DEBUG3 | ||
| 151 | * Address: 0x50 | ||
| 152 | * SCT: no | ||
| 153 | */ | ||
| 154 | #define HW_HWECC_DEBUG3 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x50)) | ||
| 155 | #define BP_HWECC_DEBUG3_OMEGA0 18 | ||
| 156 | #define BM_HWECC_DEBUG3_OMEGA0 0x7fc0000 | ||
| 157 | #define BF_HWECC_DEBUG3_OMEGA0(v) (((v) << 18) & 0x7fc0000) | ||
| 158 | #define BP_HWECC_DEBUG3_SYNDROME7 9 | ||
| 159 | #define BM_HWECC_DEBUG3_SYNDROME7 0x3fe00 | ||
| 160 | #define BF_HWECC_DEBUG3_SYNDROME7(v) (((v) << 9) & 0x3fe00) | ||
| 161 | #define BP_HWECC_DEBUG3_SYNDROME6 0 | ||
| 162 | #define BM_HWECC_DEBUG3_SYNDROME6 0x1ff | ||
| 163 | #define BF_HWECC_DEBUG3_SYNDROME6(v) (((v) << 0) & 0x1ff) | ||
| 164 | |||
| 165 | /** | ||
| 166 | * Register: HW_HWECC_DEBUG4 | ||
| 167 | * Address: 0x60 | ||
| 168 | * SCT: no | ||
| 169 | */ | ||
| 170 | #define HW_HWECC_DEBUG4 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x60)) | ||
| 171 | #define BP_HWECC_DEBUG4_OMEGA3 18 | ||
| 172 | #define BM_HWECC_DEBUG4_OMEGA3 0x7fc0000 | ||
| 173 | #define BF_HWECC_DEBUG4_OMEGA3(v) (((v) << 18) & 0x7fc0000) | ||
| 174 | #define BP_HWECC_DEBUG4_OMEGA2 9 | ||
| 175 | #define BM_HWECC_DEBUG4_OMEGA2 0x3fe00 | ||
| 176 | #define BF_HWECC_DEBUG4_OMEGA2(v) (((v) << 9) & 0x3fe00) | ||
| 177 | #define BP_HWECC_DEBUG4_OMEGA1 0 | ||
| 178 | #define BM_HWECC_DEBUG4_OMEGA1 0x1ff | ||
| 179 | #define BF_HWECC_DEBUG4_OMEGA1(v) (((v) << 0) & 0x1ff) | ||
| 180 | |||
| 181 | /** | ||
| 182 | * Register: HW_HWECC_DEBUG5 | ||
| 183 | * Address: 0x70 | ||
| 184 | * SCT: no | ||
| 185 | */ | ||
| 186 | #define HW_HWECC_DEBUG5 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x70)) | ||
| 187 | #define BP_HWECC_DEBUG5_LAMBDA2 18 | ||
| 188 | #define BM_HWECC_DEBUG5_LAMBDA2 0x7fc0000 | ||
| 189 | #define BF_HWECC_DEBUG5_LAMBDA2(v) (((v) << 18) & 0x7fc0000) | ||
| 190 | #define BP_HWECC_DEBUG5_LAMBDA1 9 | ||
| 191 | #define BM_HWECC_DEBUG5_LAMBDA1 0x3fe00 | ||
| 192 | #define BF_HWECC_DEBUG5_LAMBDA1(v) (((v) << 9) & 0x3fe00) | ||
| 193 | #define BP_HWECC_DEBUG5_LAMBDA0 0 | ||
| 194 | #define BM_HWECC_DEBUG5_LAMBDA0 0x1ff | ||
| 195 | #define BF_HWECC_DEBUG5_LAMBDA0(v) (((v) << 0) & 0x1ff) | ||
| 196 | |||
| 197 | /** | ||
| 198 | * Register: HW_HWECC_DEBUG6 | ||
| 199 | * Address: 0x80 | ||
| 200 | * SCT: no | ||
| 201 | */ | ||
| 202 | #define HW_HWECC_DEBUG6 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x80)) | ||
| 203 | #define BP_HWECC_DEBUG6_LAMBDA4 9 | ||
| 204 | #define BM_HWECC_DEBUG6_LAMBDA4 0x3fe00 | ||
| 205 | #define BF_HWECC_DEBUG6_LAMBDA4(v) (((v) << 9) & 0x3fe00) | ||
| 206 | #define BP_HWECC_DEBUG6_LAMBDA3 0 | ||
| 207 | #define BM_HWECC_DEBUG6_LAMBDA3 0x1ff | ||
| 208 | #define BF_HWECC_DEBUG6_LAMBDA3(v) (((v) << 0) & 0x1ff) | ||
| 209 | |||
| 210 | /** | ||
| 211 | * Register: HW_HWECC_DATA | ||
| 212 | * Address: 0x90 | ||
| 213 | * SCT: yes | ||
| 214 | */ | ||
| 215 | #define HW_HWECC_DATA (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x0)) | ||
| 216 | #define HW_HWECC_DATA_SET (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x4)) | ||
| 217 | #define HW_HWECC_DATA_CLR (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x8)) | ||
| 218 | #define HW_HWECC_DATA_TOG (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0xc)) | ||
| 219 | #define BP_HWECC_DATA_DATA 0 | ||
| 220 | #define BM_HWECC_DATA_DATA 0xffffffff | ||
| 221 | #define BF_HWECC_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 222 | |||
| 223 | #endif /* __HEADERGEN__STMP3600__HWECC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-i2c.h b/firmware/target/arm/imx233/regs/stmp3600/regs-i2c.h new file mode 100644 index 0000000000..0b3317c231 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-i2c.h | |||
| @@ -0,0 +1,521 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__I2C__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__I2C__H__ | ||
| 25 | |||
| 26 | #define REGS_I2C_BASE (0x80058000) | ||
| 27 | |||
| 28 | #define REGS_I2C_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_I2C_CTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_I2C_CTRL0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_I2C_CTRL0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_I2C_CTRL0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_I2C_CTRL0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_I2C_CTRL0_SFTRST 31 | ||
| 40 | #define BM_I2C_CTRL0_SFTRST 0x80000000 | ||
| 41 | #define BV_I2C_CTRL0_SFTRST__RUN 0x0 | ||
| 42 | #define BV_I2C_CTRL0_SFTRST__RESET 0x1 | ||
| 43 | #define BF_I2C_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 44 | #define BF_I2C_CTRL0_SFTRST_V(v) ((BV_I2C_CTRL0_SFTRST__##v << 31) & 0x80000000) | ||
| 45 | #define BP_I2C_CTRL0_CLKGATE 30 | ||
| 46 | #define BM_I2C_CTRL0_CLKGATE 0x40000000 | ||
| 47 | #define BV_I2C_CTRL0_CLKGATE__RUN 0x0 | ||
| 48 | #define BV_I2C_CTRL0_CLKGATE__NO_CLKS 0x1 | ||
| 49 | #define BF_I2C_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 50 | #define BF_I2C_CTRL0_CLKGATE_V(v) ((BV_I2C_CTRL0_CLKGATE__##v << 30) & 0x40000000) | ||
| 51 | #define BP_I2C_CTRL0_RUN 29 | ||
| 52 | #define BM_I2C_CTRL0_RUN 0x20000000 | ||
| 53 | #define BV_I2C_CTRL0_RUN__HALT 0x0 | ||
| 54 | #define BV_I2C_CTRL0_RUN__RUN 0x1 | ||
| 55 | #define BF_I2C_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
| 56 | #define BF_I2C_CTRL0_RUN_V(v) ((BV_I2C_CTRL0_RUN__##v << 29) & 0x20000000) | ||
| 57 | #define BP_I2C_CTRL0_PRE_ACK 27 | ||
| 58 | #define BM_I2C_CTRL0_PRE_ACK 0x8000000 | ||
| 59 | #define BF_I2C_CTRL0_PRE_ACK(v) (((v) << 27) & 0x8000000) | ||
| 60 | #define BP_I2C_CTRL0_ACKNOWLEDGE 26 | ||
| 61 | #define BM_I2C_CTRL0_ACKNOWLEDGE 0x4000000 | ||
| 62 | #define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK 0x0 | ||
| 63 | #define BV_I2C_CTRL0_ACKNOWLEDGE__ACK 0x1 | ||
| 64 | #define BF_I2C_CTRL0_ACKNOWLEDGE(v) (((v) << 26) & 0x4000000) | ||
| 65 | #define BF_I2C_CTRL0_ACKNOWLEDGE_V(v) ((BV_I2C_CTRL0_ACKNOWLEDGE__##v << 26) & 0x4000000) | ||
| 66 | #define BP_I2C_CTRL0_SEND_NAK_ON_LAST 25 | ||
| 67 | #define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x2000000 | ||
| 68 | #define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT 0x0 | ||
| 69 | #define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT 0x1 | ||
| 70 | #define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v) (((v) << 25) & 0x2000000) | ||
| 71 | #define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(v) ((BV_I2C_CTRL0_SEND_NAK_ON_LAST__##v << 25) & 0x2000000) | ||
| 72 | #define BP_I2C_CTRL0_PIO_MODE 24 | ||
| 73 | #define BM_I2C_CTRL0_PIO_MODE 0x1000000 | ||
| 74 | #define BF_I2C_CTRL0_PIO_MODE(v) (((v) << 24) & 0x1000000) | ||
| 75 | #define BP_I2C_CTRL0_MULTI_MASTER 23 | ||
| 76 | #define BM_I2C_CTRL0_MULTI_MASTER 0x800000 | ||
| 77 | #define BV_I2C_CTRL0_MULTI_MASTER__SINGLE 0x0 | ||
| 78 | #define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE 0x1 | ||
| 79 | #define BF_I2C_CTRL0_MULTI_MASTER(v) (((v) << 23) & 0x800000) | ||
| 80 | #define BF_I2C_CTRL0_MULTI_MASTER_V(v) ((BV_I2C_CTRL0_MULTI_MASTER__##v << 23) & 0x800000) | ||
| 81 | #define BP_I2C_CTRL0_CLOCK_HELD 22 | ||
| 82 | #define BM_I2C_CTRL0_CLOCK_HELD 0x400000 | ||
| 83 | #define BV_I2C_CTRL0_CLOCK_HELD__RELEASE 0x0 | ||
| 84 | #define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW 0x1 | ||
| 85 | #define BF_I2C_CTRL0_CLOCK_HELD(v) (((v) << 22) & 0x400000) | ||
| 86 | #define BF_I2C_CTRL0_CLOCK_HELD_V(v) ((BV_I2C_CTRL0_CLOCK_HELD__##v << 22) & 0x400000) | ||
| 87 | #define BP_I2C_CTRL0_RETAIN_CLOCK 21 | ||
| 88 | #define BM_I2C_CTRL0_RETAIN_CLOCK 0x200000 | ||
| 89 | #define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE 0x0 | ||
| 90 | #define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW 0x1 | ||
| 91 | #define BF_I2C_CTRL0_RETAIN_CLOCK(v) (((v) << 21) & 0x200000) | ||
| 92 | #define BF_I2C_CTRL0_RETAIN_CLOCK_V(v) ((BV_I2C_CTRL0_RETAIN_CLOCK__##v << 21) & 0x200000) | ||
| 93 | #define BP_I2C_CTRL0_POST_SEND_STOP 20 | ||
| 94 | #define BM_I2C_CTRL0_POST_SEND_STOP 0x100000 | ||
| 95 | #define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP 0x0 | ||
| 96 | #define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP 0x1 | ||
| 97 | #define BF_I2C_CTRL0_POST_SEND_STOP(v) (((v) << 20) & 0x100000) | ||
| 98 | #define BF_I2C_CTRL0_POST_SEND_STOP_V(v) ((BV_I2C_CTRL0_POST_SEND_STOP__##v << 20) & 0x100000) | ||
| 99 | #define BP_I2C_CTRL0_PRE_SEND_START 19 | ||
| 100 | #define BM_I2C_CTRL0_PRE_SEND_START 0x80000 | ||
| 101 | #define BV_I2C_CTRL0_PRE_SEND_START__NO_START 0x0 | ||
| 102 | #define BV_I2C_CTRL0_PRE_SEND_START__SEND_START 0x1 | ||
| 103 | #define BF_I2C_CTRL0_PRE_SEND_START(v) (((v) << 19) & 0x80000) | ||
| 104 | #define BF_I2C_CTRL0_PRE_SEND_START_V(v) ((BV_I2C_CTRL0_PRE_SEND_START__##v << 19) & 0x80000) | ||
| 105 | #define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 18 | ||
| 106 | #define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 0x40000 | ||
| 107 | #define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0 | ||
| 108 | #define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED 0x1 | ||
| 109 | #define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v) (((v) << 18) & 0x40000) | ||
| 110 | #define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v) ((BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##v << 18) & 0x40000) | ||
| 111 | #define BP_I2C_CTRL0_MASTER_MODE 17 | ||
| 112 | #define BM_I2C_CTRL0_MASTER_MODE 0x20000 | ||
| 113 | #define BV_I2C_CTRL0_MASTER_MODE__SLAVE 0x0 | ||
| 114 | #define BV_I2C_CTRL0_MASTER_MODE__MASTER 0x1 | ||
| 115 | #define BF_I2C_CTRL0_MASTER_MODE(v) (((v) << 17) & 0x20000) | ||
| 116 | #define BF_I2C_CTRL0_MASTER_MODE_V(v) ((BV_I2C_CTRL0_MASTER_MODE__##v << 17) & 0x20000) | ||
| 117 | #define BP_I2C_CTRL0_DIRECTION 16 | ||
| 118 | #define BM_I2C_CTRL0_DIRECTION 0x10000 | ||
| 119 | #define BV_I2C_CTRL0_DIRECTION__RECEIVE 0x0 | ||
| 120 | #define BV_I2C_CTRL0_DIRECTION__TRANSMIT 0x1 | ||
| 121 | #define BF_I2C_CTRL0_DIRECTION(v) (((v) << 16) & 0x10000) | ||
| 122 | #define BF_I2C_CTRL0_DIRECTION_V(v) ((BV_I2C_CTRL0_DIRECTION__##v << 16) & 0x10000) | ||
| 123 | #define BP_I2C_CTRL0_XFER_COUNT 0 | ||
| 124 | #define BM_I2C_CTRL0_XFER_COUNT 0xffff | ||
| 125 | #define BF_I2C_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
| 126 | |||
| 127 | /** | ||
| 128 | * Register: HW_I2C_TIMING0 | ||
| 129 | * Address: 0x10 | ||
| 130 | * SCT: yes | ||
| 131 | */ | ||
| 132 | #define HW_I2C_TIMING0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x0)) | ||
| 133 | #define HW_I2C_TIMING0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x4)) | ||
| 134 | #define HW_I2C_TIMING0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x8)) | ||
| 135 | #define HW_I2C_TIMING0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0xc)) | ||
| 136 | #define BP_I2C_TIMING0_HIGH_COUNT 16 | ||
| 137 | #define BM_I2C_TIMING0_HIGH_COUNT 0x3ff0000 | ||
| 138 | #define BF_I2C_TIMING0_HIGH_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
| 139 | #define BP_I2C_TIMING0_RCV_COUNT 0 | ||
| 140 | #define BM_I2C_TIMING0_RCV_COUNT 0x3ff | ||
| 141 | #define BF_I2C_TIMING0_RCV_COUNT(v) (((v) << 0) & 0x3ff) | ||
| 142 | |||
| 143 | /** | ||
| 144 | * Register: HW_I2C_TIMING1 | ||
| 145 | * Address: 0x20 | ||
| 146 | * SCT: yes | ||
| 147 | */ | ||
| 148 | #define HW_I2C_TIMING1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x0)) | ||
| 149 | #define HW_I2C_TIMING1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x4)) | ||
| 150 | #define HW_I2C_TIMING1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x8)) | ||
| 151 | #define HW_I2C_TIMING1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0xc)) | ||
| 152 | #define BP_I2C_TIMING1_LOW_COUNT 16 | ||
| 153 | #define BM_I2C_TIMING1_LOW_COUNT 0x3ff0000 | ||
| 154 | #define BF_I2C_TIMING1_LOW_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
| 155 | #define BP_I2C_TIMING1_XMIT_COUNT 0 | ||
| 156 | #define BM_I2C_TIMING1_XMIT_COUNT 0x3ff | ||
| 157 | #define BF_I2C_TIMING1_XMIT_COUNT(v) (((v) << 0) & 0x3ff) | ||
| 158 | |||
| 159 | /** | ||
| 160 | * Register: HW_I2C_TIMING2 | ||
| 161 | * Address: 0x30 | ||
| 162 | * SCT: yes | ||
| 163 | */ | ||
| 164 | #define HW_I2C_TIMING2 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x0)) | ||
| 165 | #define HW_I2C_TIMING2_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x4)) | ||
| 166 | #define HW_I2C_TIMING2_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x8)) | ||
| 167 | #define HW_I2C_TIMING2_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0xc)) | ||
| 168 | #define BP_I2C_TIMING2_BUS_FREE 16 | ||
| 169 | #define BM_I2C_TIMING2_BUS_FREE 0x3ff0000 | ||
| 170 | #define BF_I2C_TIMING2_BUS_FREE(v) (((v) << 16) & 0x3ff0000) | ||
| 171 | #define BP_I2C_TIMING2_LEADIN_COUNT 0 | ||
| 172 | #define BM_I2C_TIMING2_LEADIN_COUNT 0x3ff | ||
| 173 | #define BF_I2C_TIMING2_LEADIN_COUNT(v) (((v) << 0) & 0x3ff) | ||
| 174 | |||
| 175 | /** | ||
| 176 | * Register: HW_I2C_CTRL1 | ||
| 177 | * Address: 0x40 | ||
| 178 | * SCT: yes | ||
| 179 | */ | ||
| 180 | #define HW_I2C_CTRL1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x0)) | ||
| 181 | #define HW_I2C_CTRL1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x4)) | ||
| 182 | #define HW_I2C_CTRL1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x8)) | ||
| 183 | #define HW_I2C_CTRL1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0xc)) | ||
| 184 | #define BP_I2C_CTRL1_BCAST_SLAVE_EN 24 | ||
| 185 | #define BM_I2C_CTRL1_BCAST_SLAVE_EN 0x1000000 | ||
| 186 | #define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST 0x0 | ||
| 187 | #define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST 0x1 | ||
| 188 | #define BF_I2C_CTRL1_BCAST_SLAVE_EN(v) (((v) << 24) & 0x1000000) | ||
| 189 | #define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(v) ((BV_I2C_CTRL1_BCAST_SLAVE_EN__##v << 24) & 0x1000000) | ||
| 190 | #define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE 16 | ||
| 191 | #define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE 0xff0000 | ||
| 192 | #define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) (((v) << 16) & 0xff0000) | ||
| 193 | #define BP_I2C_CTRL1_BUS_FREE_IRQ_EN 15 | ||
| 194 | #define BM_I2C_CTRL1_BUS_FREE_IRQ_EN 0x8000 | ||
| 195 | #define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED 0x0 | ||
| 196 | #define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED 0x1 | ||
| 197 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v) (((v) << 15) & 0x8000) | ||
| 198 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v) ((BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##v << 15) & 0x8000) | ||
| 199 | #define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 14 | ||
| 200 | #define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 0x4000 | ||
| 201 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED 0x0 | ||
| 202 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED 0x1 | ||
| 203 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
| 204 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v) ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##v << 14) & 0x4000) | ||
| 205 | #define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 13 | ||
| 206 | #define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 0x2000 | ||
| 207 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED 0x0 | ||
| 208 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED 0x1 | ||
| 209 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v) (((v) << 13) & 0x2000) | ||
| 210 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v) ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##v << 13) & 0x2000) | ||
| 211 | #define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 12 | ||
| 212 | #define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 0x1000 | ||
| 213 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED 0x0 | ||
| 214 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED 0x1 | ||
| 215 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v) (((v) << 12) & 0x1000) | ||
| 216 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v) ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##v << 12) & 0x1000) | ||
| 217 | #define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN 11 | ||
| 218 | #define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN 0x800 | ||
| 219 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED 0x0 | ||
| 220 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED 0x1 | ||
| 221 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v) (((v) << 11) & 0x800) | ||
| 222 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v) ((BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##v << 11) & 0x800) | ||
| 223 | #define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN 10 | ||
| 224 | #define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN 0x400 | ||
| 225 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED 0x0 | ||
| 226 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED 0x1 | ||
| 227 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v) (((v) << 10) & 0x400) | ||
| 228 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v) ((BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##v << 10) & 0x400) | ||
| 229 | #define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN 9 | ||
| 230 | #define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN 0x200 | ||
| 231 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED 0x0 | ||
| 232 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED 0x1 | ||
| 233 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v) (((v) << 9) & 0x200) | ||
| 234 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v) ((BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##v << 9) & 0x200) | ||
| 235 | #define BP_I2C_CTRL1_SLAVE_IRQ_EN 8 | ||
| 236 | #define BM_I2C_CTRL1_SLAVE_IRQ_EN 0x100 | ||
| 237 | #define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED 0x0 | ||
| 238 | #define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED 0x1 | ||
| 239 | #define BF_I2C_CTRL1_SLAVE_IRQ_EN(v) (((v) << 8) & 0x100) | ||
| 240 | #define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(v) ((BV_I2C_CTRL1_SLAVE_IRQ_EN__##v << 8) & 0x100) | ||
| 241 | #define BP_I2C_CTRL1_BUS_FREE_IRQ 7 | ||
| 242 | #define BM_I2C_CTRL1_BUS_FREE_IRQ 0x80 | ||
| 243 | #define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST 0x0 | ||
| 244 | #define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST 0x1 | ||
| 245 | #define BF_I2C_CTRL1_BUS_FREE_IRQ(v) (((v) << 7) & 0x80) | ||
| 246 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_V(v) ((BV_I2C_CTRL1_BUS_FREE_IRQ__##v << 7) & 0x80) | ||
| 247 | #define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 6 | ||
| 248 | #define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40 | ||
| 249 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST 0x0 | ||
| 250 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST 0x1 | ||
| 251 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v) (((v) << 6) & 0x40) | ||
| 252 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v) ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##v << 6) & 0x40) | ||
| 253 | #define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ 5 | ||
| 254 | #define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20 | ||
| 255 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST 0x0 | ||
| 256 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST 0x1 | ||
| 257 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v) (((v) << 5) & 0x20) | ||
| 258 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v) ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##v << 5) & 0x20) | ||
| 259 | #define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 4 | ||
| 260 | #define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10 | ||
| 261 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST 0x0 | ||
| 262 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST 0x1 | ||
| 263 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v) (((v) << 4) & 0x10) | ||
| 264 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v) ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##v << 4) & 0x10) | ||
| 265 | #define BP_I2C_CTRL1_EARLY_TERM_IRQ 3 | ||
| 266 | #define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x8 | ||
| 267 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST 0x0 | ||
| 268 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST 0x1 | ||
| 269 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ(v) (((v) << 3) & 0x8) | ||
| 270 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(v) ((BV_I2C_CTRL1_EARLY_TERM_IRQ__##v << 3) & 0x8) | ||
| 271 | #define BP_I2C_CTRL1_MASTER_LOSS_IRQ 2 | ||
| 272 | #define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x4 | ||
| 273 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST 0x0 | ||
| 274 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST 0x1 | ||
| 275 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v) (((v) << 2) & 0x4) | ||
| 276 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(v) ((BV_I2C_CTRL1_MASTER_LOSS_IRQ__##v << 2) & 0x4) | ||
| 277 | #define BP_I2C_CTRL1_SLAVE_STOP_IRQ 1 | ||
| 278 | #define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x2 | ||
| 279 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST 0x0 | ||
| 280 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST 0x1 | ||
| 281 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v) (((v) << 1) & 0x2) | ||
| 282 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(v) ((BV_I2C_CTRL1_SLAVE_STOP_IRQ__##v << 1) & 0x2) | ||
| 283 | #define BP_I2C_CTRL1_SLAVE_IRQ 0 | ||
| 284 | #define BM_I2C_CTRL1_SLAVE_IRQ 0x1 | ||
| 285 | #define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST 0x0 | ||
| 286 | #define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST 0x1 | ||
| 287 | #define BF_I2C_CTRL1_SLAVE_IRQ(v) (((v) << 0) & 0x1) | ||
| 288 | #define BF_I2C_CTRL1_SLAVE_IRQ_V(v) ((BV_I2C_CTRL1_SLAVE_IRQ__##v << 0) & 0x1) | ||
| 289 | |||
| 290 | /** | ||
| 291 | * Register: HW_I2C_STAT | ||
| 292 | * Address: 0x50 | ||
| 293 | * SCT: no | ||
| 294 | */ | ||
| 295 | #define HW_I2C_STAT (*(volatile unsigned long *)(REGS_I2C_BASE + 0x50)) | ||
| 296 | #define BP_I2C_STAT_MASTER_PRESENT 31 | ||
| 297 | #define BM_I2C_STAT_MASTER_PRESENT 0x80000000 | ||
| 298 | #define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE 0x0 | ||
| 299 | #define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE 0x1 | ||
| 300 | #define BF_I2C_STAT_MASTER_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 301 | #define BF_I2C_STAT_MASTER_PRESENT_V(v) ((BV_I2C_STAT_MASTER_PRESENT__##v << 31) & 0x80000000) | ||
| 302 | #define BP_I2C_STAT_SLAVE_PRESENT 30 | ||
| 303 | #define BM_I2C_STAT_SLAVE_PRESENT 0x40000000 | ||
| 304 | #define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE 0x0 | ||
| 305 | #define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE 0x1 | ||
| 306 | #define BF_I2C_STAT_SLAVE_PRESENT(v) (((v) << 30) & 0x40000000) | ||
| 307 | #define BF_I2C_STAT_SLAVE_PRESENT_V(v) ((BV_I2C_STAT_SLAVE_PRESENT__##v << 30) & 0x40000000) | ||
| 308 | #define BP_I2C_STAT_ANY_ENABLED_IRQ 29 | ||
| 309 | #define BM_I2C_STAT_ANY_ENABLED_IRQ 0x20000000 | ||
| 310 | #define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS 0x0 | ||
| 311 | #define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST 0x1 | ||
| 312 | #define BF_I2C_STAT_ANY_ENABLED_IRQ(v) (((v) << 29) & 0x20000000) | ||
| 313 | #define BF_I2C_STAT_ANY_ENABLED_IRQ_V(v) ((BV_I2C_STAT_ANY_ENABLED_IRQ__##v << 29) & 0x20000000) | ||
| 314 | #define BP_I2C_STAT_RCVD_SLAVE_ADDR 16 | ||
| 315 | #define BM_I2C_STAT_RCVD_SLAVE_ADDR 0xff0000 | ||
| 316 | #define BF_I2C_STAT_RCVD_SLAVE_ADDR(v) (((v) << 16) & 0xff0000) | ||
| 317 | #define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO 15 | ||
| 318 | #define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO 0x8000 | ||
| 319 | #define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED 0x0 | ||
| 320 | #define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO 0x1 | ||
| 321 | #define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v) (((v) << 15) & 0x8000) | ||
| 322 | #define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v) ((BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##v << 15) & 0x8000) | ||
| 323 | #define BP_I2C_STAT_SLAVE_FOUND 14 | ||
| 324 | #define BM_I2C_STAT_SLAVE_FOUND 0x4000 | ||
| 325 | #define BV_I2C_STAT_SLAVE_FOUND__IDLE 0x0 | ||
| 326 | #define BV_I2C_STAT_SLAVE_FOUND__WAITING 0x1 | ||
| 327 | #define BF_I2C_STAT_SLAVE_FOUND(v) (((v) << 14) & 0x4000) | ||
| 328 | #define BF_I2C_STAT_SLAVE_FOUND_V(v) ((BV_I2C_STAT_SLAVE_FOUND__##v << 14) & 0x4000) | ||
| 329 | #define BP_I2C_STAT_SLAVE_SEARCHING 13 | ||
| 330 | #define BM_I2C_STAT_SLAVE_SEARCHING 0x2000 | ||
| 331 | #define BV_I2C_STAT_SLAVE_SEARCHING__IDLE 0x0 | ||
| 332 | #define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE 0x1 | ||
| 333 | #define BF_I2C_STAT_SLAVE_SEARCHING(v) (((v) << 13) & 0x2000) | ||
| 334 | #define BF_I2C_STAT_SLAVE_SEARCHING_V(v) ((BV_I2C_STAT_SLAVE_SEARCHING__##v << 13) & 0x2000) | ||
| 335 | #define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT 12 | ||
| 336 | #define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT 0x1000 | ||
| 337 | #define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE 0x0 | ||
| 338 | #define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING 0x1 | ||
| 339 | #define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v) (((v) << 12) & 0x1000) | ||
| 340 | #define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v) ((BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##v << 12) & 0x1000) | ||
| 341 | #define BP_I2C_STAT_BUS_BUSY 11 | ||
| 342 | #define BM_I2C_STAT_BUS_BUSY 0x800 | ||
| 343 | #define BV_I2C_STAT_BUS_BUSY__IDLE 0x0 | ||
| 344 | #define BV_I2C_STAT_BUS_BUSY__BUSY 0x1 | ||
| 345 | #define BF_I2C_STAT_BUS_BUSY(v) (((v) << 11) & 0x800) | ||
| 346 | #define BF_I2C_STAT_BUS_BUSY_V(v) ((BV_I2C_STAT_BUS_BUSY__##v << 11) & 0x800) | ||
| 347 | #define BP_I2C_STAT_CLK_GEN_BUSY 10 | ||
| 348 | #define BM_I2C_STAT_CLK_GEN_BUSY 0x400 | ||
| 349 | #define BV_I2C_STAT_CLK_GEN_BUSY__IDLE 0x0 | ||
| 350 | #define BV_I2C_STAT_CLK_GEN_BUSY__BUSY 0x1 | ||
| 351 | #define BF_I2C_STAT_CLK_GEN_BUSY(v) (((v) << 10) & 0x400) | ||
| 352 | #define BF_I2C_STAT_CLK_GEN_BUSY_V(v) ((BV_I2C_STAT_CLK_GEN_BUSY__##v << 10) & 0x400) | ||
| 353 | #define BP_I2C_STAT_DATA_ENGINE_BUSY 9 | ||
| 354 | #define BM_I2C_STAT_DATA_ENGINE_BUSY 0x200 | ||
| 355 | #define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE 0x0 | ||
| 356 | #define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY 0x1 | ||
| 357 | #define BF_I2C_STAT_DATA_ENGINE_BUSY(v) (((v) << 9) & 0x200) | ||
| 358 | #define BF_I2C_STAT_DATA_ENGINE_BUSY_V(v) ((BV_I2C_STAT_DATA_ENGINE_BUSY__##v << 9) & 0x200) | ||
| 359 | #define BP_I2C_STAT_SLAVE_BUSY 8 | ||
| 360 | #define BM_I2C_STAT_SLAVE_BUSY 0x100 | ||
| 361 | #define BV_I2C_STAT_SLAVE_BUSY__IDLE 0x0 | ||
| 362 | #define BV_I2C_STAT_SLAVE_BUSY__BUSY 0x1 | ||
| 363 | #define BF_I2C_STAT_SLAVE_BUSY(v) (((v) << 8) & 0x100) | ||
| 364 | #define BF_I2C_STAT_SLAVE_BUSY_V(v) ((BV_I2C_STAT_SLAVE_BUSY__##v << 8) & 0x100) | ||
| 365 | #define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY 7 | ||
| 366 | #define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY 0x80 | ||
| 367 | #define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 368 | #define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST 0x1 | ||
| 369 | #define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v) (((v) << 7) & 0x80) | ||
| 370 | #define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##v << 7) & 0x80) | ||
| 371 | #define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 6 | ||
| 372 | #define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 0x40 | ||
| 373 | #define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 374 | #define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST 0x1 | ||
| 375 | #define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v) (((v) << 6) & 0x40) | ||
| 376 | #define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##v << 6) & 0x40) | ||
| 377 | #define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 5 | ||
| 378 | #define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 0x20 | ||
| 379 | #define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 380 | #define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST 0x1 | ||
| 381 | #define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v) (((v) << 5) & 0x20) | ||
| 382 | #define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##v << 5) & 0x20) | ||
| 383 | #define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 4 | ||
| 384 | #define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 0x10 | ||
| 385 | #define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 386 | #define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST 0x1 | ||
| 387 | #define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v) (((v) << 4) & 0x10) | ||
| 388 | #define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##v << 4) & 0x10) | ||
| 389 | #define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 3 | ||
| 390 | #define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 0x8 | ||
| 391 | #define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 392 | #define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST 0x1 | ||
| 393 | #define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v) (((v) << 3) & 0x8) | ||
| 394 | #define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##v << 3) & 0x8) | ||
| 395 | #define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 2 | ||
| 396 | #define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 0x4 | ||
| 397 | #define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 398 | #define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST 0x1 | ||
| 399 | #define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v) (((v) << 2) & 0x4) | ||
| 400 | #define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##v << 2) & 0x4) | ||
| 401 | #define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 1 | ||
| 402 | #define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 0x2 | ||
| 403 | #define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 404 | #define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST 0x1 | ||
| 405 | #define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v) (((v) << 1) & 0x2) | ||
| 406 | #define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##v << 1) & 0x2) | ||
| 407 | #define BP_I2C_STAT_SLAVE_IRQ_SUMMARY 0 | ||
| 408 | #define BM_I2C_STAT_SLAVE_IRQ_SUMMARY 0x1 | ||
| 409 | #define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 410 | #define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST 0x1 | ||
| 411 | #define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v) (((v) << 0) & 0x1) | ||
| 412 | #define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##v << 0) & 0x1) | ||
| 413 | |||
| 414 | /** | ||
| 415 | * Register: HW_I2C_DATA | ||
| 416 | * Address: 0x60 | ||
| 417 | * SCT: no | ||
| 418 | */ | ||
| 419 | #define HW_I2C_DATA (*(volatile unsigned long *)(REGS_I2C_BASE + 0x60)) | ||
| 420 | #define BP_I2C_DATA_DATA 0 | ||
| 421 | #define BM_I2C_DATA_DATA 0xffffffff | ||
| 422 | #define BF_I2C_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 423 | |||
| 424 | /** | ||
| 425 | * Register: HW_I2C_DEBUG0 | ||
| 426 | * Address: 0x70 | ||
| 427 | * SCT: yes | ||
| 428 | */ | ||
| 429 | #define HW_I2C_DEBUG0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x0)) | ||
| 430 | #define HW_I2C_DEBUG0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x4)) | ||
| 431 | #define HW_I2C_DEBUG0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x8)) | ||
| 432 | #define HW_I2C_DEBUG0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0xc)) | ||
| 433 | #define BP_I2C_DEBUG0_DMAREQ 31 | ||
| 434 | #define BM_I2C_DEBUG0_DMAREQ 0x80000000 | ||
| 435 | #define BF_I2C_DEBUG0_DMAREQ(v) (((v) << 31) & 0x80000000) | ||
| 436 | #define BP_I2C_DEBUG0_DMAENDCMD 30 | ||
| 437 | #define BM_I2C_DEBUG0_DMAENDCMD 0x40000000 | ||
| 438 | #define BF_I2C_DEBUG0_DMAENDCMD(v) (((v) << 30) & 0x40000000) | ||
| 439 | #define BP_I2C_DEBUG0_DMAKICK 29 | ||
| 440 | #define BM_I2C_DEBUG0_DMAKICK 0x20000000 | ||
| 441 | #define BF_I2C_DEBUG0_DMAKICK(v) (((v) << 29) & 0x20000000) | ||
| 442 | #define BP_I2C_DEBUG0_TBD 26 | ||
| 443 | #define BM_I2C_DEBUG0_TBD 0x1c000000 | ||
| 444 | #define BF_I2C_DEBUG0_TBD(v) (((v) << 26) & 0x1c000000) | ||
| 445 | #define BP_I2C_DEBUG0_DMA_STATE 16 | ||
| 446 | #define BM_I2C_DEBUG0_DMA_STATE 0x3ff0000 | ||
| 447 | #define BF_I2C_DEBUG0_DMA_STATE(v) (((v) << 16) & 0x3ff0000) | ||
| 448 | #define BP_I2C_DEBUG0_START_TOGGLE 15 | ||
| 449 | #define BM_I2C_DEBUG0_START_TOGGLE 0x8000 | ||
| 450 | #define BF_I2C_DEBUG0_START_TOGGLE(v) (((v) << 15) & 0x8000) | ||
| 451 | #define BP_I2C_DEBUG0_STOP_TOGGLE 14 | ||
| 452 | #define BM_I2C_DEBUG0_STOP_TOGGLE 0x4000 | ||
| 453 | #define BF_I2C_DEBUG0_STOP_TOGGLE(v) (((v) << 14) & 0x4000) | ||
| 454 | #define BP_I2C_DEBUG0_GRAB_TOGGLE 13 | ||
| 455 | #define BM_I2C_DEBUG0_GRAB_TOGGLE 0x2000 | ||
| 456 | #define BF_I2C_DEBUG0_GRAB_TOGGLE(v) (((v) << 13) & 0x2000) | ||
| 457 | #define BP_I2C_DEBUG0_CHANGE_TOGGLE 12 | ||
| 458 | #define BM_I2C_DEBUG0_CHANGE_TOGGLE 0x1000 | ||
| 459 | #define BF_I2C_DEBUG0_CHANGE_TOGGLE(v) (((v) << 12) & 0x1000) | ||
| 460 | #define BP_I2C_DEBUG0_TESTMODE 11 | ||
| 461 | #define BM_I2C_DEBUG0_TESTMODE 0x800 | ||
| 462 | #define BF_I2C_DEBUG0_TESTMODE(v) (((v) << 11) & 0x800) | ||
| 463 | #define BP_I2C_DEBUG0_SLAVE_HOLD_CLK 10 | ||
| 464 | #define BM_I2C_DEBUG0_SLAVE_HOLD_CLK 0x400 | ||
| 465 | #define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v) (((v) << 10) & 0x400) | ||
| 466 | #define BP_I2C_DEBUG0_SLAVE_STATE 0 | ||
| 467 | #define BM_I2C_DEBUG0_SLAVE_STATE 0x3ff | ||
| 468 | #define BF_I2C_DEBUG0_SLAVE_STATE(v) (((v) << 0) & 0x3ff) | ||
| 469 | |||
| 470 | /** | ||
| 471 | * Register: HW_I2C_DEBUG1 | ||
| 472 | * Address: 0x80 | ||
| 473 | * SCT: yes | ||
| 474 | */ | ||
| 475 | #define HW_I2C_DEBUG1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x0)) | ||
| 476 | #define HW_I2C_DEBUG1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x4)) | ||
| 477 | #define HW_I2C_DEBUG1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x8)) | ||
| 478 | #define HW_I2C_DEBUG1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0xc)) | ||
| 479 | #define BP_I2C_DEBUG1_I2C_CLK_IN 31 | ||
| 480 | #define BM_I2C_DEBUG1_I2C_CLK_IN 0x80000000 | ||
| 481 | #define BF_I2C_DEBUG1_I2C_CLK_IN(v) (((v) << 31) & 0x80000000) | ||
| 482 | #define BP_I2C_DEBUG1_I2C_DATA_IN 30 | ||
| 483 | #define BM_I2C_DEBUG1_I2C_DATA_IN 0x40000000 | ||
| 484 | #define BF_I2C_DEBUG1_I2C_DATA_IN(v) (((v) << 30) & 0x40000000) | ||
| 485 | #define BP_I2C_DEBUG1_DMA_BYTE_ENABLES 24 | ||
| 486 | #define BM_I2C_DEBUG1_DMA_BYTE_ENABLES 0xf000000 | ||
| 487 | #define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v) (((v) << 24) & 0xf000000) | ||
| 488 | #define BP_I2C_DEBUG1_CLK_GEN_STATE 16 | ||
| 489 | #define BM_I2C_DEBUG1_CLK_GEN_STATE 0x7f0000 | ||
| 490 | #define BF_I2C_DEBUG1_CLK_GEN_STATE(v) (((v) << 16) & 0x7f0000) | ||
| 491 | #define BP_I2C_DEBUG1_LST_MODE 9 | ||
| 492 | #define BM_I2C_DEBUG1_LST_MODE 0x600 | ||
| 493 | #define BV_I2C_DEBUG1_LST_MODE__BCAST 0x0 | ||
| 494 | #define BV_I2C_DEBUG1_LST_MODE__MY_WRITE 0x1 | ||
| 495 | #define BV_I2C_DEBUG1_LST_MODE__MY_READ 0x2 | ||
| 496 | #define BV_I2C_DEBUG1_LST_MODE__NOT_ME 0x3 | ||
| 497 | #define BF_I2C_DEBUG1_LST_MODE(v) (((v) << 9) & 0x600) | ||
| 498 | #define BF_I2C_DEBUG1_LST_MODE_V(v) ((BV_I2C_DEBUG1_LST_MODE__##v << 9) & 0x600) | ||
| 499 | #define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST 8 | ||
| 500 | #define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST 0x100 | ||
| 501 | #define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v) (((v) << 8) & 0x100) | ||
| 502 | #define BP_I2C_DEBUG1_FORCE_CLK_ON 5 | ||
| 503 | #define BM_I2C_DEBUG1_FORCE_CLK_ON 0x20 | ||
| 504 | #define BF_I2C_DEBUG1_FORCE_CLK_ON(v) (((v) << 5) & 0x20) | ||
| 505 | #define BP_I2C_DEBUG1_FORCE_CLK_IDLE 4 | ||
| 506 | #define BM_I2C_DEBUG1_FORCE_CLK_IDLE 0x10 | ||
| 507 | #define BF_I2C_DEBUG1_FORCE_CLK_IDLE(v) (((v) << 4) & 0x10) | ||
| 508 | #define BP_I2C_DEBUG1_FORCE_ARB_LOSS 3 | ||
| 509 | #define BM_I2C_DEBUG1_FORCE_ARB_LOSS 0x8 | ||
| 510 | #define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v) (((v) << 3) & 0x8) | ||
| 511 | #define BP_I2C_DEBUG1_FORCE_RCV_ACK 2 | ||
| 512 | #define BM_I2C_DEBUG1_FORCE_RCV_ACK 0x4 | ||
| 513 | #define BF_I2C_DEBUG1_FORCE_RCV_ACK(v) (((v) << 2) & 0x4) | ||
| 514 | #define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE 1 | ||
| 515 | #define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE 0x2 | ||
| 516 | #define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v) (((v) << 1) & 0x2) | ||
| 517 | #define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE 0 | ||
| 518 | #define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE 0x1 | ||
| 519 | #define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v) (((v) << 0) & 0x1) | ||
| 520 | |||
| 521 | #endif /* __HEADERGEN__STMP3600__I2C__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-icoll.h b/firmware/target/arm/imx233/regs/stmp3600/regs-icoll.h new file mode 100644 index 0000000000..130ab2ca17 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-icoll.h | |||
| @@ -0,0 +1,348 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__ICOLL__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__ICOLL__H__ | ||
| 25 | |||
| 26 | #define REGS_ICOLL_BASE (0x80000000) | ||
| 27 | |||
| 28 | #define REGS_ICOLL_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_ICOLL_VECTOR | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_ICOLL_VECTOR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_ICOLL_VECTOR_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_ICOLL_VECTOR_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_ICOLL_VECTOR_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_ICOLL_VECTOR_IRQVECTOR 2 | ||
| 40 | #define BM_ICOLL_VECTOR_IRQVECTOR 0xfffffffc | ||
| 41 | #define BF_ICOLL_VECTOR_IRQVECTOR(v) (((v) << 2) & 0xfffffffc) | ||
| 42 | |||
| 43 | /** | ||
| 44 | * Register: HW_ICOLL_LEVELACK | ||
| 45 | * Address: 0x10 | ||
| 46 | * SCT: no | ||
| 47 | */ | ||
| 48 | #define HW_ICOLL_LEVELACK (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x10)) | ||
| 49 | #define BP_ICOLL_LEVELACK_IRQLEVELACK 0 | ||
| 50 | #define BM_ICOLL_LEVELACK_IRQLEVELACK 0xf | ||
| 51 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 | ||
| 52 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2 | ||
| 53 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4 | ||
| 54 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8 | ||
| 55 | #define BF_ICOLL_LEVELACK_IRQLEVELACK(v) (((v) << 0) & 0xf) | ||
| 56 | #define BF_ICOLL_LEVELACK_IRQLEVELACK_V(v) ((BV_ICOLL_LEVELACK_IRQLEVELACK__##v << 0) & 0xf) | ||
| 57 | |||
| 58 | /** | ||
| 59 | * Register: HW_ICOLL_CTRL | ||
| 60 | * Address: 0x20 | ||
| 61 | * SCT: yes | ||
| 62 | */ | ||
| 63 | #define HW_ICOLL_CTRL (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x0)) | ||
| 64 | #define HW_ICOLL_CTRL_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x4)) | ||
| 65 | #define HW_ICOLL_CTRL_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x8)) | ||
| 66 | #define HW_ICOLL_CTRL_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0xc)) | ||
| 67 | #define BP_ICOLL_CTRL_SFTRST 31 | ||
| 68 | #define BM_ICOLL_CTRL_SFTRST 0x80000000 | ||
| 69 | #define BV_ICOLL_CTRL_SFTRST__RUN 0x0 | ||
| 70 | #define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1 | ||
| 71 | #define BF_ICOLL_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 72 | #define BF_ICOLL_CTRL_SFTRST_V(v) ((BV_ICOLL_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
| 73 | #define BP_ICOLL_CTRL_CLKGATE 30 | ||
| 74 | #define BM_ICOLL_CTRL_CLKGATE 0x40000000 | ||
| 75 | #define BV_ICOLL_CTRL_CLKGATE__RUN 0x0 | ||
| 76 | #define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1 | ||
| 77 | #define BF_ICOLL_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 78 | #define BF_ICOLL_CTRL_CLKGATE_V(v) ((BV_ICOLL_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
| 79 | #define BP_ICOLL_CTRL_ENABLE2FIQ35 27 | ||
| 80 | #define BM_ICOLL_CTRL_ENABLE2FIQ35 0x8000000 | ||
| 81 | #define BV_ICOLL_CTRL_ENABLE2FIQ35__DISABLE 0x0 | ||
| 82 | #define BV_ICOLL_CTRL_ENABLE2FIQ35__ENABLE 0x1 | ||
| 83 | #define BF_ICOLL_CTRL_ENABLE2FIQ35(v) (((v) << 27) & 0x8000000) | ||
| 84 | #define BF_ICOLL_CTRL_ENABLE2FIQ35_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ35__##v << 27) & 0x8000000) | ||
| 85 | #define BP_ICOLL_CTRL_ENABLE2FIQ34 26 | ||
| 86 | #define BM_ICOLL_CTRL_ENABLE2FIQ34 0x4000000 | ||
| 87 | #define BV_ICOLL_CTRL_ENABLE2FIQ34__DISABLE 0x0 | ||
| 88 | #define BV_ICOLL_CTRL_ENABLE2FIQ34__ENABLE 0x1 | ||
| 89 | #define BF_ICOLL_CTRL_ENABLE2FIQ34(v) (((v) << 26) & 0x4000000) | ||
| 90 | #define BF_ICOLL_CTRL_ENABLE2FIQ34_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ34__##v << 26) & 0x4000000) | ||
| 91 | #define BP_ICOLL_CTRL_ENABLE2FIQ33 25 | ||
| 92 | #define BM_ICOLL_CTRL_ENABLE2FIQ33 0x2000000 | ||
| 93 | #define BV_ICOLL_CTRL_ENABLE2FIQ33__DISABLE 0x0 | ||
| 94 | #define BV_ICOLL_CTRL_ENABLE2FIQ33__ENABLE 0x1 | ||
| 95 | #define BF_ICOLL_CTRL_ENABLE2FIQ33(v) (((v) << 25) & 0x2000000) | ||
| 96 | #define BF_ICOLL_CTRL_ENABLE2FIQ33_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ33__##v << 25) & 0x2000000) | ||
| 97 | #define BP_ICOLL_CTRL_ENABLE2FIQ32 24 | ||
| 98 | #define BM_ICOLL_CTRL_ENABLE2FIQ32 0x1000000 | ||
| 99 | #define BV_ICOLL_CTRL_ENABLE2FIQ32__DISABLE 0x0 | ||
| 100 | #define BV_ICOLL_CTRL_ENABLE2FIQ32__ENABLE 0x1 | ||
| 101 | #define BF_ICOLL_CTRL_ENABLE2FIQ32(v) (((v) << 24) & 0x1000000) | ||
| 102 | #define BF_ICOLL_CTRL_ENABLE2FIQ32_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ32__##v << 24) & 0x1000000) | ||
| 103 | #define BP_ICOLL_CTRL_BYPASS_FSM 20 | ||
| 104 | #define BM_ICOLL_CTRL_BYPASS_FSM 0x100000 | ||
| 105 | #define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0 | ||
| 106 | #define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1 | ||
| 107 | #define BF_ICOLL_CTRL_BYPASS_FSM(v) (((v) << 20) & 0x100000) | ||
| 108 | #define BF_ICOLL_CTRL_BYPASS_FSM_V(v) ((BV_ICOLL_CTRL_BYPASS_FSM__##v << 20) & 0x100000) | ||
| 109 | #define BP_ICOLL_CTRL_NO_NESTING 19 | ||
| 110 | #define BM_ICOLL_CTRL_NO_NESTING 0x80000 | ||
| 111 | #define BV_ICOLL_CTRL_NO_NESTING__NORMAL 0x0 | ||
| 112 | #define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1 | ||
| 113 | #define BF_ICOLL_CTRL_NO_NESTING(v) (((v) << 19) & 0x80000) | ||
| 114 | #define BF_ICOLL_CTRL_NO_NESTING_V(v) ((BV_ICOLL_CTRL_NO_NESTING__##v << 19) & 0x80000) | ||
| 115 | #define BP_ICOLL_CTRL_ARM_RSE_MODE 18 | ||
| 116 | #define BM_ICOLL_CTRL_ARM_RSE_MODE 0x40000 | ||
| 117 | #define BV_ICOLL_CTRL_ARM_RSE_MODE__MUST_WRITE 0x0 | ||
| 118 | #define BV_ICOLL_CTRL_ARM_RSE_MODE__READ_SIDE_EFFECT 0x1 | ||
| 119 | #define BF_ICOLL_CTRL_ARM_RSE_MODE(v) (((v) << 18) & 0x40000) | ||
| 120 | #define BF_ICOLL_CTRL_ARM_RSE_MODE_V(v) ((BV_ICOLL_CTRL_ARM_RSE_MODE__##v << 18) & 0x40000) | ||
| 121 | #define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE 17 | ||
| 122 | #define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x20000 | ||
| 123 | #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0 | ||
| 124 | #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE 0x1 | ||
| 125 | #define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v) (((v) << 17) & 0x20000) | ||
| 126 | #define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v) ((BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##v << 17) & 0x20000) | ||
| 127 | #define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE 16 | ||
| 128 | #define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x10000 | ||
| 129 | #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0 | ||
| 130 | #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE 0x1 | ||
| 131 | #define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v) (((v) << 16) & 0x10000) | ||
| 132 | #define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v) ((BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##v << 16) & 0x10000) | ||
| 133 | |||
| 134 | /** | ||
| 135 | * Register: HW_ICOLL_STAT | ||
| 136 | * Address: 0x30 | ||
| 137 | * SCT: no | ||
| 138 | */ | ||
| 139 | #define HW_ICOLL_STAT (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x30)) | ||
| 140 | #define BP_ICOLL_STAT_VECTOR_NUMBER 0 | ||
| 141 | #define BM_ICOLL_STAT_VECTOR_NUMBER 0x3f | ||
| 142 | #define BF_ICOLL_STAT_VECTOR_NUMBER(v) (((v) << 0) & 0x3f) | ||
| 143 | |||
| 144 | /** | ||
| 145 | * Register: HW_ICOLL_VBASE | ||
| 146 | * Address: 0x160 | ||
| 147 | * SCT: yes | ||
| 148 | */ | ||
| 149 | #define HW_ICOLL_VBASE (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x0)) | ||
| 150 | #define HW_ICOLL_VBASE_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x4)) | ||
| 151 | #define HW_ICOLL_VBASE_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x8)) | ||
| 152 | #define HW_ICOLL_VBASE_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0xc)) | ||
| 153 | #define BP_ICOLL_VBASE_TABLE_ADDRESS 2 | ||
| 154 | #define BM_ICOLL_VBASE_TABLE_ADDRESS 0xfffffffc | ||
| 155 | #define BF_ICOLL_VBASE_TABLE_ADDRESS(v) (((v) << 2) & 0xfffffffc) | ||
| 156 | |||
| 157 | /** | ||
| 158 | * Register: HW_ICOLL_DEBUG | ||
| 159 | * Address: 0x170 | ||
| 160 | * SCT: no | ||
| 161 | */ | ||
| 162 | #define HW_ICOLL_DEBUG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x170)) | ||
| 163 | #define BP_ICOLL_DEBUG_INSERVICE 28 | ||
| 164 | #define BM_ICOLL_DEBUG_INSERVICE 0xf0000000 | ||
| 165 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1 | ||
| 166 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2 | ||
| 167 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4 | ||
| 168 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8 | ||
| 169 | #define BF_ICOLL_DEBUG_INSERVICE(v) (((v) << 28) & 0xf0000000) | ||
| 170 | #define BF_ICOLL_DEBUG_INSERVICE_V(v) ((BV_ICOLL_DEBUG_INSERVICE__##v << 28) & 0xf0000000) | ||
| 171 | #define BP_ICOLL_DEBUG_LEVEL_REQUESTS 24 | ||
| 172 | #define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0xf000000 | ||
| 173 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1 | ||
| 174 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2 | ||
| 175 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4 | ||
| 176 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8 | ||
| 177 | #define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v) (((v) << 24) & 0xf000000) | ||
| 178 | #define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(v) ((BV_ICOLL_DEBUG_LEVEL_REQUESTS__##v << 24) & 0xf000000) | ||
| 179 | #define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL 20 | ||
| 180 | #define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0xf00000 | ||
| 181 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1 | ||
| 182 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2 | ||
| 183 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4 | ||
| 184 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8 | ||
| 185 | #define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v) (((v) << 20) & 0xf00000) | ||
| 186 | #define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v) ((BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##v << 20) & 0xf00000) | ||
| 187 | #define BP_ICOLL_DEBUG_FIQ 17 | ||
| 188 | #define BM_ICOLL_DEBUG_FIQ 0x20000 | ||
| 189 | #define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0 | ||
| 190 | #define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED 0x1 | ||
| 191 | #define BF_ICOLL_DEBUG_FIQ(v) (((v) << 17) & 0x20000) | ||
| 192 | #define BF_ICOLL_DEBUG_FIQ_V(v) ((BV_ICOLL_DEBUG_FIQ__##v << 17) & 0x20000) | ||
| 193 | #define BP_ICOLL_DEBUG_IRQ 16 | ||
| 194 | #define BM_ICOLL_DEBUG_IRQ 0x10000 | ||
| 195 | #define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0 | ||
| 196 | #define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED 0x1 | ||
| 197 | #define BF_ICOLL_DEBUG_IRQ(v) (((v) << 16) & 0x10000) | ||
| 198 | #define BF_ICOLL_DEBUG_IRQ_V(v) ((BV_ICOLL_DEBUG_IRQ__##v << 16) & 0x10000) | ||
| 199 | #define BP_ICOLL_DEBUG_VECTOR_FSM 0 | ||
| 200 | #define BM_ICOLL_DEBUG_VECTOR_FSM 0x3ff | ||
| 201 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE 0x0 | ||
| 202 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1 0x1 | ||
| 203 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2 0x2 | ||
| 204 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING 0x4 | ||
| 205 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3 0x8 | ||
| 206 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4 0x10 | ||
| 207 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20 | ||
| 208 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40 | ||
| 209 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80 | ||
| 210 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5 0x100 | ||
| 211 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6 0x200 | ||
| 212 | #define BF_ICOLL_DEBUG_VECTOR_FSM(v) (((v) << 0) & 0x3ff) | ||
| 213 | #define BF_ICOLL_DEBUG_VECTOR_FSM_V(v) ((BV_ICOLL_DEBUG_VECTOR_FSM__##v << 0) & 0x3ff) | ||
| 214 | |||
| 215 | /** | ||
| 216 | * Register: HW_ICOLL_DBGFLAG | ||
| 217 | * Address: 0x1a0 | ||
| 218 | * SCT: yes | ||
| 219 | */ | ||
| 220 | #define HW_ICOLL_DBGFLAG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x0)) | ||
| 221 | #define HW_ICOLL_DBGFLAG_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x4)) | ||
| 222 | #define HW_ICOLL_DBGFLAG_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x8)) | ||
| 223 | #define HW_ICOLL_DBGFLAG_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0xc)) | ||
| 224 | #define BP_ICOLL_DBGFLAG_FLAG 0 | ||
| 225 | #define BM_ICOLL_DBGFLAG_FLAG 0xffff | ||
| 226 | #define BF_ICOLL_DBGFLAG_FLAG(v) (((v) << 0) & 0xffff) | ||
| 227 | |||
| 228 | /** | ||
| 229 | * Register: HW_ICOLL_DBGREQUESTn | ||
| 230 | * Address: 0x1b0+n*0x10 | ||
| 231 | * SCT: no | ||
| 232 | */ | ||
| 233 | #define HW_ICOLL_DBGREQUESTn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1b0+(n)*0x10)) | ||
| 234 | #define BP_ICOLL_DBGREQUESTn_BITS 0 | ||
| 235 | #define BM_ICOLL_DBGREQUESTn_BITS 0xffffffff | ||
| 236 | #define BF_ICOLL_DBGREQUESTn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 237 | |||
| 238 | /** | ||
| 239 | * Register: HW_ICOLL_RAWn | ||
| 240 | * Address: 0x40+n*0x10 | ||
| 241 | * SCT: no | ||
| 242 | */ | ||
| 243 | #define HW_ICOLL_RAWn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40+(n)*0x10)) | ||
| 244 | #define BP_ICOLL_RAWn_RAW_IRQS 0 | ||
| 245 | #define BM_ICOLL_RAWn_RAW_IRQS 0xffffffff | ||
| 246 | #define BF_ICOLL_RAWn_RAW_IRQS(v) (((v) << 0) & 0xffffffff) | ||
| 247 | |||
| 248 | /** | ||
| 249 | * Register: HW_ICOLL_DBGREADn | ||
| 250 | * Address: 0x180+n*0x10 | ||
| 251 | * SCT: no | ||
| 252 | */ | ||
| 253 | #define HW_ICOLL_DBGREADn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x180+(n)*0x10)) | ||
| 254 | #define BP_ICOLL_DBGREADn_VALUE 0 | ||
| 255 | #define BM_ICOLL_DBGREADn_VALUE 0xffffffff | ||
| 256 | #define BF_ICOLL_DBGREADn_VALUE(v) (((v) << 0) & 0xffffffff) | ||
| 257 | |||
| 258 | /** | ||
| 259 | * Register: HW_ICOLL_PRIORITYn | ||
| 260 | * Address: 0x60+n*0x10 | ||
| 261 | * SCT: yes | ||
| 262 | */ | ||
| 263 | #define HW_ICOLL_PRIORITYn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x0)) | ||
| 264 | #define HW_ICOLL_PRIORITYn_SET(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x4)) | ||
| 265 | #define HW_ICOLL_PRIORITYn_CLR(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x8)) | ||
| 266 | #define HW_ICOLL_PRIORITYn_TOG(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0xc)) | ||
| 267 | #define BP_ICOLL_PRIORITYn_SOFTIRQ3 27 | ||
| 268 | #define BM_ICOLL_PRIORITYn_SOFTIRQ3 0x8000000 | ||
| 269 | #define BV_ICOLL_PRIORITYn_SOFTIRQ3__NO_INTERRUPT 0x0 | ||
| 270 | #define BV_ICOLL_PRIORITYn_SOFTIRQ3__FORCE_INTERRUPT 0x1 | ||
| 271 | #define BF_ICOLL_PRIORITYn_SOFTIRQ3(v) (((v) << 27) & 0x8000000) | ||
| 272 | #define BF_ICOLL_PRIORITYn_SOFTIRQ3_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ3__##v << 27) & 0x8000000) | ||
| 273 | #define BP_ICOLL_PRIORITYn_ENABLE3 26 | ||
| 274 | #define BM_ICOLL_PRIORITYn_ENABLE3 0x4000000 | ||
| 275 | #define BV_ICOLL_PRIORITYn_ENABLE3__DISABLE 0x0 | ||
| 276 | #define BV_ICOLL_PRIORITYn_ENABLE3__ENABLE 0x1 | ||
| 277 | #define BF_ICOLL_PRIORITYn_ENABLE3(v) (((v) << 26) & 0x4000000) | ||
| 278 | #define BF_ICOLL_PRIORITYn_ENABLE3_V(v) ((BV_ICOLL_PRIORITYn_ENABLE3__##v << 26) & 0x4000000) | ||
| 279 | #define BP_ICOLL_PRIORITYn_PRIORITY3 24 | ||
| 280 | #define BM_ICOLL_PRIORITYn_PRIORITY3 0x3000000 | ||
| 281 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL0 0x0 | ||
| 282 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL1 0x1 | ||
| 283 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL2 0x2 | ||
| 284 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL3 0x3 | ||
| 285 | #define BF_ICOLL_PRIORITYn_PRIORITY3(v) (((v) << 24) & 0x3000000) | ||
| 286 | #define BF_ICOLL_PRIORITYn_PRIORITY3_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY3__##v << 24) & 0x3000000) | ||
| 287 | #define BP_ICOLL_PRIORITYn_SOFTIRQ2 19 | ||
| 288 | #define BM_ICOLL_PRIORITYn_SOFTIRQ2 0x80000 | ||
| 289 | #define BV_ICOLL_PRIORITYn_SOFTIRQ2__NO_INTERRUPT 0x0 | ||
| 290 | #define BV_ICOLL_PRIORITYn_SOFTIRQ2__FORCE_INTERRUPT 0x1 | ||
| 291 | #define BF_ICOLL_PRIORITYn_SOFTIRQ2(v) (((v) << 19) & 0x80000) | ||
| 292 | #define BF_ICOLL_PRIORITYn_SOFTIRQ2_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ2__##v << 19) & 0x80000) | ||
| 293 | #define BP_ICOLL_PRIORITYn_ENABLE2 18 | ||
| 294 | #define BM_ICOLL_PRIORITYn_ENABLE2 0x40000 | ||
| 295 | #define BV_ICOLL_PRIORITYn_ENABLE2__DISABLE 0x0 | ||
| 296 | #define BV_ICOLL_PRIORITYn_ENABLE2__ENABLE 0x1 | ||
| 297 | #define BF_ICOLL_PRIORITYn_ENABLE2(v) (((v) << 18) & 0x40000) | ||
| 298 | #define BF_ICOLL_PRIORITYn_ENABLE2_V(v) ((BV_ICOLL_PRIORITYn_ENABLE2__##v << 18) & 0x40000) | ||
| 299 | #define BP_ICOLL_PRIORITYn_PRIORITY2 16 | ||
| 300 | #define BM_ICOLL_PRIORITYn_PRIORITY2 0x30000 | ||
| 301 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL0 0x0 | ||
| 302 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL1 0x1 | ||
| 303 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL2 0x2 | ||
| 304 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL3 0x3 | ||
| 305 | #define BF_ICOLL_PRIORITYn_PRIORITY2(v) (((v) << 16) & 0x30000) | ||
| 306 | #define BF_ICOLL_PRIORITYn_PRIORITY2_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY2__##v << 16) & 0x30000) | ||
| 307 | #define BP_ICOLL_PRIORITYn_SOFTIRQ1 11 | ||
| 308 | #define BM_ICOLL_PRIORITYn_SOFTIRQ1 0x800 | ||
| 309 | #define BV_ICOLL_PRIORITYn_SOFTIRQ1__NO_INTERRUPT 0x0 | ||
| 310 | #define BV_ICOLL_PRIORITYn_SOFTIRQ1__FORCE_INTERRUPT 0x1 | ||
| 311 | #define BF_ICOLL_PRIORITYn_SOFTIRQ1(v) (((v) << 11) & 0x800) | ||
| 312 | #define BF_ICOLL_PRIORITYn_SOFTIRQ1_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ1__##v << 11) & 0x800) | ||
| 313 | #define BP_ICOLL_PRIORITYn_ENABLE1 10 | ||
| 314 | #define BM_ICOLL_PRIORITYn_ENABLE1 0x400 | ||
| 315 | #define BV_ICOLL_PRIORITYn_ENABLE1__DISABLE 0x0 | ||
| 316 | #define BV_ICOLL_PRIORITYn_ENABLE1__ENABLE 0x1 | ||
| 317 | #define BF_ICOLL_PRIORITYn_ENABLE1(v) (((v) << 10) & 0x400) | ||
| 318 | #define BF_ICOLL_PRIORITYn_ENABLE1_V(v) ((BV_ICOLL_PRIORITYn_ENABLE1__##v << 10) & 0x400) | ||
| 319 | #define BP_ICOLL_PRIORITYn_PRIORITY1 8 | ||
| 320 | #define BM_ICOLL_PRIORITYn_PRIORITY1 0x300 | ||
| 321 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL0 0x0 | ||
| 322 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL1 0x1 | ||
| 323 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL2 0x2 | ||
| 324 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL3 0x3 | ||
| 325 | #define BF_ICOLL_PRIORITYn_PRIORITY1(v) (((v) << 8) & 0x300) | ||
| 326 | #define BF_ICOLL_PRIORITYn_PRIORITY1_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY1__##v << 8) & 0x300) | ||
| 327 | #define BP_ICOLL_PRIORITYn_SOFTIRQ0 3 | ||
| 328 | #define BM_ICOLL_PRIORITYn_SOFTIRQ0 0x8 | ||
| 329 | #define BV_ICOLL_PRIORITYn_SOFTIRQ0__NO_INTERRUPT 0x0 | ||
| 330 | #define BV_ICOLL_PRIORITYn_SOFTIRQ0__FORCE_INTERRUPT 0x1 | ||
| 331 | #define BF_ICOLL_PRIORITYn_SOFTIRQ0(v) (((v) << 3) & 0x8) | ||
| 332 | #define BF_ICOLL_PRIORITYn_SOFTIRQ0_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ0__##v << 3) & 0x8) | ||
| 333 | #define BP_ICOLL_PRIORITYn_ENABLE0 2 | ||
| 334 | #define BM_ICOLL_PRIORITYn_ENABLE0 0x4 | ||
| 335 | #define BV_ICOLL_PRIORITYn_ENABLE0__DISABLE 0x0 | ||
| 336 | #define BV_ICOLL_PRIORITYn_ENABLE0__ENABLE 0x1 | ||
| 337 | #define BF_ICOLL_PRIORITYn_ENABLE0(v) (((v) << 2) & 0x4) | ||
| 338 | #define BF_ICOLL_PRIORITYn_ENABLE0_V(v) ((BV_ICOLL_PRIORITYn_ENABLE0__##v << 2) & 0x4) | ||
| 339 | #define BP_ICOLL_PRIORITYn_PRIORITY0 0 | ||
| 340 | #define BM_ICOLL_PRIORITYn_PRIORITY0 0x3 | ||
| 341 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL0 0x0 | ||
| 342 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL1 0x1 | ||
| 343 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL2 0x2 | ||
| 344 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL3 0x3 | ||
| 345 | #define BF_ICOLL_PRIORITYn_PRIORITY0(v) (((v) << 0) & 0x3) | ||
| 346 | #define BF_ICOLL_PRIORITYn_PRIORITY0_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY0__##v << 0) & 0x3) | ||
| 347 | |||
| 348 | #endif /* __HEADERGEN__STMP3600__ICOLL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-ir.h b/firmware/target/arm/imx233/regs/stmp3600/regs-ir.h new file mode 100644 index 0000000000..56eeabaaa3 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-ir.h | |||
| @@ -0,0 +1,477 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__IR__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__IR__H__ | ||
| 25 | |||
| 26 | #define REGS_IR_BASE (0x80078000) | ||
| 27 | |||
| 28 | #define REGS_IR_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_IR_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_IR_CTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_IR_CTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_IR_CTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_IR_CTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_IR_CTRL_SFTRST 31 | ||
| 40 | #define BM_IR_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BV_IR_CTRL_SFTRST__RUN 0x0 | ||
| 42 | #define BV_IR_CTRL_SFTRST__RESET 0x1 | ||
| 43 | #define BF_IR_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 44 | #define BF_IR_CTRL_SFTRST_V(v) ((BV_IR_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
| 45 | #define BP_IR_CTRL_CLKGATE 30 | ||
| 46 | #define BM_IR_CTRL_CLKGATE 0x40000000 | ||
| 47 | #define BF_IR_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 48 | #define BP_IR_CTRL_MTA 24 | ||
| 49 | #define BM_IR_CTRL_MTA 0x7000000 | ||
| 50 | #define BV_IR_CTRL_MTA__MTA_10MS 0x0 | ||
| 51 | #define BV_IR_CTRL_MTA__MTA_5MS 0x1 | ||
| 52 | #define BV_IR_CTRL_MTA__MTA_1MS 0x2 | ||
| 53 | #define BV_IR_CTRL_MTA__MTA_500US 0x3 | ||
| 54 | #define BV_IR_CTRL_MTA__MTA_100US 0x4 | ||
| 55 | #define BV_IR_CTRL_MTA__MTA_50US 0x5 | ||
| 56 | #define BV_IR_CTRL_MTA__MTA_10US 0x6 | ||
| 57 | #define BV_IR_CTRL_MTA__MTA_0 0x7 | ||
| 58 | #define BF_IR_CTRL_MTA(v) (((v) << 24) & 0x7000000) | ||
| 59 | #define BF_IR_CTRL_MTA_V(v) ((BV_IR_CTRL_MTA__##v << 24) & 0x7000000) | ||
| 60 | #define BP_IR_CTRL_MODE 22 | ||
| 61 | #define BM_IR_CTRL_MODE 0xc00000 | ||
| 62 | #define BV_IR_CTRL_MODE__SIR 0x0 | ||
| 63 | #define BV_IR_CTRL_MODE__MIR 0x1 | ||
| 64 | #define BV_IR_CTRL_MODE__FIR 0x2 | ||
| 65 | #define BV_IR_CTRL_MODE__VFIR 0x3 | ||
| 66 | #define BF_IR_CTRL_MODE(v) (((v) << 22) & 0xc00000) | ||
| 67 | #define BF_IR_CTRL_MODE_V(v) ((BV_IR_CTRL_MODE__##v << 22) & 0xc00000) | ||
| 68 | #define BP_IR_CTRL_SPEED 19 | ||
| 69 | #define BM_IR_CTRL_SPEED 0x380000 | ||
| 70 | #define BV_IR_CTRL_SPEED__SPD000 0x0 | ||
| 71 | #define BV_IR_CTRL_SPEED__SPD001 0x1 | ||
| 72 | #define BV_IR_CTRL_SPEED__SPD010 0x2 | ||
| 73 | #define BV_IR_CTRL_SPEED__SPD011 0x3 | ||
| 74 | #define BV_IR_CTRL_SPEED__SPD100 0x4 | ||
| 75 | #define BV_IR_CTRL_SPEED__SPD101 0x5 | ||
| 76 | #define BF_IR_CTRL_SPEED(v) (((v) << 19) & 0x380000) | ||
| 77 | #define BF_IR_CTRL_SPEED_V(v) ((BV_IR_CTRL_SPEED__##v << 19) & 0x380000) | ||
| 78 | #define BP_IR_CTRL_TC_TIME_DIV 8 | ||
| 79 | #define BM_IR_CTRL_TC_TIME_DIV 0x3f00 | ||
| 80 | #define BF_IR_CTRL_TC_TIME_DIV(v) (((v) << 8) & 0x3f00) | ||
| 81 | #define BP_IR_CTRL_TC_TYPE 7 | ||
| 82 | #define BM_IR_CTRL_TC_TYPE 0x80 | ||
| 83 | #define BF_IR_CTRL_TC_TYPE(v) (((v) << 7) & 0x80) | ||
| 84 | #define BP_IR_CTRL_SIR_GAP 4 | ||
| 85 | #define BM_IR_CTRL_SIR_GAP 0x70 | ||
| 86 | #define BV_IR_CTRL_SIR_GAP__GAP_10K 0x0 | ||
| 87 | #define BV_IR_CTRL_SIR_GAP__GAP_5K 0x1 | ||
| 88 | #define BV_IR_CTRL_SIR_GAP__GAP_1K 0x2 | ||
| 89 | #define BV_IR_CTRL_SIR_GAP__GAP_500 0x3 | ||
| 90 | #define BV_IR_CTRL_SIR_GAP__GAP_100 0x4 | ||
| 91 | #define BV_IR_CTRL_SIR_GAP__GAP_50 0x5 | ||
| 92 | #define BV_IR_CTRL_SIR_GAP__GAP_10 0x6 | ||
| 93 | #define BV_IR_CTRL_SIR_GAP__GAP_0 0x7 | ||
| 94 | #define BF_IR_CTRL_SIR_GAP(v) (((v) << 4) & 0x70) | ||
| 95 | #define BF_IR_CTRL_SIR_GAP_V(v) ((BV_IR_CTRL_SIR_GAP__##v << 4) & 0x70) | ||
| 96 | #define BP_IR_CTRL_SIPEN 3 | ||
| 97 | #define BM_IR_CTRL_SIPEN 0x8 | ||
| 98 | #define BF_IR_CTRL_SIPEN(v) (((v) << 3) & 0x8) | ||
| 99 | #define BP_IR_CTRL_TCEN 2 | ||
| 100 | #define BM_IR_CTRL_TCEN 0x4 | ||
| 101 | #define BF_IR_CTRL_TCEN(v) (((v) << 2) & 0x4) | ||
| 102 | #define BP_IR_CTRL_TXEN 1 | ||
| 103 | #define BM_IR_CTRL_TXEN 0x2 | ||
| 104 | #define BF_IR_CTRL_TXEN(v) (((v) << 1) & 0x2) | ||
| 105 | #define BP_IR_CTRL_RXEN 0 | ||
| 106 | #define BM_IR_CTRL_RXEN 0x1 | ||
| 107 | #define BF_IR_CTRL_RXEN(v) (((v) << 0) & 0x1) | ||
| 108 | |||
| 109 | /** | ||
| 110 | * Register: HW_IR_TXDMA | ||
| 111 | * Address: 0x10 | ||
| 112 | * SCT: yes | ||
| 113 | */ | ||
| 114 | #define HW_IR_TXDMA (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x0)) | ||
| 115 | #define HW_IR_TXDMA_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x4)) | ||
| 116 | #define HW_IR_TXDMA_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x8)) | ||
| 117 | #define HW_IR_TXDMA_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0xc)) | ||
| 118 | #define BP_IR_TXDMA_RUN 31 | ||
| 119 | #define BM_IR_TXDMA_RUN 0x80000000 | ||
| 120 | #define BF_IR_TXDMA_RUN(v) (((v) << 31) & 0x80000000) | ||
| 121 | #define BP_IR_TXDMA_EMPTY 29 | ||
| 122 | #define BM_IR_TXDMA_EMPTY 0x20000000 | ||
| 123 | #define BF_IR_TXDMA_EMPTY(v) (((v) << 29) & 0x20000000) | ||
| 124 | #define BP_IR_TXDMA_INT 28 | ||
| 125 | #define BM_IR_TXDMA_INT 0x10000000 | ||
| 126 | #define BF_IR_TXDMA_INT(v) (((v) << 28) & 0x10000000) | ||
| 127 | #define BP_IR_TXDMA_CHANGE 27 | ||
| 128 | #define BM_IR_TXDMA_CHANGE 0x8000000 | ||
| 129 | #define BF_IR_TXDMA_CHANGE(v) (((v) << 27) & 0x8000000) | ||
| 130 | #define BP_IR_TXDMA_NEW_MTA 24 | ||
| 131 | #define BM_IR_TXDMA_NEW_MTA 0x7000000 | ||
| 132 | #define BF_IR_TXDMA_NEW_MTA(v) (((v) << 24) & 0x7000000) | ||
| 133 | #define BP_IR_TXDMA_NEW_MODE 22 | ||
| 134 | #define BM_IR_TXDMA_NEW_MODE 0xc00000 | ||
| 135 | #define BF_IR_TXDMA_NEW_MODE(v) (((v) << 22) & 0xc00000) | ||
| 136 | #define BP_IR_TXDMA_NEW_SPEED 19 | ||
| 137 | #define BM_IR_TXDMA_NEW_SPEED 0x380000 | ||
| 138 | #define BF_IR_TXDMA_NEW_SPEED(v) (((v) << 19) & 0x380000) | ||
| 139 | #define BP_IR_TXDMA_BOF_TYPE 18 | ||
| 140 | #define BM_IR_TXDMA_BOF_TYPE 0x40000 | ||
| 141 | #define BF_IR_TXDMA_BOF_TYPE(v) (((v) << 18) & 0x40000) | ||
| 142 | #define BP_IR_TXDMA_XBOFS 12 | ||
| 143 | #define BM_IR_TXDMA_XBOFS 0x3f000 | ||
| 144 | #define BF_IR_TXDMA_XBOFS(v) (((v) << 12) & 0x3f000) | ||
| 145 | #define BP_IR_TXDMA_XFER_COUNT 0 | ||
| 146 | #define BM_IR_TXDMA_XFER_COUNT 0xfff | ||
| 147 | #define BF_IR_TXDMA_XFER_COUNT(v) (((v) << 0) & 0xfff) | ||
| 148 | |||
| 149 | /** | ||
| 150 | * Register: HW_IR_RXDMA | ||
| 151 | * Address: 0x20 | ||
| 152 | * SCT: yes | ||
| 153 | */ | ||
| 154 | #define HW_IR_RXDMA (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x0)) | ||
| 155 | #define HW_IR_RXDMA_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x4)) | ||
| 156 | #define HW_IR_RXDMA_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x8)) | ||
| 157 | #define HW_IR_RXDMA_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0xc)) | ||
| 158 | #define BP_IR_RXDMA_RUN 31 | ||
| 159 | #define BM_IR_RXDMA_RUN 0x80000000 | ||
| 160 | #define BF_IR_RXDMA_RUN(v) (((v) << 31) & 0x80000000) | ||
| 161 | #define BP_IR_RXDMA_XFER_COUNT 0 | ||
| 162 | #define BM_IR_RXDMA_XFER_COUNT 0x3ff | ||
| 163 | #define BF_IR_RXDMA_XFER_COUNT(v) (((v) << 0) & 0x3ff) | ||
| 164 | |||
| 165 | /** | ||
| 166 | * Register: HW_IR_DBGCTRL | ||
| 167 | * Address: 0x30 | ||
| 168 | * SCT: yes | ||
| 169 | */ | ||
| 170 | #define HW_IR_DBGCTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x0)) | ||
| 171 | #define HW_IR_DBGCTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x4)) | ||
| 172 | #define HW_IR_DBGCTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x8)) | ||
| 173 | #define HW_IR_DBGCTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0xc)) | ||
| 174 | #define BP_IR_DBGCTRL_VFIRSWZ 12 | ||
| 175 | #define BM_IR_DBGCTRL_VFIRSWZ 0x1000 | ||
| 176 | #define BV_IR_DBGCTRL_VFIRSWZ__NORMAL 0x0 | ||
| 177 | #define BV_IR_DBGCTRL_VFIRSWZ__SWAP 0x1 | ||
| 178 | #define BF_IR_DBGCTRL_VFIRSWZ(v) (((v) << 12) & 0x1000) | ||
| 179 | #define BF_IR_DBGCTRL_VFIRSWZ_V(v) ((BV_IR_DBGCTRL_VFIRSWZ__##v << 12) & 0x1000) | ||
| 180 | #define BP_IR_DBGCTRL_RXFRMOFF 11 | ||
| 181 | #define BM_IR_DBGCTRL_RXFRMOFF 0x800 | ||
| 182 | #define BF_IR_DBGCTRL_RXFRMOFF(v) (((v) << 11) & 0x800) | ||
| 183 | #define BP_IR_DBGCTRL_RXCRCOFF 10 | ||
| 184 | #define BM_IR_DBGCTRL_RXCRCOFF 0x400 | ||
| 185 | #define BF_IR_DBGCTRL_RXCRCOFF(v) (((v) << 10) & 0x400) | ||
| 186 | #define BP_IR_DBGCTRL_RXINVERT 9 | ||
| 187 | #define BM_IR_DBGCTRL_RXINVERT 0x200 | ||
| 188 | #define BF_IR_DBGCTRL_RXINVERT(v) (((v) << 9) & 0x200) | ||
| 189 | #define BP_IR_DBGCTRL_TXFRMOFF 8 | ||
| 190 | #define BM_IR_DBGCTRL_TXFRMOFF 0x100 | ||
| 191 | #define BF_IR_DBGCTRL_TXFRMOFF(v) (((v) << 8) & 0x100) | ||
| 192 | #define BP_IR_DBGCTRL_TXCRCOFF 7 | ||
| 193 | #define BM_IR_DBGCTRL_TXCRCOFF 0x80 | ||
| 194 | #define BF_IR_DBGCTRL_TXCRCOFF(v) (((v) << 7) & 0x80) | ||
| 195 | #define BP_IR_DBGCTRL_TXINVERT 6 | ||
| 196 | #define BM_IR_DBGCTRL_TXINVERT 0x40 | ||
| 197 | #define BF_IR_DBGCTRL_TXINVERT(v) (((v) << 6) & 0x40) | ||
| 198 | #define BP_IR_DBGCTRL_INTLOOPBACK 5 | ||
| 199 | #define BM_IR_DBGCTRL_INTLOOPBACK 0x20 | ||
| 200 | #define BF_IR_DBGCTRL_INTLOOPBACK(v) (((v) << 5) & 0x20) | ||
| 201 | #define BP_IR_DBGCTRL_DUPLEX 4 | ||
| 202 | #define BM_IR_DBGCTRL_DUPLEX 0x10 | ||
| 203 | #define BF_IR_DBGCTRL_DUPLEX(v) (((v) << 4) & 0x10) | ||
| 204 | #define BP_IR_DBGCTRL_MIO_RX 3 | ||
| 205 | #define BM_IR_DBGCTRL_MIO_RX 0x8 | ||
| 206 | #define BF_IR_DBGCTRL_MIO_RX(v) (((v) << 3) & 0x8) | ||
| 207 | #define BP_IR_DBGCTRL_MIO_TX 2 | ||
| 208 | #define BM_IR_DBGCTRL_MIO_TX 0x4 | ||
| 209 | #define BF_IR_DBGCTRL_MIO_TX(v) (((v) << 2) & 0x4) | ||
| 210 | #define BP_IR_DBGCTRL_MIO_SCLK 1 | ||
| 211 | #define BM_IR_DBGCTRL_MIO_SCLK 0x2 | ||
| 212 | #define BF_IR_DBGCTRL_MIO_SCLK(v) (((v) << 1) & 0x2) | ||
| 213 | #define BP_IR_DBGCTRL_MIO_EN 0 | ||
| 214 | #define BM_IR_DBGCTRL_MIO_EN 0x1 | ||
| 215 | #define BF_IR_DBGCTRL_MIO_EN(v) (((v) << 0) & 0x1) | ||
| 216 | |||
| 217 | /** | ||
| 218 | * Register: HW_IR_INTR | ||
| 219 | * Address: 0x40 | ||
| 220 | * SCT: yes | ||
| 221 | */ | ||
| 222 | #define HW_IR_INTR (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x0)) | ||
| 223 | #define HW_IR_INTR_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x4)) | ||
| 224 | #define HW_IR_INTR_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x8)) | ||
| 225 | #define HW_IR_INTR_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0xc)) | ||
| 226 | #define BP_IR_INTR_RXABORT_IRQ_EN 22 | ||
| 227 | #define BM_IR_INTR_RXABORT_IRQ_EN 0x400000 | ||
| 228 | #define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0 | ||
| 229 | #define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED 0x1 | ||
| 230 | #define BF_IR_INTR_RXABORT_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
| 231 | #define BF_IR_INTR_RXABORT_IRQ_EN_V(v) ((BV_IR_INTR_RXABORT_IRQ_EN__##v << 22) & 0x400000) | ||
| 232 | #define BP_IR_INTR_SPEED_IRQ_EN 21 | ||
| 233 | #define BM_IR_INTR_SPEED_IRQ_EN 0x200000 | ||
| 234 | #define BV_IR_INTR_SPEED_IRQ_EN__DISABLED 0x0 | ||
| 235 | #define BV_IR_INTR_SPEED_IRQ_EN__ENABLED 0x1 | ||
| 236 | #define BF_IR_INTR_SPEED_IRQ_EN(v) (((v) << 21) & 0x200000) | ||
| 237 | #define BF_IR_INTR_SPEED_IRQ_EN_V(v) ((BV_IR_INTR_SPEED_IRQ_EN__##v << 21) & 0x200000) | ||
| 238 | #define BP_IR_INTR_RXOF_IRQ_EN 20 | ||
| 239 | #define BM_IR_INTR_RXOF_IRQ_EN 0x100000 | ||
| 240 | #define BV_IR_INTR_RXOF_IRQ_EN__DISABLED 0x0 | ||
| 241 | #define BV_IR_INTR_RXOF_IRQ_EN__ENABLED 0x1 | ||
| 242 | #define BF_IR_INTR_RXOF_IRQ_EN(v) (((v) << 20) & 0x100000) | ||
| 243 | #define BF_IR_INTR_RXOF_IRQ_EN_V(v) ((BV_IR_INTR_RXOF_IRQ_EN__##v << 20) & 0x100000) | ||
| 244 | #define BP_IR_INTR_TXUF_IRQ_EN 19 | ||
| 245 | #define BM_IR_INTR_TXUF_IRQ_EN 0x80000 | ||
| 246 | #define BV_IR_INTR_TXUF_IRQ_EN__DISABLED 0x0 | ||
| 247 | #define BV_IR_INTR_TXUF_IRQ_EN__ENABLED 0x1 | ||
| 248 | #define BF_IR_INTR_TXUF_IRQ_EN(v) (((v) << 19) & 0x80000) | ||
| 249 | #define BF_IR_INTR_TXUF_IRQ_EN_V(v) ((BV_IR_INTR_TXUF_IRQ_EN__##v << 19) & 0x80000) | ||
| 250 | #define BP_IR_INTR_TC_IRQ_EN 18 | ||
| 251 | #define BM_IR_INTR_TC_IRQ_EN 0x40000 | ||
| 252 | #define BV_IR_INTR_TC_IRQ_EN__DISABLED 0x0 | ||
| 253 | #define BV_IR_INTR_TC_IRQ_EN__ENABLED 0x1 | ||
| 254 | #define BF_IR_INTR_TC_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
| 255 | #define BF_IR_INTR_TC_IRQ_EN_V(v) ((BV_IR_INTR_TC_IRQ_EN__##v << 18) & 0x40000) | ||
| 256 | #define BP_IR_INTR_RX_IRQ_EN 17 | ||
| 257 | #define BM_IR_INTR_RX_IRQ_EN 0x20000 | ||
| 258 | #define BV_IR_INTR_RX_IRQ_EN__DISABLED 0x0 | ||
| 259 | #define BV_IR_INTR_RX_IRQ_EN__ENABLED 0x1 | ||
| 260 | #define BF_IR_INTR_RX_IRQ_EN(v) (((v) << 17) & 0x20000) | ||
| 261 | #define BF_IR_INTR_RX_IRQ_EN_V(v) ((BV_IR_INTR_RX_IRQ_EN__##v << 17) & 0x20000) | ||
| 262 | #define BP_IR_INTR_TX_IRQ_EN 16 | ||
| 263 | #define BM_IR_INTR_TX_IRQ_EN 0x10000 | ||
| 264 | #define BV_IR_INTR_TX_IRQ_EN__DISABLED 0x0 | ||
| 265 | #define BV_IR_INTR_TX_IRQ_EN__ENABLED 0x1 | ||
| 266 | #define BF_IR_INTR_TX_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
| 267 | #define BF_IR_INTR_TX_IRQ_EN_V(v) ((BV_IR_INTR_TX_IRQ_EN__##v << 16) & 0x10000) | ||
| 268 | #define BP_IR_INTR_RXABORT_IRQ 6 | ||
| 269 | #define BM_IR_INTR_RXABORT_IRQ 0x40 | ||
| 270 | #define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST 0x0 | ||
| 271 | #define BV_IR_INTR_RXABORT_IRQ__REQUEST 0x1 | ||
| 272 | #define BF_IR_INTR_RXABORT_IRQ(v) (((v) << 6) & 0x40) | ||
| 273 | #define BF_IR_INTR_RXABORT_IRQ_V(v) ((BV_IR_INTR_RXABORT_IRQ__##v << 6) & 0x40) | ||
| 274 | #define BP_IR_INTR_SPEED_IRQ 5 | ||
| 275 | #define BM_IR_INTR_SPEED_IRQ 0x20 | ||
| 276 | #define BV_IR_INTR_SPEED_IRQ__NO_REQUEST 0x0 | ||
| 277 | #define BV_IR_INTR_SPEED_IRQ__REQUEST 0x1 | ||
| 278 | #define BF_IR_INTR_SPEED_IRQ(v) (((v) << 5) & 0x20) | ||
| 279 | #define BF_IR_INTR_SPEED_IRQ_V(v) ((BV_IR_INTR_SPEED_IRQ__##v << 5) & 0x20) | ||
| 280 | #define BP_IR_INTR_RXOF_IRQ 4 | ||
| 281 | #define BM_IR_INTR_RXOF_IRQ 0x10 | ||
| 282 | #define BV_IR_INTR_RXOF_IRQ__NO_REQUEST 0x0 | ||
| 283 | #define BV_IR_INTR_RXOF_IRQ__REQUEST 0x1 | ||
| 284 | #define BF_IR_INTR_RXOF_IRQ(v) (((v) << 4) & 0x10) | ||
| 285 | #define BF_IR_INTR_RXOF_IRQ_V(v) ((BV_IR_INTR_RXOF_IRQ__##v << 4) & 0x10) | ||
| 286 | #define BP_IR_INTR_TXUF_IRQ 3 | ||
| 287 | #define BM_IR_INTR_TXUF_IRQ 0x8 | ||
| 288 | #define BV_IR_INTR_TXUF_IRQ__NO_REQUEST 0x0 | ||
| 289 | #define BV_IR_INTR_TXUF_IRQ__REQUEST 0x1 | ||
| 290 | #define BF_IR_INTR_TXUF_IRQ(v) (((v) << 3) & 0x8) | ||
| 291 | #define BF_IR_INTR_TXUF_IRQ_V(v) ((BV_IR_INTR_TXUF_IRQ__##v << 3) & 0x8) | ||
| 292 | #define BP_IR_INTR_TC_IRQ 2 | ||
| 293 | #define BM_IR_INTR_TC_IRQ 0x4 | ||
| 294 | #define BV_IR_INTR_TC_IRQ__NO_REQUEST 0x0 | ||
| 295 | #define BV_IR_INTR_TC_IRQ__REQUEST 0x1 | ||
| 296 | #define BF_IR_INTR_TC_IRQ(v) (((v) << 2) & 0x4) | ||
| 297 | #define BF_IR_INTR_TC_IRQ_V(v) ((BV_IR_INTR_TC_IRQ__##v << 2) & 0x4) | ||
| 298 | #define BP_IR_INTR_RX_IRQ 1 | ||
| 299 | #define BM_IR_INTR_RX_IRQ 0x2 | ||
| 300 | #define BV_IR_INTR_RX_IRQ__NO_REQUEST 0x0 | ||
| 301 | #define BV_IR_INTR_RX_IRQ__REQUEST 0x1 | ||
| 302 | #define BF_IR_INTR_RX_IRQ(v) (((v) << 1) & 0x2) | ||
| 303 | #define BF_IR_INTR_RX_IRQ_V(v) ((BV_IR_INTR_RX_IRQ__##v << 1) & 0x2) | ||
| 304 | #define BP_IR_INTR_TX_IRQ 0 | ||
| 305 | #define BM_IR_INTR_TX_IRQ 0x1 | ||
| 306 | #define BV_IR_INTR_TX_IRQ__NO_REQUEST 0x0 | ||
| 307 | #define BV_IR_INTR_TX_IRQ__REQUEST 0x1 | ||
| 308 | #define BF_IR_INTR_TX_IRQ(v) (((v) << 0) & 0x1) | ||
| 309 | #define BF_IR_INTR_TX_IRQ_V(v) ((BV_IR_INTR_TX_IRQ__##v << 0) & 0x1) | ||
| 310 | |||
| 311 | /** | ||
| 312 | * Register: HW_IR_DATA | ||
| 313 | * Address: 0x50 | ||
| 314 | * SCT: no | ||
| 315 | */ | ||
| 316 | #define HW_IR_DATA (*(volatile unsigned long *)(REGS_IR_BASE + 0x50)) | ||
| 317 | #define BP_IR_DATA_DATA 0 | ||
| 318 | #define BM_IR_DATA_DATA 0xffffffff | ||
| 319 | #define BF_IR_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 320 | |||
| 321 | /** | ||
| 322 | * Register: HW_IR_STAT | ||
| 323 | * Address: 0x60 | ||
| 324 | * SCT: no | ||
| 325 | */ | ||
| 326 | #define HW_IR_STAT (*(volatile unsigned long *)(REGS_IR_BASE + 0x60)) | ||
| 327 | #define BP_IR_STAT_PRESENT 31 | ||
| 328 | #define BM_IR_STAT_PRESENT 0x80000000 | ||
| 329 | #define BV_IR_STAT_PRESENT__UNAVAILABLE 0x0 | ||
| 330 | #define BV_IR_STAT_PRESENT__AVAILABLE 0x1 | ||
| 331 | #define BF_IR_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 332 | #define BF_IR_STAT_PRESENT_V(v) ((BV_IR_STAT_PRESENT__##v << 31) & 0x80000000) | ||
| 333 | #define BP_IR_STAT_MODE_ALLOWED 29 | ||
| 334 | #define BM_IR_STAT_MODE_ALLOWED 0x60000000 | ||
| 335 | #define BV_IR_STAT_MODE_ALLOWED__VFIR 0x0 | ||
| 336 | #define BV_IR_STAT_MODE_ALLOWED__FIR 0x1 | ||
| 337 | #define BV_IR_STAT_MODE_ALLOWED__MIR 0x2 | ||
| 338 | #define BV_IR_STAT_MODE_ALLOWED__SIR 0x3 | ||
| 339 | #define BF_IR_STAT_MODE_ALLOWED(v) (((v) << 29) & 0x60000000) | ||
| 340 | #define BF_IR_STAT_MODE_ALLOWED_V(v) ((BV_IR_STAT_MODE_ALLOWED__##v << 29) & 0x60000000) | ||
| 341 | #define BP_IR_STAT_ANY_IRQ 28 | ||
| 342 | #define BM_IR_STAT_ANY_IRQ 0x10000000 | ||
| 343 | #define BV_IR_STAT_ANY_IRQ__NO_REQUEST 0x0 | ||
| 344 | #define BV_IR_STAT_ANY_IRQ__REQUEST 0x1 | ||
| 345 | #define BF_IR_STAT_ANY_IRQ(v) (((v) << 28) & 0x10000000) | ||
| 346 | #define BF_IR_STAT_ANY_IRQ_V(v) ((BV_IR_STAT_ANY_IRQ__##v << 28) & 0x10000000) | ||
| 347 | #define BP_IR_STAT_RXABORT_SUMMARY 22 | ||
| 348 | #define BM_IR_STAT_RXABORT_SUMMARY 0x400000 | ||
| 349 | #define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST 0x0 | ||
| 350 | #define BV_IR_STAT_RXABORT_SUMMARY__REQUEST 0x1 | ||
| 351 | #define BF_IR_STAT_RXABORT_SUMMARY(v) (((v) << 22) & 0x400000) | ||
| 352 | #define BF_IR_STAT_RXABORT_SUMMARY_V(v) ((BV_IR_STAT_RXABORT_SUMMARY__##v << 22) & 0x400000) | ||
| 353 | #define BP_IR_STAT_SPEED_SUMMARY 21 | ||
| 354 | #define BM_IR_STAT_SPEED_SUMMARY 0x200000 | ||
| 355 | #define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST 0x0 | ||
| 356 | #define BV_IR_STAT_SPEED_SUMMARY__REQUEST 0x1 | ||
| 357 | #define BF_IR_STAT_SPEED_SUMMARY(v) (((v) << 21) & 0x200000) | ||
| 358 | #define BF_IR_STAT_SPEED_SUMMARY_V(v) ((BV_IR_STAT_SPEED_SUMMARY__##v << 21) & 0x200000) | ||
| 359 | #define BP_IR_STAT_RXOF_SUMMARY 20 | ||
| 360 | #define BM_IR_STAT_RXOF_SUMMARY 0x100000 | ||
| 361 | #define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST 0x0 | ||
| 362 | #define BV_IR_STAT_RXOF_SUMMARY__REQUEST 0x1 | ||
| 363 | #define BF_IR_STAT_RXOF_SUMMARY(v) (((v) << 20) & 0x100000) | ||
| 364 | #define BF_IR_STAT_RXOF_SUMMARY_V(v) ((BV_IR_STAT_RXOF_SUMMARY__##v << 20) & 0x100000) | ||
| 365 | #define BP_IR_STAT_TXUF_SUMMARY 19 | ||
| 366 | #define BM_IR_STAT_TXUF_SUMMARY 0x80000 | ||
| 367 | #define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST 0x0 | ||
| 368 | #define BV_IR_STAT_TXUF_SUMMARY__REQUEST 0x1 | ||
| 369 | #define BF_IR_STAT_TXUF_SUMMARY(v) (((v) << 19) & 0x80000) | ||
| 370 | #define BF_IR_STAT_TXUF_SUMMARY_V(v) ((BV_IR_STAT_TXUF_SUMMARY__##v << 19) & 0x80000) | ||
| 371 | #define BP_IR_STAT_TC_SUMMARY 18 | ||
| 372 | #define BM_IR_STAT_TC_SUMMARY 0x40000 | ||
| 373 | #define BV_IR_STAT_TC_SUMMARY__NO_REQUEST 0x0 | ||
| 374 | #define BV_IR_STAT_TC_SUMMARY__REQUEST 0x1 | ||
| 375 | #define BF_IR_STAT_TC_SUMMARY(v) (((v) << 18) & 0x40000) | ||
| 376 | #define BF_IR_STAT_TC_SUMMARY_V(v) ((BV_IR_STAT_TC_SUMMARY__##v << 18) & 0x40000) | ||
| 377 | #define BP_IR_STAT_RX_SUMMARY 17 | ||
| 378 | #define BM_IR_STAT_RX_SUMMARY 0x20000 | ||
| 379 | #define BV_IR_STAT_RX_SUMMARY__NO_REQUEST 0x0 | ||
| 380 | #define BV_IR_STAT_RX_SUMMARY__REQUEST 0x1 | ||
| 381 | #define BF_IR_STAT_RX_SUMMARY(v) (((v) << 17) & 0x20000) | ||
| 382 | #define BF_IR_STAT_RX_SUMMARY_V(v) ((BV_IR_STAT_RX_SUMMARY__##v << 17) & 0x20000) | ||
| 383 | #define BP_IR_STAT_TX_SUMMARY 16 | ||
| 384 | #define BM_IR_STAT_TX_SUMMARY 0x10000 | ||
| 385 | #define BV_IR_STAT_TX_SUMMARY__NO_REQUEST 0x0 | ||
| 386 | #define BV_IR_STAT_TX_SUMMARY__REQUEST 0x1 | ||
| 387 | #define BF_IR_STAT_TX_SUMMARY(v) (((v) << 16) & 0x10000) | ||
| 388 | #define BF_IR_STAT_TX_SUMMARY_V(v) ((BV_IR_STAT_TX_SUMMARY__##v << 16) & 0x10000) | ||
| 389 | #define BP_IR_STAT_MEDIA_BUSY 2 | ||
| 390 | #define BM_IR_STAT_MEDIA_BUSY 0x4 | ||
| 391 | #define BF_IR_STAT_MEDIA_BUSY(v) (((v) << 2) & 0x4) | ||
| 392 | #define BP_IR_STAT_RX_ACTIVE 1 | ||
| 393 | #define BM_IR_STAT_RX_ACTIVE 0x2 | ||
| 394 | #define BF_IR_STAT_RX_ACTIVE(v) (((v) << 1) & 0x2) | ||
| 395 | #define BP_IR_STAT_TX_ACTIVE 0 | ||
| 396 | #define BM_IR_STAT_TX_ACTIVE 0x1 | ||
| 397 | #define BF_IR_STAT_TX_ACTIVE(v) (((v) << 0) & 0x1) | ||
| 398 | |||
| 399 | /** | ||
| 400 | * Register: HW_IR_TCCTRL | ||
| 401 | * Address: 0x70 | ||
| 402 | * SCT: yes | ||
| 403 | */ | ||
| 404 | #define HW_IR_TCCTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x0)) | ||
| 405 | #define HW_IR_TCCTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x4)) | ||
| 406 | #define HW_IR_TCCTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x8)) | ||
| 407 | #define HW_IR_TCCTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0xc)) | ||
| 408 | #define BP_IR_TCCTRL_INIT 31 | ||
| 409 | #define BM_IR_TCCTRL_INIT 0x80000000 | ||
| 410 | #define BF_IR_TCCTRL_INIT(v) (((v) << 31) & 0x80000000) | ||
| 411 | #define BP_IR_TCCTRL_GO 30 | ||
| 412 | #define BM_IR_TCCTRL_GO 0x40000000 | ||
| 413 | #define BF_IR_TCCTRL_GO(v) (((v) << 30) & 0x40000000) | ||
| 414 | #define BP_IR_TCCTRL_BUSY 29 | ||
| 415 | #define BM_IR_TCCTRL_BUSY 0x20000000 | ||
| 416 | #define BF_IR_TCCTRL_BUSY(v) (((v) << 29) & 0x20000000) | ||
| 417 | #define BP_IR_TCCTRL_TEMIC 24 | ||
| 418 | #define BM_IR_TCCTRL_TEMIC 0x1000000 | ||
| 419 | #define BV_IR_TCCTRL_TEMIC__LOW 0x0 | ||
| 420 | #define BV_IR_TCCTRL_TEMIC__HIGH 0x1 | ||
| 421 | #define BF_IR_TCCTRL_TEMIC(v) (((v) << 24) & 0x1000000) | ||
| 422 | #define BF_IR_TCCTRL_TEMIC_V(v) ((BV_IR_TCCTRL_TEMIC__##v << 24) & 0x1000000) | ||
| 423 | #define BP_IR_TCCTRL_EXT_DATA 16 | ||
| 424 | #define BM_IR_TCCTRL_EXT_DATA 0xff0000 | ||
| 425 | #define BF_IR_TCCTRL_EXT_DATA(v) (((v) << 16) & 0xff0000) | ||
| 426 | #define BP_IR_TCCTRL_DATA 8 | ||
| 427 | #define BM_IR_TCCTRL_DATA 0xff00 | ||
| 428 | #define BF_IR_TCCTRL_DATA(v) (((v) << 8) & 0xff00) | ||
| 429 | #define BP_IR_TCCTRL_ADDR 5 | ||
| 430 | #define BM_IR_TCCTRL_ADDR 0xe0 | ||
| 431 | #define BF_IR_TCCTRL_ADDR(v) (((v) << 5) & 0xe0) | ||
| 432 | #define BP_IR_TCCTRL_INDX 1 | ||
| 433 | #define BM_IR_TCCTRL_INDX 0x1e | ||
| 434 | #define BF_IR_TCCTRL_INDX(v) (((v) << 1) & 0x1e) | ||
| 435 | #define BP_IR_TCCTRL_C 0 | ||
| 436 | #define BM_IR_TCCTRL_C 0x1 | ||
| 437 | #define BF_IR_TCCTRL_C(v) (((v) << 0) & 0x1) | ||
| 438 | |||
| 439 | /** | ||
| 440 | * Register: HW_IR_SI_READ | ||
| 441 | * Address: 0x80 | ||
| 442 | * SCT: no | ||
| 443 | */ | ||
| 444 | #define HW_IR_SI_READ (*(volatile unsigned long *)(REGS_IR_BASE + 0x80)) | ||
| 445 | #define BP_IR_SI_READ_ABORT 8 | ||
| 446 | #define BM_IR_SI_READ_ABORT 0x100 | ||
| 447 | #define BF_IR_SI_READ_ABORT(v) (((v) << 8) & 0x100) | ||
| 448 | #define BP_IR_SI_READ_DATA 0 | ||
| 449 | #define BM_IR_SI_READ_DATA 0xff | ||
| 450 | #define BF_IR_SI_READ_DATA(v) (((v) << 0) & 0xff) | ||
| 451 | |||
| 452 | /** | ||
| 453 | * Register: HW_IR_DEBUG | ||
| 454 | * Address: 0x90 | ||
| 455 | * SCT: no | ||
| 456 | */ | ||
| 457 | #define HW_IR_DEBUG (*(volatile unsigned long *)(REGS_IR_BASE + 0x90)) | ||
| 458 | #define BP_IR_DEBUG_TXDMAKICK 5 | ||
| 459 | #define BM_IR_DEBUG_TXDMAKICK 0x20 | ||
| 460 | #define BF_IR_DEBUG_TXDMAKICK(v) (((v) << 5) & 0x20) | ||
| 461 | #define BP_IR_DEBUG_RXDMAKICK 4 | ||
| 462 | #define BM_IR_DEBUG_RXDMAKICK 0x10 | ||
| 463 | #define BF_IR_DEBUG_RXDMAKICK(v) (((v) << 4) & 0x10) | ||
| 464 | #define BP_IR_DEBUG_TXDMAEND 3 | ||
| 465 | #define BM_IR_DEBUG_TXDMAEND 0x8 | ||
| 466 | #define BF_IR_DEBUG_TXDMAEND(v) (((v) << 3) & 0x8) | ||
| 467 | #define BP_IR_DEBUG_RXDMAEND 2 | ||
| 468 | #define BM_IR_DEBUG_RXDMAEND 0x4 | ||
| 469 | #define BF_IR_DEBUG_RXDMAEND(v) (((v) << 2) & 0x4) | ||
| 470 | #define BP_IR_DEBUG_TXDMAREQ 1 | ||
| 471 | #define BM_IR_DEBUG_TXDMAREQ 0x2 | ||
| 472 | #define BF_IR_DEBUG_TXDMAREQ(v) (((v) << 1) & 0x2) | ||
| 473 | #define BP_IR_DEBUG_RXDMAREQ 0 | ||
| 474 | #define BM_IR_DEBUG_RXDMAREQ 0x1 | ||
| 475 | #define BF_IR_DEBUG_RXDMAREQ(v) (((v) << 0) & 0x1) | ||
| 476 | |||
| 477 | #endif /* __HEADERGEN__STMP3600__IR__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-lcdif.h b/firmware/target/arm/imx233/regs/stmp3600/regs-lcdif.h new file mode 100644 index 0000000000..24b17d5905 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-lcdif.h | |||
| @@ -0,0 +1,167 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__LCDIF__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__LCDIF__H__ | ||
| 25 | |||
| 26 | #define REGS_LCDIF_BASE (0x80060000) | ||
| 27 | |||
| 28 | #define REGS_LCDIF_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_LCDIF_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_LCDIF_CTRL (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_LCDIF_CTRL_SET (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_LCDIF_CTRL_CLR (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_LCDIF_CTRL_TOG (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_LCDIF_CTRL_SFTRST 31 | ||
| 40 | #define BM_LCDIF_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_LCDIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_LCDIF_CTRL_CLKGATE 30 | ||
| 43 | #define BM_LCDIF_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_LCDIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_LCDIF_CTRL_PRESENT 29 | ||
| 46 | #define BM_LCDIF_CTRL_PRESENT 0x20000000 | ||
| 47 | #define BF_LCDIF_CTRL_PRESENT(v) (((v) << 29) & 0x20000000) | ||
| 48 | #define BP_LCDIF_CTRL_BUSY_ENABLE 25 | ||
| 49 | #define BM_LCDIF_CTRL_BUSY_ENABLE 0x2000000 | ||
| 50 | #define BV_LCDIF_CTRL_BUSY_ENABLE__BUSY_DISABLED 0x0 | ||
| 51 | #define BV_LCDIF_CTRL_BUSY_ENABLE__BUSY_ENABLED 0x1 | ||
| 52 | #define BF_LCDIF_CTRL_BUSY_ENABLE(v) (((v) << 25) & 0x2000000) | ||
| 53 | #define BF_LCDIF_CTRL_BUSY_ENABLE_V(v) ((BV_LCDIF_CTRL_BUSY_ENABLE__##v << 25) & 0x2000000) | ||
| 54 | #define BP_LCDIF_CTRL_FIFO_STATUS 24 | ||
| 55 | #define BM_LCDIF_CTRL_FIFO_STATUS 0x1000000 | ||
| 56 | #define BV_LCDIF_CTRL_FIFO_STATUS__FIFO_FULL 0x0 | ||
| 57 | #define BV_LCDIF_CTRL_FIFO_STATUS__FIFO_OK 0x1 | ||
| 58 | #define BF_LCDIF_CTRL_FIFO_STATUS(v) (((v) << 24) & 0x1000000) | ||
| 59 | #define BF_LCDIF_CTRL_FIFO_STATUS_V(v) ((BV_LCDIF_CTRL_FIFO_STATUS__##v << 24) & 0x1000000) | ||
| 60 | #define BP_LCDIF_CTRL_DMA_REQ 23 | ||
| 61 | #define BM_LCDIF_CTRL_DMA_REQ 0x800000 | ||
| 62 | #define BF_LCDIF_CTRL_DMA_REQ(v) (((v) << 23) & 0x800000) | ||
| 63 | #define BP_LCDIF_CTRL_DATA_SWIZZLE 21 | ||
| 64 | #define BM_LCDIF_CTRL_DATA_SWIZZLE 0x600000 | ||
| 65 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__NO_SWAP 0x0 | ||
| 66 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 | ||
| 67 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 | ||
| 68 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 | ||
| 69 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_SWAP 0x2 | ||
| 70 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 | ||
| 71 | #define BF_LCDIF_CTRL_DATA_SWIZZLE(v) (((v) << 21) & 0x600000) | ||
| 72 | #define BF_LCDIF_CTRL_DATA_SWIZZLE_V(v) ((BV_LCDIF_CTRL_DATA_SWIZZLE__##v << 21) & 0x600000) | ||
| 73 | #define BP_LCDIF_CTRL_RESET 20 | ||
| 74 | #define BM_LCDIF_CTRL_RESET 0x100000 | ||
| 75 | #define BV_LCDIF_CTRL_RESET__LCDRESET_LOW 0x0 | ||
| 76 | #define BV_LCDIF_CTRL_RESET__LCDRESET_HIGH 0x1 | ||
| 77 | #define BF_LCDIF_CTRL_RESET(v) (((v) << 20) & 0x100000) | ||
| 78 | #define BF_LCDIF_CTRL_RESET_V(v) ((BV_LCDIF_CTRL_RESET__##v << 20) & 0x100000) | ||
| 79 | #define BP_LCDIF_CTRL_MODE86 19 | ||
| 80 | #define BM_LCDIF_CTRL_MODE86 0x80000 | ||
| 81 | #define BV_LCDIF_CTRL_MODE86__8080_MODE 0x0 | ||
| 82 | #define BV_LCDIF_CTRL_MODE86__6800_MODE 0x1 | ||
| 83 | #define BF_LCDIF_CTRL_MODE86(v) (((v) << 19) & 0x80000) | ||
| 84 | #define BF_LCDIF_CTRL_MODE86_V(v) ((BV_LCDIF_CTRL_MODE86__##v << 19) & 0x80000) | ||
| 85 | #define BP_LCDIF_CTRL_DATA_SELECT 18 | ||
| 86 | #define BM_LCDIF_CTRL_DATA_SELECT 0x40000 | ||
| 87 | #define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE 0x0 | ||
| 88 | #define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1 | ||
| 89 | #define BF_LCDIF_CTRL_DATA_SELECT(v) (((v) << 18) & 0x40000) | ||
| 90 | #define BF_LCDIF_CTRL_DATA_SELECT_V(v) ((BV_LCDIF_CTRL_DATA_SELECT__##v << 18) & 0x40000) | ||
| 91 | #define BP_LCDIF_CTRL_WORD_LENGTH 17 | ||
| 92 | #define BM_LCDIF_CTRL_WORD_LENGTH 0x20000 | ||
| 93 | #define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT 0x0 | ||
| 94 | #define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT 0x1 | ||
| 95 | #define BF_LCDIF_CTRL_WORD_LENGTH(v) (((v) << 17) & 0x20000) | ||
| 96 | #define BF_LCDIF_CTRL_WORD_LENGTH_V(v) ((BV_LCDIF_CTRL_WORD_LENGTH__##v << 17) & 0x20000) | ||
| 97 | #define BP_LCDIF_CTRL_RUN 16 | ||
| 98 | #define BM_LCDIF_CTRL_RUN 0x10000 | ||
| 99 | #define BF_LCDIF_CTRL_RUN(v) (((v) << 16) & 0x10000) | ||
| 100 | #define BP_LCDIF_CTRL_COUNT 0 | ||
| 101 | #define BM_LCDIF_CTRL_COUNT 0xffff | ||
| 102 | #define BF_LCDIF_CTRL_COUNT(v) (((v) << 0) & 0xffff) | ||
| 103 | |||
| 104 | /** | ||
| 105 | * Register: HW_LCDIF_TIMING | ||
| 106 | * Address: 0x10 | ||
| 107 | * SCT: no | ||
| 108 | */ | ||
| 109 | #define HW_LCDIF_TIMING (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10)) | ||
| 110 | #define BP_LCDIF_TIMING_CMD_HOLD 24 | ||
| 111 | #define BM_LCDIF_TIMING_CMD_HOLD 0xff000000 | ||
| 112 | #define BF_LCDIF_TIMING_CMD_HOLD(v) (((v) << 24) & 0xff000000) | ||
| 113 | #define BP_LCDIF_TIMING_CMD_SETUP 16 | ||
| 114 | #define BM_LCDIF_TIMING_CMD_SETUP 0xff0000 | ||
| 115 | #define BF_LCDIF_TIMING_CMD_SETUP(v) (((v) << 16) & 0xff0000) | ||
| 116 | #define BP_LCDIF_TIMING_DATA_HOLD 8 | ||
| 117 | #define BM_LCDIF_TIMING_DATA_HOLD 0xff00 | ||
| 118 | #define BF_LCDIF_TIMING_DATA_HOLD(v) (((v) << 8) & 0xff00) | ||
| 119 | #define BP_LCDIF_TIMING_DATA_SETUP 0 | ||
| 120 | #define BM_LCDIF_TIMING_DATA_SETUP 0xff | ||
| 121 | #define BF_LCDIF_TIMING_DATA_SETUP(v) (((v) << 0) & 0xff) | ||
| 122 | |||
| 123 | /** | ||
| 124 | * Register: HW_LCDIF_DATA | ||
| 125 | * Address: 0x20 | ||
| 126 | * SCT: no | ||
| 127 | */ | ||
| 128 | #define HW_LCDIF_DATA (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x20)) | ||
| 129 | #define BP_LCDIF_DATA_DATA_THREE 24 | ||
| 130 | #define BM_LCDIF_DATA_DATA_THREE 0xff000000 | ||
| 131 | #define BF_LCDIF_DATA_DATA_THREE(v) (((v) << 24) & 0xff000000) | ||
| 132 | #define BP_LCDIF_DATA_DATA_TWO 16 | ||
| 133 | #define BM_LCDIF_DATA_DATA_TWO 0xff0000 | ||
| 134 | #define BF_LCDIF_DATA_DATA_TWO(v) (((v) << 16) & 0xff0000) | ||
| 135 | #define BP_LCDIF_DATA_DATA_ONE 8 | ||
| 136 | #define BM_LCDIF_DATA_DATA_ONE 0xff00 | ||
| 137 | #define BF_LCDIF_DATA_DATA_ONE(v) (((v) << 8) & 0xff00) | ||
| 138 | #define BP_LCDIF_DATA_DATA_ZERO 0 | ||
| 139 | #define BM_LCDIF_DATA_DATA_ZERO 0xff | ||
| 140 | #define BF_LCDIF_DATA_DATA_ZERO(v) (((v) << 0) & 0xff) | ||
| 141 | |||
| 142 | /** | ||
| 143 | * Register: HW_LCDIF_DEBUG | ||
| 144 | * Address: 0x30 | ||
| 145 | * SCT: no | ||
| 146 | */ | ||
| 147 | #define HW_LCDIF_DEBUG (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30)) | ||
| 148 | #define BP_LCDIF_DEBUG_BUSY 27 | ||
| 149 | #define BM_LCDIF_DEBUG_BUSY 0x8000000 | ||
| 150 | #define BF_LCDIF_DEBUG_BUSY(v) (((v) << 27) & 0x8000000) | ||
| 151 | #define BP_LCDIF_DEBUG_LAST_SUBWORD 26 | ||
| 152 | #define BM_LCDIF_DEBUG_LAST_SUBWORD 0x4000000 | ||
| 153 | #define BF_LCDIF_DEBUG_LAST_SUBWORD(v) (((v) << 26) & 0x4000000) | ||
| 154 | #define BP_LCDIF_DEBUG_SUBWORD_POSITION 24 | ||
| 155 | #define BM_LCDIF_DEBUG_SUBWORD_POSITION 0x3000000 | ||
| 156 | #define BF_LCDIF_DEBUG_SUBWORD_POSITION(v) (((v) << 24) & 0x3000000) | ||
| 157 | #define BP_LCDIF_DEBUG_EMPTY_WORD 23 | ||
| 158 | #define BM_LCDIF_DEBUG_EMPTY_WORD 0x800000 | ||
| 159 | #define BF_LCDIF_DEBUG_EMPTY_WORD(v) (((v) << 23) & 0x800000) | ||
| 160 | #define BP_LCDIF_DEBUG_STATE 16 | ||
| 161 | #define BM_LCDIF_DEBUG_STATE 0x7f0000 | ||
| 162 | #define BF_LCDIF_DEBUG_STATE(v) (((v) << 16) & 0x7f0000) | ||
| 163 | #define BP_LCDIF_DEBUG_DATA_COUNT 0 | ||
| 164 | #define BM_LCDIF_DEBUG_DATA_COUNT 0xffff | ||
| 165 | #define BF_LCDIF_DEBUG_DATA_COUNT(v) (((v) << 0) & 0xffff) | ||
| 166 | |||
| 167 | #endif /* __HEADERGEN__STMP3600__LCDIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h new file mode 100644 index 0000000000..c799635306 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h | |||
| @@ -0,0 +1,572 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__LRADC__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__LRADC__H__ | ||
| 25 | |||
| 26 | #define REGS_LRADC_BASE (0x80050000) | ||
| 27 | |||
| 28 | #define REGS_LRADC_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_LRADC_CTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_LRADC_CTRL0 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_LRADC_CTRL0_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_LRADC_CTRL0_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_LRADC_CTRL0_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_LRADC_CTRL0_SFTRST 31 | ||
| 40 | #define BM_LRADC_CTRL0_SFTRST 0x80000000 | ||
| 41 | #define BF_LRADC_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_LRADC_CTRL0_CLKGATE 30 | ||
| 43 | #define BM_LRADC_CTRL0_CLKGATE 0x40000000 | ||
| 44 | #define BF_LRADC_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_LRADC_CTRL0_ONCHIP_GROUNDREF 21 | ||
| 46 | #define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x200000 | ||
| 47 | #define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF 0x0 | ||
| 48 | #define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON 0x1 | ||
| 49 | #define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v) (((v) << 21) & 0x200000) | ||
| 50 | #define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v) ((BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##v << 21) & 0x200000) | ||
| 51 | #define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE 20 | ||
| 52 | #define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x100000 | ||
| 53 | #define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0 | ||
| 54 | #define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON 0x1 | ||
| 55 | #define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v) (((v) << 20) & 0x100000) | ||
| 56 | #define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v) ((BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##v << 20) & 0x100000) | ||
| 57 | #define BP_LRADC_CTRL0_YMINUS_ENABLE 19 | ||
| 58 | #define BM_LRADC_CTRL0_YMINUS_ENABLE 0x80000 | ||
| 59 | #define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF 0x0 | ||
| 60 | #define BV_LRADC_CTRL0_YMINUS_ENABLE__ON 0x1 | ||
| 61 | #define BF_LRADC_CTRL0_YMINUS_ENABLE(v) (((v) << 19) & 0x80000) | ||
| 62 | #define BF_LRADC_CTRL0_YMINUS_ENABLE_V(v) ((BV_LRADC_CTRL0_YMINUS_ENABLE__##v << 19) & 0x80000) | ||
| 63 | #define BP_LRADC_CTRL0_XMINUS_ENABLE 18 | ||
| 64 | #define BM_LRADC_CTRL0_XMINUS_ENABLE 0x40000 | ||
| 65 | #define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF 0x0 | ||
| 66 | #define BV_LRADC_CTRL0_XMINUS_ENABLE__ON 0x1 | ||
| 67 | #define BF_LRADC_CTRL0_XMINUS_ENABLE(v) (((v) << 18) & 0x40000) | ||
| 68 | #define BF_LRADC_CTRL0_XMINUS_ENABLE_V(v) ((BV_LRADC_CTRL0_XMINUS_ENABLE__##v << 18) & 0x40000) | ||
| 69 | #define BP_LRADC_CTRL0_YPLUS_ENABLE 17 | ||
| 70 | #define BM_LRADC_CTRL0_YPLUS_ENABLE 0x20000 | ||
| 71 | #define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF 0x0 | ||
| 72 | #define BV_LRADC_CTRL0_YPLUS_ENABLE__ON 0x1 | ||
| 73 | #define BF_LRADC_CTRL0_YPLUS_ENABLE(v) (((v) << 17) & 0x20000) | ||
| 74 | #define BF_LRADC_CTRL0_YPLUS_ENABLE_V(v) ((BV_LRADC_CTRL0_YPLUS_ENABLE__##v << 17) & 0x20000) | ||
| 75 | #define BP_LRADC_CTRL0_XPLUS_ENABLE 16 | ||
| 76 | #define BM_LRADC_CTRL0_XPLUS_ENABLE 0x10000 | ||
| 77 | #define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF 0x0 | ||
| 78 | #define BV_LRADC_CTRL0_XPLUS_ENABLE__ON 0x1 | ||
| 79 | #define BF_LRADC_CTRL0_XPLUS_ENABLE(v) (((v) << 16) & 0x10000) | ||
| 80 | #define BF_LRADC_CTRL0_XPLUS_ENABLE_V(v) ((BV_LRADC_CTRL0_XPLUS_ENABLE__##v << 16) & 0x10000) | ||
| 81 | #define BP_LRADC_CTRL0_SCHEDULE 0 | ||
| 82 | #define BM_LRADC_CTRL0_SCHEDULE 0xff | ||
| 83 | #define BF_LRADC_CTRL0_SCHEDULE(v) (((v) << 0) & 0xff) | ||
| 84 | |||
| 85 | /** | ||
| 86 | * Register: HW_LRADC_CTRL1 | ||
| 87 | * Address: 0x10 | ||
| 88 | * SCT: yes | ||
| 89 | */ | ||
| 90 | #define HW_LRADC_CTRL1 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x0)) | ||
| 91 | #define HW_LRADC_CTRL1_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x4)) | ||
| 92 | #define HW_LRADC_CTRL1_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x8)) | ||
| 93 | #define HW_LRADC_CTRL1_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0xc)) | ||
| 94 | #define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 24 | ||
| 95 | #define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x1000000 | ||
| 96 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0 | ||
| 97 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE 0x1 | ||
| 98 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v) (((v) << 24) & 0x1000000) | ||
| 99 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v) ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##v << 24) & 0x1000000) | ||
| 100 | #define BP_LRADC_CTRL1_LRADC7_IRQ_EN 23 | ||
| 101 | #define BM_LRADC_CTRL1_LRADC7_IRQ_EN 0x800000 | ||
| 102 | #define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE 0x0 | ||
| 103 | #define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE 0x1 | ||
| 104 | #define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v) (((v) << 23) & 0x800000) | ||
| 105 | #define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC7_IRQ_EN__##v << 23) & 0x800000) | ||
| 106 | #define BP_LRADC_CTRL1_LRADC6_IRQ_EN 22 | ||
| 107 | #define BM_LRADC_CTRL1_LRADC6_IRQ_EN 0x400000 | ||
| 108 | #define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE 0x0 | ||
| 109 | #define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE 0x1 | ||
| 110 | #define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
| 111 | #define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC6_IRQ_EN__##v << 22) & 0x400000) | ||
| 112 | #define BP_LRADC_CTRL1_LRADC5_IRQ_EN 21 | ||
| 113 | #define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x200000 | ||
| 114 | #define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE 0x0 | ||
| 115 | #define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE 0x1 | ||
| 116 | #define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v) (((v) << 21) & 0x200000) | ||
| 117 | #define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC5_IRQ_EN__##v << 21) & 0x200000) | ||
| 118 | #define BP_LRADC_CTRL1_LRADC4_IRQ_EN 20 | ||
| 119 | #define BM_LRADC_CTRL1_LRADC4_IRQ_EN 0x100000 | ||
| 120 | #define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE 0x0 | ||
| 121 | #define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE 0x1 | ||
| 122 | #define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v) (((v) << 20) & 0x100000) | ||
| 123 | #define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC4_IRQ_EN__##v << 20) & 0x100000) | ||
| 124 | #define BP_LRADC_CTRL1_LRADC3_IRQ_EN 19 | ||
| 125 | #define BM_LRADC_CTRL1_LRADC3_IRQ_EN 0x80000 | ||
| 126 | #define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE 0x0 | ||
| 127 | #define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE 0x1 | ||
| 128 | #define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v) (((v) << 19) & 0x80000) | ||
| 129 | #define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC3_IRQ_EN__##v << 19) & 0x80000) | ||
| 130 | #define BP_LRADC_CTRL1_LRADC2_IRQ_EN 18 | ||
| 131 | #define BM_LRADC_CTRL1_LRADC2_IRQ_EN 0x40000 | ||
| 132 | #define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE 0x0 | ||
| 133 | #define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE 0x1 | ||
| 134 | #define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
| 135 | #define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC2_IRQ_EN__##v << 18) & 0x40000) | ||
| 136 | #define BP_LRADC_CTRL1_LRADC1_IRQ_EN 17 | ||
| 137 | #define BM_LRADC_CTRL1_LRADC1_IRQ_EN 0x20000 | ||
| 138 | #define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE 0x0 | ||
| 139 | #define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE 0x1 | ||
| 140 | #define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v) (((v) << 17) & 0x20000) | ||
| 141 | #define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC1_IRQ_EN__##v << 17) & 0x20000) | ||
| 142 | #define BP_LRADC_CTRL1_LRADC0_IRQ_EN 16 | ||
| 143 | #define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x10000 | ||
| 144 | #define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE 0x0 | ||
| 145 | #define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE 0x1 | ||
| 146 | #define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
| 147 | #define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC0_IRQ_EN__##v << 16) & 0x10000) | ||
| 148 | #define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ 8 | ||
| 149 | #define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x100 | ||
| 150 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR 0x0 | ||
| 151 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING 0x1 | ||
| 152 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v) (((v) << 8) & 0x100) | ||
| 153 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v) ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##v << 8) & 0x100) | ||
| 154 | #define BP_LRADC_CTRL1_LRADC7_IRQ 7 | ||
| 155 | #define BM_LRADC_CTRL1_LRADC7_IRQ 0x80 | ||
| 156 | #define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR 0x0 | ||
| 157 | #define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING 0x1 | ||
| 158 | #define BF_LRADC_CTRL1_LRADC7_IRQ(v) (((v) << 7) & 0x80) | ||
| 159 | #define BF_LRADC_CTRL1_LRADC7_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC7_IRQ__##v << 7) & 0x80) | ||
| 160 | #define BP_LRADC_CTRL1_LRADC6_IRQ 6 | ||
| 161 | #define BM_LRADC_CTRL1_LRADC6_IRQ 0x40 | ||
| 162 | #define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR 0x0 | ||
| 163 | #define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING 0x1 | ||
| 164 | #define BF_LRADC_CTRL1_LRADC6_IRQ(v) (((v) << 6) & 0x40) | ||
| 165 | #define BF_LRADC_CTRL1_LRADC6_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC6_IRQ__##v << 6) & 0x40) | ||
| 166 | #define BP_LRADC_CTRL1_LRADC5_IRQ 5 | ||
| 167 | #define BM_LRADC_CTRL1_LRADC5_IRQ 0x20 | ||
| 168 | #define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR 0x0 | ||
| 169 | #define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING 0x1 | ||
| 170 | #define BF_LRADC_CTRL1_LRADC5_IRQ(v) (((v) << 5) & 0x20) | ||
| 171 | #define BF_LRADC_CTRL1_LRADC5_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC5_IRQ__##v << 5) & 0x20) | ||
| 172 | #define BP_LRADC_CTRL1_LRADC4_IRQ 4 | ||
| 173 | #define BM_LRADC_CTRL1_LRADC4_IRQ 0x10 | ||
| 174 | #define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR 0x0 | ||
| 175 | #define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING 0x1 | ||
| 176 | #define BF_LRADC_CTRL1_LRADC4_IRQ(v) (((v) << 4) & 0x10) | ||
| 177 | #define BF_LRADC_CTRL1_LRADC4_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC4_IRQ__##v << 4) & 0x10) | ||
| 178 | #define BP_LRADC_CTRL1_LRADC3_IRQ 3 | ||
| 179 | #define BM_LRADC_CTRL1_LRADC3_IRQ 0x8 | ||
| 180 | #define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR 0x0 | ||
| 181 | #define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING 0x1 | ||
| 182 | #define BF_LRADC_CTRL1_LRADC3_IRQ(v) (((v) << 3) & 0x8) | ||
| 183 | #define BF_LRADC_CTRL1_LRADC3_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC3_IRQ__##v << 3) & 0x8) | ||
| 184 | #define BP_LRADC_CTRL1_LRADC2_IRQ 2 | ||
| 185 | #define BM_LRADC_CTRL1_LRADC2_IRQ 0x4 | ||
| 186 | #define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR 0x0 | ||
| 187 | #define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING 0x1 | ||
| 188 | #define BF_LRADC_CTRL1_LRADC2_IRQ(v) (((v) << 2) & 0x4) | ||
| 189 | #define BF_LRADC_CTRL1_LRADC2_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC2_IRQ__##v << 2) & 0x4) | ||
| 190 | #define BP_LRADC_CTRL1_LRADC1_IRQ 1 | ||
| 191 | #define BM_LRADC_CTRL1_LRADC1_IRQ 0x2 | ||
| 192 | #define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR 0x0 | ||
| 193 | #define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING 0x1 | ||
| 194 | #define BF_LRADC_CTRL1_LRADC1_IRQ(v) (((v) << 1) & 0x2) | ||
| 195 | #define BF_LRADC_CTRL1_LRADC1_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC1_IRQ__##v << 1) & 0x2) | ||
| 196 | #define BP_LRADC_CTRL1_LRADC0_IRQ 0 | ||
| 197 | #define BM_LRADC_CTRL1_LRADC0_IRQ 0x1 | ||
| 198 | #define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR 0x0 | ||
| 199 | #define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING 0x1 | ||
| 200 | #define BF_LRADC_CTRL1_LRADC0_IRQ(v) (((v) << 0) & 0x1) | ||
| 201 | #define BF_LRADC_CTRL1_LRADC0_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC0_IRQ__##v << 0) & 0x1) | ||
| 202 | |||
| 203 | /** | ||
| 204 | * Register: HW_LRADC_CTRL2 | ||
| 205 | * Address: 0x20 | ||
| 206 | * SCT: yes | ||
| 207 | */ | ||
| 208 | #define HW_LRADC_CTRL2 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x0)) | ||
| 209 | #define HW_LRADC_CTRL2_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x4)) | ||
| 210 | #define HW_LRADC_CTRL2_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x8)) | ||
| 211 | #define HW_LRADC_CTRL2_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0xc)) | ||
| 212 | #define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 | ||
| 213 | #define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xff000000 | ||
| 214 | #define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v) (((v) << 24) & 0xff000000) | ||
| 215 | #define BP_LRADC_CTRL2_LRADC6SELECT 20 | ||
| 216 | #define BM_LRADC_CTRL2_LRADC6SELECT 0xf00000 | ||
| 217 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL0 0x0 | ||
| 218 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL1 0x1 | ||
| 219 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL2 0x2 | ||
| 220 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL3 0x3 | ||
| 221 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL4 0x4 | ||
| 222 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL5 0x5 | ||
| 223 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL6 0x6 | ||
| 224 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL7 0x7 | ||
| 225 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL8 0x8 | ||
| 226 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL9 0x9 | ||
| 227 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL10 0xa | ||
| 228 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL11 0xb | ||
| 229 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL12 0xc | ||
| 230 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL13 0xd | ||
| 231 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL14 0xe | ||
| 232 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL15 0xf | ||
| 233 | #define BF_LRADC_CTRL2_LRADC6SELECT(v) (((v) << 20) & 0xf00000) | ||
| 234 | #define BF_LRADC_CTRL2_LRADC6SELECT_V(v) ((BV_LRADC_CTRL2_LRADC6SELECT__##v << 20) & 0xf00000) | ||
| 235 | #define BP_LRADC_CTRL2_LRADC7SELECT 16 | ||
| 236 | #define BM_LRADC_CTRL2_LRADC7SELECT 0xf0000 | ||
| 237 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL0 0x0 | ||
| 238 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL1 0x1 | ||
| 239 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL2 0x2 | ||
| 240 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL3 0x3 | ||
| 241 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL4 0x4 | ||
| 242 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL5 0x5 | ||
| 243 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL6 0x6 | ||
| 244 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL7 0x7 | ||
| 245 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL8 0x8 | ||
| 246 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL9 0x9 | ||
| 247 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL10 0xa | ||
| 248 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL11 0xb | ||
| 249 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL12 0xc | ||
| 250 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL13 0xd | ||
| 251 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL14 0xe | ||
| 252 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL15 0xf | ||
| 253 | #define BF_LRADC_CTRL2_LRADC7SELECT(v) (((v) << 16) & 0xf0000) | ||
| 254 | #define BF_LRADC_CTRL2_LRADC7SELECT_V(v) ((BV_LRADC_CTRL2_LRADC7SELECT__##v << 16) & 0xf0000) | ||
| 255 | #define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 9 | ||
| 256 | #define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 0x200 | ||
| 257 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0 | ||
| 258 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1 | ||
| 259 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v) (((v) << 9) & 0x200) | ||
| 260 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v) ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##v << 9) & 0x200) | ||
| 261 | #define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 8 | ||
| 262 | #define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 0x100 | ||
| 263 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0 | ||
| 264 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1 | ||
| 265 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v) (((v) << 8) & 0x100) | ||
| 266 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v) ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##v << 8) & 0x100) | ||
| 267 | #define BP_LRADC_CTRL2_TEMP_ISRC1 4 | ||
| 268 | #define BM_LRADC_CTRL2_TEMP_ISRC1 0xf0 | ||
| 269 | #define BV_LRADC_CTRL2_TEMP_ISRC1__300 0xf | ||
| 270 | #define BV_LRADC_CTRL2_TEMP_ISRC1__280 0xe | ||
| 271 | #define BV_LRADC_CTRL2_TEMP_ISRC1__260 0xd | ||
| 272 | #define BV_LRADC_CTRL2_TEMP_ISRC1__240 0xc | ||
| 273 | #define BV_LRADC_CTRL2_TEMP_ISRC1__220 0xb | ||
| 274 | #define BV_LRADC_CTRL2_TEMP_ISRC1__200 0xa | ||
| 275 | #define BV_LRADC_CTRL2_TEMP_ISRC1__180 0x9 | ||
| 276 | #define BV_LRADC_CTRL2_TEMP_ISRC1__160 0x8 | ||
| 277 | #define BV_LRADC_CTRL2_TEMP_ISRC1__140 0x7 | ||
| 278 | #define BV_LRADC_CTRL2_TEMP_ISRC1__120 0x6 | ||
| 279 | #define BV_LRADC_CTRL2_TEMP_ISRC1__100 0x5 | ||
| 280 | #define BV_LRADC_CTRL2_TEMP_ISRC1__80 0x4 | ||
| 281 | #define BV_LRADC_CTRL2_TEMP_ISRC1__60 0x3 | ||
| 282 | #define BV_LRADC_CTRL2_TEMP_ISRC1__40 0x2 | ||
| 283 | #define BV_LRADC_CTRL2_TEMP_ISRC1__20 0x1 | ||
| 284 | #define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO 0x0 | ||
| 285 | #define BF_LRADC_CTRL2_TEMP_ISRC1(v) (((v) << 4) & 0xf0) | ||
| 286 | #define BF_LRADC_CTRL2_TEMP_ISRC1_V(v) ((BV_LRADC_CTRL2_TEMP_ISRC1__##v << 4) & 0xf0) | ||
| 287 | #define BP_LRADC_CTRL2_TEMP_ISRC0 0 | ||
| 288 | #define BM_LRADC_CTRL2_TEMP_ISRC0 0xf | ||
| 289 | #define BV_LRADC_CTRL2_TEMP_ISRC0__300 0xf | ||
| 290 | #define BV_LRADC_CTRL2_TEMP_ISRC0__280 0xe | ||
| 291 | #define BV_LRADC_CTRL2_TEMP_ISRC0__260 0xd | ||
| 292 | #define BV_LRADC_CTRL2_TEMP_ISRC0__240 0xc | ||
| 293 | #define BV_LRADC_CTRL2_TEMP_ISRC0__220 0xb | ||
| 294 | #define BV_LRADC_CTRL2_TEMP_ISRC0__200 0xa | ||
| 295 | #define BV_LRADC_CTRL2_TEMP_ISRC0__180 0x9 | ||
| 296 | #define BV_LRADC_CTRL2_TEMP_ISRC0__160 0x8 | ||
| 297 | #define BV_LRADC_CTRL2_TEMP_ISRC0__140 0x7 | ||
| 298 | #define BV_LRADC_CTRL2_TEMP_ISRC0__120 0x6 | ||
| 299 | #define BV_LRADC_CTRL2_TEMP_ISRC0__100 0x5 | ||
| 300 | #define BV_LRADC_CTRL2_TEMP_ISRC0__80 0x4 | ||
| 301 | #define BV_LRADC_CTRL2_TEMP_ISRC0__60 0x3 | ||
| 302 | #define BV_LRADC_CTRL2_TEMP_ISRC0__40 0x2 | ||
| 303 | #define BV_LRADC_CTRL2_TEMP_ISRC0__20 0x1 | ||
| 304 | #define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO 0x0 | ||
| 305 | #define BF_LRADC_CTRL2_TEMP_ISRC0(v) (((v) << 0) & 0xf) | ||
| 306 | #define BF_LRADC_CTRL2_TEMP_ISRC0_V(v) ((BV_LRADC_CTRL2_TEMP_ISRC0__##v << 0) & 0xf) | ||
| 307 | |||
| 308 | /** | ||
| 309 | * Register: HW_LRADC_CTRL3 | ||
| 310 | * Address: 0x30 | ||
| 311 | * SCT: yes | ||
| 312 | */ | ||
| 313 | #define HW_LRADC_CTRL3 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x0)) | ||
| 314 | #define HW_LRADC_CTRL3_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x4)) | ||
| 315 | #define HW_LRADC_CTRL3_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x8)) | ||
| 316 | #define HW_LRADC_CTRL3_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0xc)) | ||
| 317 | #define BP_LRADC_CTRL3_DISCARD 24 | ||
| 318 | #define BM_LRADC_CTRL3_DISCARD 0x3000000 | ||
| 319 | #define BV_LRADC_CTRL3_DISCARD__1_SAMPLE 0x1 | ||
| 320 | #define BV_LRADC_CTRL3_DISCARD__2_SAMPLES 0x2 | ||
| 321 | #define BV_LRADC_CTRL3_DISCARD__3_SAMPLES 0x3 | ||
| 322 | #define BF_LRADC_CTRL3_DISCARD(v) (((v) << 24) & 0x3000000) | ||
| 323 | #define BF_LRADC_CTRL3_DISCARD_V(v) ((BV_LRADC_CTRL3_DISCARD__##v << 24) & 0x3000000) | ||
| 324 | #define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP 23 | ||
| 325 | #define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP 0x800000 | ||
| 326 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF 0x0 | ||
| 327 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON 0x1 | ||
| 328 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v) (((v) << 23) & 0x800000) | ||
| 329 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v) ((BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##v << 23) & 0x800000) | ||
| 330 | #define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN 22 | ||
| 331 | #define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN 0x400000 | ||
| 332 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON 0x0 | ||
| 333 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF 0x1 | ||
| 334 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v) (((v) << 22) & 0x400000) | ||
| 335 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v) ((BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##v << 22) & 0x400000) | ||
| 336 | #define BP_LRADC_CTRL3_FORCE_PWD40UA_PWUP 21 | ||
| 337 | #define BM_LRADC_CTRL3_FORCE_PWD40UA_PWUP 0x200000 | ||
| 338 | #define BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__OFF 0x0 | ||
| 339 | #define BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__ON 0x1 | ||
| 340 | #define BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP(v) (((v) << 21) & 0x200000) | ||
| 341 | #define BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP_V(v) ((BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__##v << 21) & 0x200000) | ||
| 342 | #define BP_LRADC_CTRL3_FORCE_PWD40UA_PWDN 20 | ||
| 343 | #define BM_LRADC_CTRL3_FORCE_PWD40UA_PWDN 0x100000 | ||
| 344 | #define BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__ON 0x0 | ||
| 345 | #define BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__OFF 0x1 | ||
| 346 | #define BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN(v) (((v) << 20) & 0x100000) | ||
| 347 | #define BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN_V(v) ((BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__##v << 20) & 0x100000) | ||
| 348 | #define BP_LRADC_CTRL3_VDD_FILTER 16 | ||
| 349 | #define BM_LRADC_CTRL3_VDD_FILTER 0x30000 | ||
| 350 | #define BV_LRADC_CTRL3_VDD_FILTER__0OHMS 0x0 | ||
| 351 | #define BV_LRADC_CTRL3_VDD_FILTER__100OHMS 0x1 | ||
| 352 | #define BV_LRADC_CTRL3_VDD_FILTER__250OHMS 0x2 | ||
| 353 | #define BV_LRADC_CTRL3_VDD_FILTER__5000OHMS 0x3 | ||
| 354 | #define BF_LRADC_CTRL3_VDD_FILTER(v) (((v) << 16) & 0x30000) | ||
| 355 | #define BF_LRADC_CTRL3_VDD_FILTER_V(v) ((BV_LRADC_CTRL3_VDD_FILTER__##v << 16) & 0x30000) | ||
| 356 | #define BP_LRADC_CTRL3_ADD_CAP2INPUTS 12 | ||
| 357 | #define BM_LRADC_CTRL3_ADD_CAP2INPUTS 0x3000 | ||
| 358 | #define BV_LRADC_CTRL3_ADD_CAP2INPUTS__0PF 0x0 | ||
| 359 | #define BV_LRADC_CTRL3_ADD_CAP2INPUTS__0_5PF 0x1 | ||
| 360 | #define BV_LRADC_CTRL3_ADD_CAP2INPUTS__1_0PF 0x2 | ||
| 361 | #define BV_LRADC_CTRL3_ADD_CAP2INPUTS__2_5PF 0x3 | ||
| 362 | #define BF_LRADC_CTRL3_ADD_CAP2INPUTS(v) (((v) << 12) & 0x3000) | ||
| 363 | #define BF_LRADC_CTRL3_ADD_CAP2INPUTS_V(v) ((BV_LRADC_CTRL3_ADD_CAP2INPUTS__##v << 12) & 0x3000) | ||
| 364 | #define BP_LRADC_CTRL3_CYCLE_TIME 8 | ||
| 365 | #define BM_LRADC_CTRL3_CYCLE_TIME 0x300 | ||
| 366 | #define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ 0x0 | ||
| 367 | #define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ 0x1 | ||
| 368 | #define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ 0x2 | ||
| 369 | #define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ 0x3 | ||
| 370 | #define BF_LRADC_CTRL3_CYCLE_TIME(v) (((v) << 8) & 0x300) | ||
| 371 | #define BF_LRADC_CTRL3_CYCLE_TIME_V(v) ((BV_LRADC_CTRL3_CYCLE_TIME__##v << 8) & 0x300) | ||
| 372 | #define BP_LRADC_CTRL3_HIGH_TIME 4 | ||
| 373 | #define BM_LRADC_CTRL3_HIGH_TIME 0x30 | ||
| 374 | #define BV_LRADC_CTRL3_HIGH_TIME__42NS 0x0 | ||
| 375 | #define BV_LRADC_CTRL3_HIGH_TIME__83NS 0x1 | ||
| 376 | #define BV_LRADC_CTRL3_HIGH_TIME__125NS 0x2 | ||
| 377 | #define BV_LRADC_CTRL3_HIGH_TIME__250NS 0x3 | ||
| 378 | #define BF_LRADC_CTRL3_HIGH_TIME(v) (((v) << 4) & 0x30) | ||
| 379 | #define BF_LRADC_CTRL3_HIGH_TIME_V(v) ((BV_LRADC_CTRL3_HIGH_TIME__##v << 4) & 0x30) | ||
| 380 | #define BP_LRADC_CTRL3_REMOVE_CFILT 3 | ||
| 381 | #define BM_LRADC_CTRL3_REMOVE_CFILT 0x8 | ||
| 382 | #define BV_LRADC_CTRL3_REMOVE_CFILT__OFF 0x0 | ||
| 383 | #define BV_LRADC_CTRL3_REMOVE_CFILT__ON 0x1 | ||
| 384 | #define BF_LRADC_CTRL3_REMOVE_CFILT(v) (((v) << 3) & 0x8) | ||
| 385 | #define BF_LRADC_CTRL3_REMOVE_CFILT_V(v) ((BV_LRADC_CTRL3_REMOVE_CFILT__##v << 3) & 0x8) | ||
| 386 | #define BP_LRADC_CTRL3_SHORT_RFILT 2 | ||
| 387 | #define BM_LRADC_CTRL3_SHORT_RFILT 0x4 | ||
| 388 | #define BV_LRADC_CTRL3_SHORT_RFILT__OFF 0x0 | ||
| 389 | #define BV_LRADC_CTRL3_SHORT_RFILT__ON 0x1 | ||
| 390 | #define BF_LRADC_CTRL3_SHORT_RFILT(v) (((v) << 2) & 0x4) | ||
| 391 | #define BF_LRADC_CTRL3_SHORT_RFILT_V(v) ((BV_LRADC_CTRL3_SHORT_RFILT__##v << 2) & 0x4) | ||
| 392 | #define BP_LRADC_CTRL3_DELAY_CLOCK 1 | ||
| 393 | #define BM_LRADC_CTRL3_DELAY_CLOCK 0x2 | ||
| 394 | #define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL 0x0 | ||
| 395 | #define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED 0x1 | ||
| 396 | #define BF_LRADC_CTRL3_DELAY_CLOCK(v) (((v) << 1) & 0x2) | ||
| 397 | #define BF_LRADC_CTRL3_DELAY_CLOCK_V(v) ((BV_LRADC_CTRL3_DELAY_CLOCK__##v << 1) & 0x2) | ||
| 398 | #define BP_LRADC_CTRL3_INVERT_CLOCK 0 | ||
| 399 | #define BM_LRADC_CTRL3_INVERT_CLOCK 0x1 | ||
| 400 | #define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL 0x0 | ||
| 401 | #define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT 0x1 | ||
| 402 | #define BF_LRADC_CTRL3_INVERT_CLOCK(v) (((v) << 0) & 0x1) | ||
| 403 | #define BF_LRADC_CTRL3_INVERT_CLOCK_V(v) ((BV_LRADC_CTRL3_INVERT_CLOCK__##v << 0) & 0x1) | ||
| 404 | |||
| 405 | /** | ||
| 406 | * Register: HW_LRADC_STATUS | ||
| 407 | * Address: 0x40 | ||
| 408 | * SCT: no | ||
| 409 | */ | ||
| 410 | #define HW_LRADC_STATUS (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40)) | ||
| 411 | #define BP_LRADC_STATUS_TEMP1_PRESENT 26 | ||
| 412 | #define BM_LRADC_STATUS_TEMP1_PRESENT 0x4000000 | ||
| 413 | #define BF_LRADC_STATUS_TEMP1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
| 414 | #define BP_LRADC_STATUS_TEMP0_PRESENT 25 | ||
| 415 | #define BM_LRADC_STATUS_TEMP0_PRESENT 0x2000000 | ||
| 416 | #define BF_LRADC_STATUS_TEMP0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
| 417 | #define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT 24 | ||
| 418 | #define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT 0x1000000 | ||
| 419 | #define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v) (((v) << 24) & 0x1000000) | ||
| 420 | #define BP_LRADC_STATUS_CHANNEL7_PRESENT 23 | ||
| 421 | #define BM_LRADC_STATUS_CHANNEL7_PRESENT 0x800000 | ||
| 422 | #define BF_LRADC_STATUS_CHANNEL7_PRESENT(v) (((v) << 23) & 0x800000) | ||
| 423 | #define BP_LRADC_STATUS_CHANNEL6_PRESENT 22 | ||
| 424 | #define BM_LRADC_STATUS_CHANNEL6_PRESENT 0x400000 | ||
| 425 | #define BF_LRADC_STATUS_CHANNEL6_PRESENT(v) (((v) << 22) & 0x400000) | ||
| 426 | #define BP_LRADC_STATUS_CHANNEL5_PRESENT 21 | ||
| 427 | #define BM_LRADC_STATUS_CHANNEL5_PRESENT 0x200000 | ||
| 428 | #define BF_LRADC_STATUS_CHANNEL5_PRESENT(v) (((v) << 21) & 0x200000) | ||
| 429 | #define BP_LRADC_STATUS_CHANNEL4_PRESENT 20 | ||
| 430 | #define BM_LRADC_STATUS_CHANNEL4_PRESENT 0x100000 | ||
| 431 | #define BF_LRADC_STATUS_CHANNEL4_PRESENT(v) (((v) << 20) & 0x100000) | ||
| 432 | #define BP_LRADC_STATUS_CHANNEL3_PRESENT 19 | ||
| 433 | #define BM_LRADC_STATUS_CHANNEL3_PRESENT 0x80000 | ||
| 434 | #define BF_LRADC_STATUS_CHANNEL3_PRESENT(v) (((v) << 19) & 0x80000) | ||
| 435 | #define BP_LRADC_STATUS_CHANNEL2_PRESENT 18 | ||
| 436 | #define BM_LRADC_STATUS_CHANNEL2_PRESENT 0x40000 | ||
| 437 | #define BF_LRADC_STATUS_CHANNEL2_PRESENT(v) (((v) << 18) & 0x40000) | ||
| 438 | #define BP_LRADC_STATUS_CHANNEL1_PRESENT 17 | ||
| 439 | #define BM_LRADC_STATUS_CHANNEL1_PRESENT 0x20000 | ||
| 440 | #define BF_LRADC_STATUS_CHANNEL1_PRESENT(v) (((v) << 17) & 0x20000) | ||
| 441 | #define BP_LRADC_STATUS_CHANNEL0_PRESENT 16 | ||
| 442 | #define BM_LRADC_STATUS_CHANNEL0_PRESENT 0x10000 | ||
| 443 | #define BF_LRADC_STATUS_CHANNEL0_PRESENT(v) (((v) << 16) & 0x10000) | ||
| 444 | #define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0 | ||
| 445 | #define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x1 | ||
| 446 | #define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN 0x0 | ||
| 447 | #define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT 0x1 | ||
| 448 | #define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v) (((v) << 0) & 0x1) | ||
| 449 | #define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(v) ((BV_LRADC_STATUS_TOUCH_DETECT_RAW__##v << 0) & 0x1) | ||
| 450 | |||
| 451 | /** | ||
| 452 | * Register: HW_LRADC_DEBUG0 | ||
| 453 | * Address: 0x110 | ||
| 454 | * SCT: no | ||
| 455 | */ | ||
| 456 | #define HW_LRADC_DEBUG0 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110)) | ||
| 457 | #define BP_LRADC_DEBUG0_READONLY 16 | ||
| 458 | #define BM_LRADC_DEBUG0_READONLY 0xffff0000 | ||
| 459 | #define BF_LRADC_DEBUG0_READONLY(v) (((v) << 16) & 0xffff0000) | ||
| 460 | #define BP_LRADC_DEBUG0_STATE 0 | ||
| 461 | #define BM_LRADC_DEBUG0_STATE 0xfff | ||
| 462 | #define BF_LRADC_DEBUG0_STATE(v) (((v) << 0) & 0xfff) | ||
| 463 | |||
| 464 | /** | ||
| 465 | * Register: HW_LRADC_DEBUG1 | ||
| 466 | * Address: 0x120 | ||
| 467 | * SCT: yes | ||
| 468 | */ | ||
| 469 | #define HW_LRADC_DEBUG1 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x0)) | ||
| 470 | #define HW_LRADC_DEBUG1_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x4)) | ||
| 471 | #define HW_LRADC_DEBUG1_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x8)) | ||
| 472 | #define HW_LRADC_DEBUG1_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0xc)) | ||
| 473 | #define BP_LRADC_DEBUG1_REQUEST 16 | ||
| 474 | #define BM_LRADC_DEBUG1_REQUEST 0xff0000 | ||
| 475 | #define BF_LRADC_DEBUG1_REQUEST(v) (((v) << 16) & 0xff0000) | ||
| 476 | #define BP_LRADC_DEBUG1_TESTMODE_COUNT 8 | ||
| 477 | #define BM_LRADC_DEBUG1_TESTMODE_COUNT 0x1f00 | ||
| 478 | #define BF_LRADC_DEBUG1_TESTMODE_COUNT(v) (((v) << 8) & 0x1f00) | ||
| 479 | #define BP_LRADC_DEBUG1_TESTMODE6 2 | ||
| 480 | #define BM_LRADC_DEBUG1_TESTMODE6 0x4 | ||
| 481 | #define BV_LRADC_DEBUG1_TESTMODE6__NORMAL 0x0 | ||
| 482 | #define BV_LRADC_DEBUG1_TESTMODE6__TEST 0x1 | ||
| 483 | #define BF_LRADC_DEBUG1_TESTMODE6(v) (((v) << 2) & 0x4) | ||
| 484 | #define BF_LRADC_DEBUG1_TESTMODE6_V(v) ((BV_LRADC_DEBUG1_TESTMODE6__##v << 2) & 0x4) | ||
| 485 | #define BP_LRADC_DEBUG1_TESTMODE5 1 | ||
| 486 | #define BM_LRADC_DEBUG1_TESTMODE5 0x2 | ||
| 487 | #define BV_LRADC_DEBUG1_TESTMODE5__NORMAL 0x0 | ||
| 488 | #define BV_LRADC_DEBUG1_TESTMODE5__TEST 0x1 | ||
| 489 | #define BF_LRADC_DEBUG1_TESTMODE5(v) (((v) << 1) & 0x2) | ||
| 490 | #define BF_LRADC_DEBUG1_TESTMODE5_V(v) ((BV_LRADC_DEBUG1_TESTMODE5__##v << 1) & 0x2) | ||
| 491 | #define BP_LRADC_DEBUG1_TESTMODE 0 | ||
| 492 | #define BM_LRADC_DEBUG1_TESTMODE 0x1 | ||
| 493 | #define BV_LRADC_DEBUG1_TESTMODE__NORMAL 0x0 | ||
| 494 | #define BV_LRADC_DEBUG1_TESTMODE__TEST 0x1 | ||
| 495 | #define BF_LRADC_DEBUG1_TESTMODE(v) (((v) << 0) & 0x1) | ||
| 496 | #define BF_LRADC_DEBUG1_TESTMODE_V(v) ((BV_LRADC_DEBUG1_TESTMODE__##v << 0) & 0x1) | ||
| 497 | |||
| 498 | /** | ||
| 499 | * Register: HW_LRADC_CONVERSION | ||
| 500 | * Address: 0x130 | ||
| 501 | * SCT: yes | ||
| 502 | */ | ||
| 503 | #define HW_LRADC_CONVERSION (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x0)) | ||
| 504 | #define HW_LRADC_CONVERSION_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x4)) | ||
| 505 | #define HW_LRADC_CONVERSION_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x8)) | ||
| 506 | #define HW_LRADC_CONVERSION_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0xc)) | ||
| 507 | #define BP_LRADC_CONVERSION_AUTOMATIC 20 | ||
| 508 | #define BM_LRADC_CONVERSION_AUTOMATIC 0x100000 | ||
| 509 | #define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE 0x0 | ||
| 510 | #define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE 0x1 | ||
| 511 | #define BF_LRADC_CONVERSION_AUTOMATIC(v) (((v) << 20) & 0x100000) | ||
| 512 | #define BF_LRADC_CONVERSION_AUTOMATIC_V(v) ((BV_LRADC_CONVERSION_AUTOMATIC__##v << 20) & 0x100000) | ||
| 513 | #define BP_LRADC_CONVERSION_SCALE_FACTOR 16 | ||
| 514 | #define BM_LRADC_CONVERSION_SCALE_FACTOR 0x30000 | ||
| 515 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH 0x0 | ||
| 516 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1 | ||
| 517 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION 0x2 | ||
| 518 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3 | ||
| 519 | #define BF_LRADC_CONVERSION_SCALE_FACTOR(v) (((v) << 16) & 0x30000) | ||
| 520 | #define BF_LRADC_CONVERSION_SCALE_FACTOR_V(v) ((BV_LRADC_CONVERSION_SCALE_FACTOR__##v << 16) & 0x30000) | ||
| 521 | #define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0 | ||
| 522 | #define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0x3ff | ||
| 523 | #define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) (((v) << 0) & 0x3ff) | ||
| 524 | |||
| 525 | /** | ||
| 526 | * Register: HW_LRADC_DELAYn | ||
| 527 | * Address: 0xd0+n*0x10 | ||
| 528 | * SCT: yes | ||
| 529 | */ | ||
| 530 | #define HW_LRADC_DELAYn(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x0)) | ||
| 531 | #define HW_LRADC_DELAYn_SET(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x4)) | ||
| 532 | #define HW_LRADC_DELAYn_CLR(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x8)) | ||
| 533 | #define HW_LRADC_DELAYn_TOG(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0xc)) | ||
| 534 | #define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 | ||
| 535 | #define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xff000000 | ||
| 536 | #define BF_LRADC_DELAYn_TRIGGER_LRADCS(v) (((v) << 24) & 0xff000000) | ||
| 537 | #define BP_LRADC_DELAYn_KICK 20 | ||
| 538 | #define BM_LRADC_DELAYn_KICK 0x100000 | ||
| 539 | #define BF_LRADC_DELAYn_KICK(v) (((v) << 20) & 0x100000) | ||
| 540 | #define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 | ||
| 541 | #define BM_LRADC_DELAYn_TRIGGER_DELAYS 0xf0000 | ||
| 542 | #define BF_LRADC_DELAYn_TRIGGER_DELAYS(v) (((v) << 16) & 0xf0000) | ||
| 543 | #define BP_LRADC_DELAYn_LOOP_COUNT 11 | ||
| 544 | #define BM_LRADC_DELAYn_LOOP_COUNT 0xf800 | ||
| 545 | #define BF_LRADC_DELAYn_LOOP_COUNT(v) (((v) << 11) & 0xf800) | ||
| 546 | #define BP_LRADC_DELAYn_DELAY 0 | ||
| 547 | #define BM_LRADC_DELAYn_DELAY 0x7ff | ||
| 548 | #define BF_LRADC_DELAYn_DELAY(v) (((v) << 0) & 0x7ff) | ||
| 549 | |||
| 550 | /** | ||
| 551 | * Register: HW_LRADC_CHn | ||
| 552 | * Address: 0x50+n*0x10 | ||
| 553 | * SCT: yes | ||
| 554 | */ | ||
| 555 | #define HW_LRADC_CHn(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x0)) | ||
| 556 | #define HW_LRADC_CHn_SET(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x4)) | ||
| 557 | #define HW_LRADC_CHn_CLR(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x8)) | ||
| 558 | #define HW_LRADC_CHn_TOG(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0xc)) | ||
| 559 | #define BP_LRADC_CHn_TOGGLE 31 | ||
| 560 | #define BM_LRADC_CHn_TOGGLE 0x80000000 | ||
| 561 | #define BF_LRADC_CHn_TOGGLE(v) (((v) << 31) & 0x80000000) | ||
| 562 | #define BP_LRADC_CHn_ACCUMULATE 29 | ||
| 563 | #define BM_LRADC_CHn_ACCUMULATE 0x20000000 | ||
| 564 | #define BF_LRADC_CHn_ACCUMULATE(v) (((v) << 29) & 0x20000000) | ||
| 565 | #define BP_LRADC_CHn_NUM_SAMPLES 24 | ||
| 566 | #define BM_LRADC_CHn_NUM_SAMPLES 0x1f000000 | ||
| 567 | #define BF_LRADC_CHn_NUM_SAMPLES(v) (((v) << 24) & 0x1f000000) | ||
| 568 | #define BP_LRADC_CHn_VALUE 0 | ||
| 569 | #define BM_LRADC_CHn_VALUE 0x3ffff | ||
| 570 | #define BF_LRADC_CHn_VALUE(v) (((v) << 0) & 0x3ffff) | ||
| 571 | |||
| 572 | #endif /* __HEADERGEN__STMP3600__LRADC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h b/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h new file mode 100644 index 0000000000..3ba723eab3 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h | |||
| @@ -0,0 +1,105 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__MEMCPY__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__MEMCPY__H__ | ||
| 25 | |||
| 26 | #define REGS_MEMCPY_BASE (0x80014000) | ||
| 27 | |||
| 28 | #define REGS_MEMCPY_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_MEMCPY_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_MEMCPY_CTRL (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_MEMCPY_CTRL_SET (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_MEMCPY_CTRL_CLR (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_MEMCPY_CTRL_TOG (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_MEMCPY_CTRL_SFTRST 31 | ||
| 40 | #define BM_MEMCPY_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BV_MEMCPY_CTRL_SFTRST__RUN 0x0 | ||
| 42 | #define BV_MEMCPY_CTRL_SFTRST__RESET 0x1 | ||
| 43 | #define BF_MEMCPY_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 44 | #define BF_MEMCPY_CTRL_SFTRST_V(v) ((BV_MEMCPY_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
| 45 | #define BP_MEMCPY_CTRL_CLKGATE 30 | ||
| 46 | #define BM_MEMCPY_CTRL_CLKGATE 0x40000000 | ||
| 47 | #define BV_MEMCPY_CTRL_CLKGATE__RUN 0x0 | ||
| 48 | #define BV_MEMCPY_CTRL_CLKGATE__NO_CLKS 0x1 | ||
| 49 | #define BF_MEMCPY_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 50 | #define BF_MEMCPY_CTRL_CLKGATE_V(v) ((BV_MEMCPY_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
| 51 | #define BP_MEMCPY_CTRL_PRESENT 29 | ||
| 52 | #define BM_MEMCPY_CTRL_PRESENT 0x20000000 | ||
| 53 | #define BV_MEMCPY_CTRL_PRESENT__UNAVAILABLE 0x0 | ||
| 54 | #define BV_MEMCPY_CTRL_PRESENT__AVAILABLE 0x1 | ||
| 55 | #define BF_MEMCPY_CTRL_PRESENT(v) (((v) << 29) & 0x20000000) | ||
| 56 | #define BF_MEMCPY_CTRL_PRESENT_V(v) ((BV_MEMCPY_CTRL_PRESENT__##v << 29) & 0x20000000) | ||
| 57 | #define BP_MEMCPY_CTRL_BURST 16 | ||
| 58 | #define BM_MEMCPY_CTRL_BURST 0x10000 | ||
| 59 | #define BF_MEMCPY_CTRL_BURST(v) (((v) << 16) & 0x10000) | ||
| 60 | #define BP_MEMCPY_CTRL_XFER_SIZE 0 | ||
| 61 | #define BM_MEMCPY_CTRL_XFER_SIZE 0xffff | ||
| 62 | #define BF_MEMCPY_CTRL_XFER_SIZE(v) (((v) << 0) & 0xffff) | ||
| 63 | |||
| 64 | /** | ||
| 65 | * Register: HW_MEMCPY_DATA | ||
| 66 | * Address: 0x10 | ||
| 67 | * SCT: yes | ||
| 68 | */ | ||
| 69 | #define HW_MEMCPY_DATA (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x0)) | ||
| 70 | #define HW_MEMCPY_DATA_SET (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x4)) | ||
| 71 | #define HW_MEMCPY_DATA_CLR (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x8)) | ||
| 72 | #define HW_MEMCPY_DATA_TOG (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0xc)) | ||
| 73 | #define BP_MEMCPY_DATA_DATA 0 | ||
| 74 | #define BM_MEMCPY_DATA_DATA 0xffffffff | ||
| 75 | #define BF_MEMCPY_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 76 | |||
| 77 | /** | ||
| 78 | * Register: HW_MEMCPY_DEBUG | ||
| 79 | * Address: 0x20 | ||
| 80 | * SCT: no | ||
| 81 | */ | ||
| 82 | #define HW_MEMCPY_DEBUG (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x20)) | ||
| 83 | #define BP_MEMCPY_DEBUG_DST_END_CMD 30 | ||
| 84 | #define BM_MEMCPY_DEBUG_DST_END_CMD 0x40000000 | ||
| 85 | #define BF_MEMCPY_DEBUG_DST_END_CMD(v) (((v) << 30) & 0x40000000) | ||
| 86 | #define BP_MEMCPY_DEBUG_DST_KICK 29 | ||
| 87 | #define BM_MEMCPY_DEBUG_DST_KICK 0x20000000 | ||
| 88 | #define BF_MEMCPY_DEBUG_DST_KICK(v) (((v) << 29) & 0x20000000) | ||
| 89 | #define BP_MEMCPY_DEBUG_DST_DMA_REQ 28 | ||
| 90 | #define BM_MEMCPY_DEBUG_DST_DMA_REQ 0x10000000 | ||
| 91 | #define BF_MEMCPY_DEBUG_DST_DMA_REQ(v) (((v) << 28) & 0x10000000) | ||
| 92 | #define BP_MEMCPY_DEBUG_SRC_KICK 25 | ||
| 93 | #define BM_MEMCPY_DEBUG_SRC_KICK 0x2000000 | ||
| 94 | #define BF_MEMCPY_DEBUG_SRC_KICK(v) (((v) << 25) & 0x2000000) | ||
| 95 | #define BP_MEMCPY_DEBUG_SRC_DMA_REQ 24 | ||
| 96 | #define BM_MEMCPY_DEBUG_SRC_DMA_REQ 0x1000000 | ||
| 97 | #define BF_MEMCPY_DEBUG_SRC_DMA_REQ(v) (((v) << 24) & 0x1000000) | ||
| 98 | #define BP_MEMCPY_DEBUG_WRITE_STATE 2 | ||
| 99 | #define BM_MEMCPY_DEBUG_WRITE_STATE 0xc | ||
| 100 | #define BF_MEMCPY_DEBUG_WRITE_STATE(v) (((v) << 2) & 0xc) | ||
| 101 | #define BP_MEMCPY_DEBUG_READ_STATE 0 | ||
| 102 | #define BM_MEMCPY_DEBUG_READ_STATE 0x3 | ||
| 103 | #define BF_MEMCPY_DEBUG_READ_STATE(v) (((v) << 0) & 0x3) | ||
| 104 | |||
| 105 | #endif /* __HEADERGEN__STMP3600__MEMCPY__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-pinctrl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-pinctrl.h new file mode 100644 index 0000000000..14b6069060 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-pinctrl.h | |||
| @@ -0,0 +1,213 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__PINCTRL__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__PINCTRL__H__ | ||
| 25 | |||
| 26 | #define REGS_PINCTRL_BASE (0x80018000) | ||
| 27 | |||
| 28 | #define REGS_PINCTRL_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_PINCTRL_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_PINCTRL_CTRL (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_PINCTRL_CTRL_SET (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_PINCTRL_CTRL_CLR (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_PINCTRL_CTRL_TOG (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_PINCTRL_CTRL_SFTRST 31 | ||
| 40 | #define BM_PINCTRL_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_PINCTRL_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_PINCTRL_CTRL_CLKGATE 30 | ||
| 43 | #define BM_PINCTRL_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_PINCTRL_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_PINCTRL_CTRL_PRESENT3 29 | ||
| 46 | #define BM_PINCTRL_CTRL_PRESENT3 0x20000000 | ||
| 47 | #define BF_PINCTRL_CTRL_PRESENT3(v) (((v) << 29) & 0x20000000) | ||
| 48 | #define BP_PINCTRL_CTRL_PRESENT2 28 | ||
| 49 | #define BM_PINCTRL_CTRL_PRESENT2 0x10000000 | ||
| 50 | #define BF_PINCTRL_CTRL_PRESENT2(v) (((v) << 28) & 0x10000000) | ||
| 51 | #define BP_PINCTRL_CTRL_PRESENT1 27 | ||
| 52 | #define BM_PINCTRL_CTRL_PRESENT1 0x8000000 | ||
| 53 | #define BF_PINCTRL_CTRL_PRESENT1(v) (((v) << 27) & 0x8000000) | ||
| 54 | #define BP_PINCTRL_CTRL_PRESENT0 26 | ||
| 55 | #define BM_PINCTRL_CTRL_PRESENT0 0x4000000 | ||
| 56 | #define BF_PINCTRL_CTRL_PRESENT0(v) (((v) << 26) & 0x4000000) | ||
| 57 | #define BP_PINCTRL_CTRL_IRQOUT3 3 | ||
| 58 | #define BM_PINCTRL_CTRL_IRQOUT3 0x8 | ||
| 59 | #define BF_PINCTRL_CTRL_IRQOUT3(v) (((v) << 3) & 0x8) | ||
| 60 | #define BP_PINCTRL_CTRL_IRQOUT2 2 | ||
| 61 | #define BM_PINCTRL_CTRL_IRQOUT2 0x4 | ||
| 62 | #define BF_PINCTRL_CTRL_IRQOUT2(v) (((v) << 2) & 0x4) | ||
| 63 | #define BP_PINCTRL_CTRL_IRQOUT1 1 | ||
| 64 | #define BM_PINCTRL_CTRL_IRQOUT1 0x2 | ||
| 65 | #define BF_PINCTRL_CTRL_IRQOUT1(v) (((v) << 1) & 0x2) | ||
| 66 | #define BP_PINCTRL_CTRL_IRQOUT0 0 | ||
| 67 | #define BM_PINCTRL_CTRL_IRQOUT0 0x1 | ||
| 68 | #define BF_PINCTRL_CTRL_IRQOUT0(v) (((v) << 0) & 0x1) | ||
| 69 | |||
| 70 | /** | ||
| 71 | * Register: HW_PINCTRL_MUXSELLn | ||
| 72 | * Address: 0x10+n*0x100 | ||
| 73 | * SCT: yes | ||
| 74 | */ | ||
| 75 | #define HW_PINCTRL_MUXSELLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0x0)) | ||
| 76 | #define HW_PINCTRL_MUXSELLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0x4)) | ||
| 77 | #define HW_PINCTRL_MUXSELLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0x8)) | ||
| 78 | #define HW_PINCTRL_MUXSELLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0xc)) | ||
| 79 | #define BP_PINCTRL_MUXSELLn_BITS 0 | ||
| 80 | #define BM_PINCTRL_MUXSELLn_BITS 0xffffffff | ||
| 81 | #define BF_PINCTRL_MUXSELLn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 82 | |||
| 83 | /** | ||
| 84 | * Register: HW_PINCTRL_MUXSELHn | ||
| 85 | * Address: 0x20+n*0x100 | ||
| 86 | * SCT: yes | ||
| 87 | */ | ||
| 88 | #define HW_PINCTRL_MUXSELHn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0x0)) | ||
| 89 | #define HW_PINCTRL_MUXSELHn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0x4)) | ||
| 90 | #define HW_PINCTRL_MUXSELHn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0x8)) | ||
| 91 | #define HW_PINCTRL_MUXSELHn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0xc)) | ||
| 92 | #define BP_PINCTRL_MUXSELHn_BITS 0 | ||
| 93 | #define BM_PINCTRL_MUXSELHn_BITS 0xffffffff | ||
| 94 | #define BF_PINCTRL_MUXSELHn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 95 | |||
| 96 | /** | ||
| 97 | * Register: HW_PINCTRL_DRIVEn | ||
| 98 | * Address: 0x30+n*0x100 | ||
| 99 | * SCT: yes | ||
| 100 | */ | ||
| 101 | #define HW_PINCTRL_DRIVEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0x0)) | ||
| 102 | #define HW_PINCTRL_DRIVEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0x4)) | ||
| 103 | #define HW_PINCTRL_DRIVEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0x8)) | ||
| 104 | #define HW_PINCTRL_DRIVEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0xc)) | ||
| 105 | #define BP_PINCTRL_DRIVEn_BITS 0 | ||
| 106 | #define BM_PINCTRL_DRIVEn_BITS 0xffffffff | ||
| 107 | #define BF_PINCTRL_DRIVEn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 108 | |||
| 109 | /** | ||
| 110 | * Register: HW_PINCTRL_DOUTn | ||
| 111 | * Address: 0x50+n*0x100 | ||
| 112 | * SCT: yes | ||
| 113 | */ | ||
| 114 | #define HW_PINCTRL_DOUTn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0x0)) | ||
| 115 | #define HW_PINCTRL_DOUTn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0x4)) | ||
| 116 | #define HW_PINCTRL_DOUTn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0x8)) | ||
| 117 | #define HW_PINCTRL_DOUTn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0xc)) | ||
| 118 | #define BP_PINCTRL_DOUTn_BITS 0 | ||
| 119 | #define BM_PINCTRL_DOUTn_BITS 0xffffffff | ||
| 120 | #define BF_PINCTRL_DOUTn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 121 | |||
| 122 | /** | ||
| 123 | * Register: HW_PINCTRL_DINn | ||
| 124 | * Address: 0x60+n*0x100 | ||
| 125 | * SCT: yes | ||
| 126 | */ | ||
| 127 | #define HW_PINCTRL_DINn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0x0)) | ||
| 128 | #define HW_PINCTRL_DINn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0x4)) | ||
| 129 | #define HW_PINCTRL_DINn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0x8)) | ||
| 130 | #define HW_PINCTRL_DINn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0xc)) | ||
| 131 | #define BP_PINCTRL_DINn_BITS 0 | ||
| 132 | #define BM_PINCTRL_DINn_BITS 0xffffffff | ||
| 133 | #define BF_PINCTRL_DINn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 134 | |||
| 135 | /** | ||
| 136 | * Register: HW_PINCTRL_DOEn | ||
| 137 | * Address: 0x70+n*0x100 | ||
| 138 | * SCT: yes | ||
| 139 | */ | ||
| 140 | #define HW_PINCTRL_DOEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0x0)) | ||
| 141 | #define HW_PINCTRL_DOEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0x4)) | ||
| 142 | #define HW_PINCTRL_DOEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0x8)) | ||
| 143 | #define HW_PINCTRL_DOEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0xc)) | ||
| 144 | #define BP_PINCTRL_DOEn_BITS 0 | ||
| 145 | #define BM_PINCTRL_DOEn_BITS 0xffffffff | ||
| 146 | #define BF_PINCTRL_DOEn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 147 | |||
| 148 | /** | ||
| 149 | * Register: HW_PINCTRL_PIN2IRQn | ||
| 150 | * Address: 0x80+n*0x100 | ||
| 151 | * SCT: yes | ||
| 152 | */ | ||
| 153 | #define HW_PINCTRL_PIN2IRQn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0x0)) | ||
| 154 | #define HW_PINCTRL_PIN2IRQn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0x4)) | ||
| 155 | #define HW_PINCTRL_PIN2IRQn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0x8)) | ||
| 156 | #define HW_PINCTRL_PIN2IRQn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0xc)) | ||
| 157 | #define BP_PINCTRL_PIN2IRQn_BITS 0 | ||
| 158 | #define BM_PINCTRL_PIN2IRQn_BITS 0xffffffff | ||
| 159 | #define BF_PINCTRL_PIN2IRQn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 160 | |||
| 161 | /** | ||
| 162 | * Register: HW_PINCTRL_IRQENn | ||
| 163 | * Address: 0x90+n*0x100 | ||
| 164 | * SCT: yes | ||
| 165 | */ | ||
| 166 | #define HW_PINCTRL_IRQENn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0x0)) | ||
| 167 | #define HW_PINCTRL_IRQENn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0x4)) | ||
| 168 | #define HW_PINCTRL_IRQENn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0x8)) | ||
| 169 | #define HW_PINCTRL_IRQENn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0xc)) | ||
| 170 | #define BP_PINCTRL_IRQENn_BITS 0 | ||
| 171 | #define BM_PINCTRL_IRQENn_BITS 0xffffffff | ||
| 172 | #define BF_PINCTRL_IRQENn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 173 | |||
| 174 | /** | ||
| 175 | * Register: HW_PINCTRL_IRQLEVELn | ||
| 176 | * Address: 0xa0+n*0x100 | ||
| 177 | * SCT: yes | ||
| 178 | */ | ||
| 179 | #define HW_PINCTRL_IRQLEVELn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0x0)) | ||
| 180 | #define HW_PINCTRL_IRQLEVELn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0x4)) | ||
| 181 | #define HW_PINCTRL_IRQLEVELn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0x8)) | ||
| 182 | #define HW_PINCTRL_IRQLEVELn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0xc)) | ||
| 183 | #define BP_PINCTRL_IRQLEVELn_BITS 0 | ||
| 184 | #define BM_PINCTRL_IRQLEVELn_BITS 0xffffffff | ||
| 185 | #define BF_PINCTRL_IRQLEVELn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 186 | |||
| 187 | /** | ||
| 188 | * Register: HW_PINCTRL_IRQPOLn | ||
| 189 | * Address: 0xb0+n*0x100 | ||
| 190 | * SCT: yes | ||
| 191 | */ | ||
| 192 | #define HW_PINCTRL_IRQPOLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0x0)) | ||
| 193 | #define HW_PINCTRL_IRQPOLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0x4)) | ||
| 194 | #define HW_PINCTRL_IRQPOLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0x8)) | ||
| 195 | #define HW_PINCTRL_IRQPOLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0xc)) | ||
| 196 | #define BP_PINCTRL_IRQPOLn_BITS 0 | ||
| 197 | #define BM_PINCTRL_IRQPOLn_BITS 0xffffffff | ||
| 198 | #define BF_PINCTRL_IRQPOLn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 199 | |||
| 200 | /** | ||
| 201 | * Register: HW_PINCTRL_IRQSTATn | ||
| 202 | * Address: 0xc0+n*0x100 | ||
| 203 | * SCT: yes | ||
| 204 | */ | ||
| 205 | #define HW_PINCTRL_IRQSTATn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0x0)) | ||
| 206 | #define HW_PINCTRL_IRQSTATn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0x4)) | ||
| 207 | #define HW_PINCTRL_IRQSTATn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0x8)) | ||
| 208 | #define HW_PINCTRL_IRQSTATn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0xc)) | ||
| 209 | #define BP_PINCTRL_IRQSTATn_BITS 0 | ||
| 210 | #define BM_PINCTRL_IRQSTATn_BITS 0xffffffff | ||
| 211 | #define BF_PINCTRL_IRQSTATn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 212 | |||
| 213 | #endif /* __HEADERGEN__STMP3600__PINCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-power.h b/firmware/target/arm/imx233/regs/stmp3600/regs-power.h new file mode 100644 index 0000000000..577a1c6415 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-power.h | |||
| @@ -0,0 +1,484 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__POWER__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__POWER__H__ | ||
| 25 | |||
| 26 | #define REGS_POWER_BASE (0x80044000) | ||
| 27 | |||
| 28 | #define REGS_POWER_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_POWER_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_POWER_CTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_POWER_CTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_POWER_CTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_POWER_CTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_POWER_CTRL_CLKGATE 30 | ||
| 40 | #define BM_POWER_CTRL_CLKGATE 0x40000000 | ||
| 41 | #define BF_POWER_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 42 | #define BP_POWER_CTRL_BATT_BO_IRQ 8 | ||
| 43 | #define BM_POWER_CTRL_BATT_BO_IRQ 0x100 | ||
| 44 | #define BF_POWER_CTRL_BATT_BO_IRQ(v) (((v) << 8) & 0x100) | ||
| 45 | #define BP_POWER_CTRL_ENIRQBATT_BO 7 | ||
| 46 | #define BM_POWER_CTRL_ENIRQBATT_BO 0x80 | ||
| 47 | #define BF_POWER_CTRL_ENIRQBATT_BO(v) (((v) << 7) & 0x80) | ||
| 48 | #define BP_POWER_CTRL_VDDIO_BO_IRQ 6 | ||
| 49 | #define BM_POWER_CTRL_VDDIO_BO_IRQ 0x40 | ||
| 50 | #define BF_POWER_CTRL_VDDIO_BO_IRQ(v) (((v) << 6) & 0x40) | ||
| 51 | #define BP_POWER_CTRL_ENIRQVDDIO_BO 5 | ||
| 52 | #define BM_POWER_CTRL_ENIRQVDDIO_BO 0x20 | ||
| 53 | #define BF_POWER_CTRL_ENIRQVDDIO_BO(v) (((v) << 5) & 0x20) | ||
| 54 | #define BP_POWER_CTRL_VDDD_BO_IRQ 4 | ||
| 55 | #define BM_POWER_CTRL_VDDD_BO_IRQ 0x10 | ||
| 56 | #define BF_POWER_CTRL_VDDD_BO_IRQ(v) (((v) << 4) & 0x10) | ||
| 57 | #define BP_POWER_CTRL_ENIRQVDDD_BO 3 | ||
| 58 | #define BM_POWER_CTRL_ENIRQVDDD_BO 0x8 | ||
| 59 | #define BF_POWER_CTRL_ENIRQVDDD_BO(v) (((v) << 3) & 0x8) | ||
| 60 | #define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 2 | ||
| 61 | #define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 0x4 | ||
| 62 | #define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v) (((v) << 2) & 0x4) | ||
| 63 | #define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 1 | ||
| 64 | #define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 0x2 | ||
| 65 | #define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v) (((v) << 1) & 0x2) | ||
| 66 | #define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0 | ||
| 67 | #define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x1 | ||
| 68 | #define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v) (((v) << 0) & 0x1) | ||
| 69 | |||
| 70 | /** | ||
| 71 | * Register: HW_POWER_5VCTRL | ||
| 72 | * Address: 0x10 | ||
| 73 | * SCT: yes | ||
| 74 | */ | ||
| 75 | #define HW_POWER_5VCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x0)) | ||
| 76 | #define HW_POWER_5VCTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x4)) | ||
| 77 | #define HW_POWER_5VCTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x8)) | ||
| 78 | #define HW_POWER_5VCTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0xc)) | ||
| 79 | #define BP_POWER_5VCTRL_PWDN_5VBRNOUT 21 | ||
| 80 | #define BM_POWER_5VCTRL_PWDN_5VBRNOUT 0x200000 | ||
| 81 | #define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v) (((v) << 21) & 0x200000) | ||
| 82 | #define BP_POWER_5VCTRL_PWDN_IOBRNOUT 20 | ||
| 83 | #define BM_POWER_5VCTRL_PWDN_IOBRNOUT 0x100000 | ||
| 84 | #define BF_POWER_5VCTRL_PWDN_IOBRNOUT(v) (((v) << 20) & 0x100000) | ||
| 85 | #define BP_POWER_5VCTRL_DISABLE_ILIMIT 19 | ||
| 86 | #define BM_POWER_5VCTRL_DISABLE_ILIMIT 0x80000 | ||
| 87 | #define BF_POWER_5VCTRL_DISABLE_ILIMIT(v) (((v) << 19) & 0x80000) | ||
| 88 | #define BP_POWER_5VCTRL_DCDC_XFER 18 | ||
| 89 | #define BM_POWER_5VCTRL_DCDC_XFER 0x40000 | ||
| 90 | #define BF_POWER_5VCTRL_DCDC_XFER(v) (((v) << 18) & 0x40000) | ||
| 91 | #define BP_POWER_5VCTRL_EN_BATT_PULLDN 17 | ||
| 92 | #define BM_POWER_5VCTRL_EN_BATT_PULLDN 0x20000 | ||
| 93 | #define BF_POWER_5VCTRL_EN_BATT_PULLDN(v) (((v) << 17) & 0x20000) | ||
| 94 | #define BP_POWER_5VCTRL_VBUSVALID_5VDETECT 16 | ||
| 95 | #define BM_POWER_5VCTRL_VBUSVALID_5VDETECT 0x10000 | ||
| 96 | #define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v) (((v) << 16) & 0x10000) | ||
| 97 | #define BP_POWER_5VCTRL_VBUSVALID_TRSH 8 | ||
| 98 | #define BM_POWER_5VCTRL_VBUSVALID_TRSH 0x300 | ||
| 99 | #define BF_POWER_5VCTRL_VBUSVALID_TRSH(v) (((v) << 8) & 0x300) | ||
| 100 | #define BP_POWER_5VCTRL_USB_SUSPEND_I 7 | ||
| 101 | #define BM_POWER_5VCTRL_USB_SUSPEND_I 0x80 | ||
| 102 | #define BF_POWER_5VCTRL_USB_SUSPEND_I(v) (((v) << 7) & 0x80) | ||
| 103 | #define BP_POWER_5VCTRL_VBUSVALID_TO_B 6 | ||
| 104 | #define BM_POWER_5VCTRL_VBUSVALID_TO_B 0x40 | ||
| 105 | #define BF_POWER_5VCTRL_VBUSVALID_TO_B(v) (((v) << 6) & 0x40) | ||
| 106 | #define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO 5 | ||
| 107 | #define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO 0x20 | ||
| 108 | #define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v) (((v) << 5) & 0x20) | ||
| 109 | #define BP_POWER_5VCTRL_OTG_PWRUP_CMPS 4 | ||
| 110 | #define BM_POWER_5VCTRL_OTG_PWRUP_CMPS 0x10 | ||
| 111 | #define BF_POWER_5VCTRL_OTG_PWRUP_CMPS(v) (((v) << 4) & 0x10) | ||
| 112 | #define BP_POWER_5VCTRL_EN_DCDC2 3 | ||
| 113 | #define BM_POWER_5VCTRL_EN_DCDC2 0x8 | ||
| 114 | #define BF_POWER_5VCTRL_EN_DCDC2(v) (((v) << 3) & 0x8) | ||
| 115 | #define BP_POWER_5VCTRL_PWD_VDDD_LINREG 2 | ||
| 116 | #define BM_POWER_5VCTRL_PWD_VDDD_LINREG 0x4 | ||
| 117 | #define BF_POWER_5VCTRL_PWD_VDDD_LINREG(v) (((v) << 2) & 0x4) | ||
| 118 | #define BP_POWER_5VCTRL_EN_DCDC1 1 | ||
| 119 | #define BM_POWER_5VCTRL_EN_DCDC1 0x2 | ||
| 120 | #define BF_POWER_5VCTRL_EN_DCDC1(v) (((v) << 1) & 0x2) | ||
| 121 | #define BP_POWER_5VCTRL_LINREG_OFFSET 0 | ||
| 122 | #define BM_POWER_5VCTRL_LINREG_OFFSET 0x1 | ||
| 123 | #define BF_POWER_5VCTRL_LINREG_OFFSET(v) (((v) << 0) & 0x1) | ||
| 124 | |||
| 125 | /** | ||
| 126 | * Register: HW_POWER_MINPWR | ||
| 127 | * Address: 0x20 | ||
| 128 | * SCT: yes | ||
| 129 | */ | ||
| 130 | #define HW_POWER_MINPWR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x0)) | ||
| 131 | #define HW_POWER_MINPWR_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x4)) | ||
| 132 | #define HW_POWER_MINPWR_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x8)) | ||
| 133 | #define HW_POWER_MINPWR_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0xc)) | ||
| 134 | #define BP_POWER_MINPWR_TEST_DISCHRG_VBUS 23 | ||
| 135 | #define BM_POWER_MINPWR_TEST_DISCHRG_VBUS 0x800000 | ||
| 136 | #define BF_POWER_MINPWR_TEST_DISCHRG_VBUS(v) (((v) << 23) & 0x800000) | ||
| 137 | #define BP_POWER_MINPWR_TEST_CHRG_VBUS 22 | ||
| 138 | #define BM_POWER_MINPWR_TEST_CHRG_VBUS 0x400000 | ||
| 139 | #define BF_POWER_MINPWR_TEST_CHRG_VBUS(v) (((v) << 22) & 0x400000) | ||
| 140 | #define BP_POWER_MINPWR_DC2_TST 21 | ||
| 141 | #define BM_POWER_MINPWR_DC2_TST 0x200000 | ||
| 142 | #define BF_POWER_MINPWR_DC2_TST(v) (((v) << 21) & 0x200000) | ||
| 143 | #define BP_POWER_MINPWR_DC1_TST 20 | ||
| 144 | #define BM_POWER_MINPWR_DC1_TST 0x100000 | ||
| 145 | #define BF_POWER_MINPWR_DC1_TST(v) (((v) << 20) & 0x100000) | ||
| 146 | #define BP_POWER_MINPWR_PERIPHERALSWOFF 19 | ||
| 147 | #define BM_POWER_MINPWR_PERIPHERALSWOFF 0x80000 | ||
| 148 | #define BF_POWER_MINPWR_PERIPHERALSWOFF(v) (((v) << 19) & 0x80000) | ||
| 149 | #define BP_POWER_MINPWR_TOGGLE_DIF 18 | ||
| 150 | #define BM_POWER_MINPWR_TOGGLE_DIF 0x40000 | ||
| 151 | #define BF_POWER_MINPWR_TOGGLE_DIF(v) (((v) << 18) & 0x40000) | ||
| 152 | #define BP_POWER_MINPWR_DISABLE_VDDIOSTEP 17 | ||
| 153 | #define BM_POWER_MINPWR_DISABLE_VDDIOSTEP 0x20000 | ||
| 154 | #define BF_POWER_MINPWR_DISABLE_VDDIOSTEP(v) (((v) << 17) & 0x20000) | ||
| 155 | #define BP_POWER_MINPWR_DISABLE_VDDSTEP 16 | ||
| 156 | #define BM_POWER_MINPWR_DISABLE_VDDSTEP 0x10000 | ||
| 157 | #define BF_POWER_MINPWR_DISABLE_VDDSTEP(v) (((v) << 16) & 0x10000) | ||
| 158 | #define BP_POWER_MINPWR_SEL_PLLDIV16CLK 9 | ||
| 159 | #define BM_POWER_MINPWR_SEL_PLLDIV16CLK 0x200 | ||
| 160 | #define BF_POWER_MINPWR_SEL_PLLDIV16CLK(v) (((v) << 9) & 0x200) | ||
| 161 | #define BP_POWER_MINPWR_PWD_VDDIOBO 8 | ||
| 162 | #define BM_POWER_MINPWR_PWD_VDDIOBO 0x100 | ||
| 163 | #define BF_POWER_MINPWR_PWD_VDDIOBO(v) (((v) << 8) & 0x100) | ||
| 164 | #define BP_POWER_MINPWR_LESSANA_I 7 | ||
| 165 | #define BM_POWER_MINPWR_LESSANA_I 0x80 | ||
| 166 | #define BF_POWER_MINPWR_LESSANA_I(v) (((v) << 7) & 0x80) | ||
| 167 | #define BP_POWER_MINPWR_DC1_HALFFETS 6 | ||
| 168 | #define BM_POWER_MINPWR_DC1_HALFFETS 0x40 | ||
| 169 | #define BF_POWER_MINPWR_DC1_HALFFETS(v) (((v) << 6) & 0x40) | ||
| 170 | #define BP_POWER_MINPWR_DC2_STOPCLK 5 | ||
| 171 | #define BM_POWER_MINPWR_DC2_STOPCLK 0x20 | ||
| 172 | #define BF_POWER_MINPWR_DC2_STOPCLK(v) (((v) << 5) & 0x20) | ||
| 173 | #define BP_POWER_MINPWR_DC1_STOPCLK 4 | ||
| 174 | #define BM_POWER_MINPWR_DC1_STOPCLK 0x10 | ||
| 175 | #define BF_POWER_MINPWR_DC1_STOPCLK(v) (((v) << 4) & 0x10) | ||
| 176 | #define BP_POWER_MINPWR_EN_DC2_PFM 3 | ||
| 177 | #define BM_POWER_MINPWR_EN_DC2_PFM 0x8 | ||
| 178 | #define BF_POWER_MINPWR_EN_DC2_PFM(v) (((v) << 3) & 0x8) | ||
| 179 | #define BP_POWER_MINPWR_EN_DC1_PFM 2 | ||
| 180 | #define BM_POWER_MINPWR_EN_DC1_PFM 0x4 | ||
| 181 | #define BF_POWER_MINPWR_EN_DC1_PFM(v) (((v) << 2) & 0x4) | ||
| 182 | #define BP_POWER_MINPWR_DC2_HALFCLK 1 | ||
| 183 | #define BM_POWER_MINPWR_DC2_HALFCLK 0x2 | ||
| 184 | #define BF_POWER_MINPWR_DC2_HALFCLK(v) (((v) << 1) & 0x2) | ||
| 185 | #define BP_POWER_MINPWR_DC1_HALFCLK 0 | ||
| 186 | #define BM_POWER_MINPWR_DC1_HALFCLK 0x1 | ||
| 187 | #define BF_POWER_MINPWR_DC1_HALFCLK(v) (((v) << 0) & 0x1) | ||
| 188 | |||
| 189 | /** | ||
| 190 | * Register: HW_POWER_BATTCHRG | ||
| 191 | * Address: 0x30 | ||
| 192 | * SCT: yes | ||
| 193 | */ | ||
| 194 | #define HW_POWER_BATTCHRG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x0)) | ||
| 195 | #define HW_POWER_BATTCHRG_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x4)) | ||
| 196 | #define HW_POWER_BATTCHRG_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x8)) | ||
| 197 | #define HW_POWER_BATTCHRG_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0xc)) | ||
| 198 | #define BP_POWER_BATTCHRG_CHRG_STS_OFF 19 | ||
| 199 | #define BM_POWER_BATTCHRG_CHRG_STS_OFF 0x80000 | ||
| 200 | #define BF_POWER_BATTCHRG_CHRG_STS_OFF(v) (((v) << 19) & 0x80000) | ||
| 201 | #define BP_POWER_BATTCHRG_LIION_4P1 18 | ||
| 202 | #define BM_POWER_BATTCHRG_LIION_4P1 0x40000 | ||
| 203 | #define BF_POWER_BATTCHRG_LIION_4P1(v) (((v) << 18) & 0x40000) | ||
| 204 | #define BP_POWER_BATTCHRG_USE_EXTERN_R 17 | ||
| 205 | #define BM_POWER_BATTCHRG_USE_EXTERN_R 0x20000 | ||
| 206 | #define BF_POWER_BATTCHRG_USE_EXTERN_R(v) (((v) << 17) & 0x20000) | ||
| 207 | #define BP_POWER_BATTCHRG_PWD_BATTCHRG 16 | ||
| 208 | #define BM_POWER_BATTCHRG_PWD_BATTCHRG 0x10000 | ||
| 209 | #define BF_POWER_BATTCHRG_PWD_BATTCHRG(v) (((v) << 16) & 0x10000) | ||
| 210 | #define BP_POWER_BATTCHRG_STOP_ILIMIT 8 | ||
| 211 | #define BM_POWER_BATTCHRG_STOP_ILIMIT 0xf00 | ||
| 212 | #define BF_POWER_BATTCHRG_STOP_ILIMIT(v) (((v) << 8) & 0xf00) | ||
| 213 | #define BP_POWER_BATTCHRG_BATTCHRG_I 0 | ||
| 214 | #define BM_POWER_BATTCHRG_BATTCHRG_I 0x3f | ||
| 215 | #define BF_POWER_BATTCHRG_BATTCHRG_I(v) (((v) << 0) & 0x3f) | ||
| 216 | |||
| 217 | /** | ||
| 218 | * Register: HW_POWER_VDDCTRL | ||
| 219 | * Address: 0x40 | ||
| 220 | * SCT: no | ||
| 221 | */ | ||
| 222 | #define HW_POWER_VDDCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x40)) | ||
| 223 | #define BP_POWER_VDDCTRL_VDDIO_BO 24 | ||
| 224 | #define BM_POWER_VDDCTRL_VDDIO_BO 0x1f000000 | ||
| 225 | #define BF_POWER_VDDCTRL_VDDIO_BO(v) (((v) << 24) & 0x1f000000) | ||
| 226 | #define BP_POWER_VDDCTRL_VDDIO_TRG 16 | ||
| 227 | #define BM_POWER_VDDCTRL_VDDIO_TRG 0x1f0000 | ||
| 228 | #define BF_POWER_VDDCTRL_VDDIO_TRG(v) (((v) << 16) & 0x1f0000) | ||
| 229 | #define BP_POWER_VDDCTRL_VDDD_BO 8 | ||
| 230 | #define BM_POWER_VDDCTRL_VDDD_BO 0x1f00 | ||
| 231 | #define BF_POWER_VDDCTRL_VDDD_BO(v) (((v) << 8) & 0x1f00) | ||
| 232 | #define BP_POWER_VDDCTRL_VDDD_TRG 0 | ||
| 233 | #define BM_POWER_VDDCTRL_VDDD_TRG 0x1f | ||
| 234 | #define BF_POWER_VDDCTRL_VDDD_TRG(v) (((v) << 0) & 0x1f) | ||
| 235 | |||
| 236 | /** | ||
| 237 | * Register: HW_POWER_DC1MULTOUT | ||
| 238 | * Address: 0x50 | ||
| 239 | * SCT: no | ||
| 240 | */ | ||
| 241 | #define HW_POWER_DC1MULTOUT (*(volatile unsigned long *)(REGS_POWER_BASE + 0x50)) | ||
| 242 | #define BP_POWER_DC1MULTOUT_FUNCV 16 | ||
| 243 | #define BM_POWER_DC1MULTOUT_FUNCV 0x1ff0000 | ||
| 244 | #define BF_POWER_DC1MULTOUT_FUNCV(v) (((v) << 16) & 0x1ff0000) | ||
| 245 | #define BP_POWER_DC1MULTOUT_EN_BATADJ 8 | ||
| 246 | #define BM_POWER_DC1MULTOUT_EN_BATADJ 0x100 | ||
| 247 | #define BF_POWER_DC1MULTOUT_EN_BATADJ(v) (((v) << 8) & 0x100) | ||
| 248 | #define BP_POWER_DC1MULTOUT_ADJTN 0 | ||
| 249 | #define BM_POWER_DC1MULTOUT_ADJTN 0xf | ||
| 250 | #define BF_POWER_DC1MULTOUT_ADJTN(v) (((v) << 0) & 0xf) | ||
| 251 | |||
| 252 | /** | ||
| 253 | * Register: HW_POWER_DC1LIMITS | ||
| 254 | * Address: 0x60 | ||
| 255 | * SCT: no | ||
| 256 | */ | ||
| 257 | #define HW_POWER_DC1LIMITS (*(volatile unsigned long *)(REGS_POWER_BASE + 0x60)) | ||
| 258 | #define BP_POWER_DC1LIMITS_EN_PFETOFF 24 | ||
| 259 | #define BM_POWER_DC1LIMITS_EN_PFETOFF 0x1000000 | ||
| 260 | #define BF_POWER_DC1LIMITS_EN_PFETOFF(v) (((v) << 24) & 0x1000000) | ||
| 261 | #define BP_POWER_DC1LIMITS_POSLIMIT_BOOST 16 | ||
| 262 | #define BM_POWER_DC1LIMITS_POSLIMIT_BOOST 0x7f0000 | ||
| 263 | #define BF_POWER_DC1LIMITS_POSLIMIT_BOOST(v) (((v) << 16) & 0x7f0000) | ||
| 264 | #define BP_POWER_DC1LIMITS_POSLIMIT_BUCK 8 | ||
| 265 | #define BM_POWER_DC1LIMITS_POSLIMIT_BUCK 0x7f00 | ||
| 266 | #define BF_POWER_DC1LIMITS_POSLIMIT_BUCK(v) (((v) << 8) & 0x7f00) | ||
| 267 | #define BP_POWER_DC1LIMITS_NEGLIMIT 0 | ||
| 268 | #define BM_POWER_DC1LIMITS_NEGLIMIT 0x7f | ||
| 269 | #define BF_POWER_DC1LIMITS_NEGLIMIT(v) (((v) << 0) & 0x7f) | ||
| 270 | |||
| 271 | /** | ||
| 272 | * Register: HW_POWER_DC2LIMITS | ||
| 273 | * Address: 0x70 | ||
| 274 | * SCT: no | ||
| 275 | */ | ||
| 276 | #define HW_POWER_DC2LIMITS (*(volatile unsigned long *)(REGS_POWER_BASE + 0x70)) | ||
| 277 | #define BP_POWER_DC2LIMITS_EN_BOOST 24 | ||
| 278 | #define BM_POWER_DC2LIMITS_EN_BOOST 0x1000000 | ||
| 279 | #define BF_POWER_DC2LIMITS_EN_BOOST(v) (((v) << 24) & 0x1000000) | ||
| 280 | #define BP_POWER_DC2LIMITS_POSLIMIT_BOOST 16 | ||
| 281 | #define BM_POWER_DC2LIMITS_POSLIMIT_BOOST 0x7f0000 | ||
| 282 | #define BF_POWER_DC2LIMITS_POSLIMIT_BOOST(v) (((v) << 16) & 0x7f0000) | ||
| 283 | #define BP_POWER_DC2LIMITS_POSLIMIT_BUCK 8 | ||
| 284 | #define BM_POWER_DC2LIMITS_POSLIMIT_BUCK 0x7f00 | ||
| 285 | #define BF_POWER_DC2LIMITS_POSLIMIT_BUCK(v) (((v) << 8) & 0x7f00) | ||
| 286 | #define BP_POWER_DC2LIMITS_NEGLIMIT 0 | ||
| 287 | #define BM_POWER_DC2LIMITS_NEGLIMIT 0x7f | ||
| 288 | #define BF_POWER_DC2LIMITS_NEGLIMIT(v) (((v) << 0) & 0x7f) | ||
| 289 | |||
| 290 | /** | ||
| 291 | * Register: HW_POWER_LOOPCTRL | ||
| 292 | * Address: 0x80 | ||
| 293 | * SCT: yes | ||
| 294 | */ | ||
| 295 | #define HW_POWER_LOOPCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0x0)) | ||
| 296 | #define HW_POWER_LOOPCTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0x4)) | ||
| 297 | #define HW_POWER_LOOPCTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0x8)) | ||
| 298 | #define HW_POWER_LOOPCTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0xc)) | ||
| 299 | #define BP_POWER_LOOPCTRL_TRAN_NOHYST 30 | ||
| 300 | #define BM_POWER_LOOPCTRL_TRAN_NOHYST 0x40000000 | ||
| 301 | #define BF_POWER_LOOPCTRL_TRAN_NOHYST(v) (((v) << 30) & 0x40000000) | ||
| 302 | #define BP_POWER_LOOPCTRL_HYST_SIGN 29 | ||
| 303 | #define BM_POWER_LOOPCTRL_HYST_SIGN 0x20000000 | ||
| 304 | #define BF_POWER_LOOPCTRL_HYST_SIGN(v) (((v) << 29) & 0x20000000) | ||
| 305 | #define BP_POWER_LOOPCTRL_EN_CMP_HYST 28 | ||
| 306 | #define BM_POWER_LOOPCTRL_EN_CMP_HYST 0x10000000 | ||
| 307 | #define BF_POWER_LOOPCTRL_EN_CMP_HYST(v) (((v) << 28) & 0x10000000) | ||
| 308 | #define BP_POWER_LOOPCTRL_EN_DC2_RCSCALE 27 | ||
| 309 | #define BM_POWER_LOOPCTRL_EN_DC2_RCSCALE 0x8000000 | ||
| 310 | #define BF_POWER_LOOPCTRL_EN_DC2_RCSCALE(v) (((v) << 27) & 0x8000000) | ||
| 311 | #define BP_POWER_LOOPCTRL_EN_DC1_RCSCALE 26 | ||
| 312 | #define BM_POWER_LOOPCTRL_EN_DC1_RCSCALE 0x4000000 | ||
| 313 | #define BF_POWER_LOOPCTRL_EN_DC1_RCSCALE(v) (((v) << 26) & 0x4000000) | ||
| 314 | #define BP_POWER_LOOPCTRL_RC_SIGN 25 | ||
| 315 | #define BM_POWER_LOOPCTRL_RC_SIGN 0x2000000 | ||
| 316 | #define BF_POWER_LOOPCTRL_RC_SIGN(v) (((v) << 25) & 0x2000000) | ||
| 317 | #define BP_POWER_LOOPCTRL_EN_RCSCALE 24 | ||
| 318 | #define BM_POWER_LOOPCTRL_EN_RCSCALE 0x1000000 | ||
| 319 | #define BF_POWER_LOOPCTRL_EN_RCSCALE(v) (((v) << 24) & 0x1000000) | ||
| 320 | #define BP_POWER_LOOPCTRL_DC2_FF 20 | ||
| 321 | #define BM_POWER_LOOPCTRL_DC2_FF 0x700000 | ||
| 322 | #define BF_POWER_LOOPCTRL_DC2_FF(v) (((v) << 20) & 0x700000) | ||
| 323 | #define BP_POWER_LOOPCTRL_DC2_R 16 | ||
| 324 | #define BM_POWER_LOOPCTRL_DC2_R 0xf0000 | ||
| 325 | #define BF_POWER_LOOPCTRL_DC2_R(v) (((v) << 16) & 0xf0000) | ||
| 326 | #define BP_POWER_LOOPCTRL_DC2_C 12 | ||
| 327 | #define BM_POWER_LOOPCTRL_DC2_C 0x3000 | ||
| 328 | #define BF_POWER_LOOPCTRL_DC2_C(v) (((v) << 12) & 0x3000) | ||
| 329 | #define BP_POWER_LOOPCTRL_DC1_FF 8 | ||
| 330 | #define BM_POWER_LOOPCTRL_DC1_FF 0x700 | ||
| 331 | #define BF_POWER_LOOPCTRL_DC1_FF(v) (((v) << 8) & 0x700) | ||
| 332 | #define BP_POWER_LOOPCTRL_DC1_R 4 | ||
| 333 | #define BM_POWER_LOOPCTRL_DC1_R 0xf0 | ||
| 334 | #define BF_POWER_LOOPCTRL_DC1_R(v) (((v) << 4) & 0xf0) | ||
| 335 | #define BP_POWER_LOOPCTRL_DC1_C 0 | ||
| 336 | #define BM_POWER_LOOPCTRL_DC1_C 0x3 | ||
| 337 | #define BF_POWER_LOOPCTRL_DC1_C(v) (((v) << 0) & 0x3) | ||
| 338 | |||
| 339 | /** | ||
| 340 | * Register: HW_POWER_STS | ||
| 341 | * Address: 0x90 | ||
| 342 | * SCT: no | ||
| 343 | */ | ||
| 344 | #define HW_POWER_STS (*(volatile unsigned long *)(REGS_POWER_BASE + 0x90)) | ||
| 345 | #define BP_POWER_STS_BATT_CHRG_PRESENT 31 | ||
| 346 | #define BM_POWER_STS_BATT_CHRG_PRESENT 0x80000000 | ||
| 347 | #define BF_POWER_STS_BATT_CHRG_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 348 | #define BP_POWER_STS_MODE 20 | ||
| 349 | #define BM_POWER_STS_MODE 0x300000 | ||
| 350 | #define BF_POWER_STS_MODE(v) (((v) << 20) & 0x300000) | ||
| 351 | #define BP_POWER_STS_BATT_BO 16 | ||
| 352 | #define BM_POWER_STS_BATT_BO 0x10000 | ||
| 353 | #define BF_POWER_STS_BATT_BO(v) (((v) << 16) & 0x10000) | ||
| 354 | #define BP_POWER_STS_CHRGSTS 14 | ||
| 355 | #define BM_POWER_STS_CHRGSTS 0x4000 | ||
| 356 | #define BF_POWER_STS_CHRGSTS(v) (((v) << 14) & 0x4000) | ||
| 357 | #define BP_POWER_STS_DC2_OK 13 | ||
| 358 | #define BM_POWER_STS_DC2_OK 0x2000 | ||
| 359 | #define BF_POWER_STS_DC2_OK(v) (((v) << 13) & 0x2000) | ||
| 360 | #define BP_POWER_STS_DC1_OK 12 | ||
| 361 | #define BM_POWER_STS_DC1_OK 0x1000 | ||
| 362 | #define BF_POWER_STS_DC1_OK(v) (((v) << 12) & 0x1000) | ||
| 363 | #define BP_POWER_STS_VDDIO_BO 9 | ||
| 364 | #define BM_POWER_STS_VDDIO_BO 0x200 | ||
| 365 | #define BF_POWER_STS_VDDIO_BO(v) (((v) << 9) & 0x200) | ||
| 366 | #define BP_POWER_STS_VDDD_BO 8 | ||
| 367 | #define BM_POWER_STS_VDDD_BO 0x100 | ||
| 368 | #define BF_POWER_STS_VDDD_BO(v) (((v) << 8) & 0x100) | ||
| 369 | #define BP_POWER_STS_VDD5V_GT_VDDIO 4 | ||
| 370 | #define BM_POWER_STS_VDD5V_GT_VDDIO 0x10 | ||
| 371 | #define BF_POWER_STS_VDD5V_GT_VDDIO(v) (((v) << 4) & 0x10) | ||
| 372 | #define BP_POWER_STS_AVALID 3 | ||
| 373 | #define BM_POWER_STS_AVALID 0x8 | ||
| 374 | #define BF_POWER_STS_AVALID(v) (((v) << 3) & 0x8) | ||
| 375 | #define BP_POWER_STS_BVALID 2 | ||
| 376 | #define BM_POWER_STS_BVALID 0x4 | ||
| 377 | #define BF_POWER_STS_BVALID(v) (((v) << 2) & 0x4) | ||
| 378 | #define BP_POWER_STS_VBUSVALID 1 | ||
| 379 | #define BM_POWER_STS_VBUSVALID 0x2 | ||
| 380 | #define BF_POWER_STS_VBUSVALID(v) (((v) << 1) & 0x2) | ||
| 381 | #define BP_POWER_STS_SESSEND 0 | ||
| 382 | #define BM_POWER_STS_SESSEND 0x1 | ||
| 383 | #define BF_POWER_STS_SESSEND(v) (((v) << 0) & 0x1) | ||
| 384 | |||
| 385 | /** | ||
| 386 | * Register: HW_POWER_SPEEDTEMP | ||
| 387 | * Address: 0xa0 | ||
| 388 | * SCT: yes | ||
| 389 | */ | ||
| 390 | #define HW_POWER_SPEEDTEMP (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x0)) | ||
| 391 | #define HW_POWER_SPEEDTEMP_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x4)) | ||
| 392 | #define HW_POWER_SPEEDTEMP_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x8)) | ||
| 393 | #define HW_POWER_SPEEDTEMP_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0xc)) | ||
| 394 | #define BP_POWER_SPEEDTEMP_SPEED_STS1 24 | ||
| 395 | #define BM_POWER_SPEEDTEMP_SPEED_STS1 0xff000000 | ||
| 396 | #define BF_POWER_SPEEDTEMP_SPEED_STS1(v) (((v) << 24) & 0xff000000) | ||
| 397 | #define BP_POWER_SPEEDTEMP_SPEED_STS2 16 | ||
| 398 | #define BM_POWER_SPEEDTEMP_SPEED_STS2 0xff0000 | ||
| 399 | #define BF_POWER_SPEEDTEMP_SPEED_STS2(v) (((v) << 16) & 0xff0000) | ||
| 400 | #define BP_POWER_SPEEDTEMP_TEMP_STS 8 | ||
| 401 | #define BM_POWER_SPEEDTEMP_TEMP_STS 0xf00 | ||
| 402 | #define BF_POWER_SPEEDTEMP_TEMP_STS(v) (((v) << 8) & 0xf00) | ||
| 403 | #define BP_POWER_SPEEDTEMP_SPEED_CTRL 4 | ||
| 404 | #define BM_POWER_SPEEDTEMP_SPEED_CTRL 0x30 | ||
| 405 | #define BF_POWER_SPEEDTEMP_SPEED_CTRL(v) (((v) << 4) & 0x30) | ||
| 406 | #define BP_POWER_SPEEDTEMP_TEMP_CTRL 0 | ||
| 407 | #define BM_POWER_SPEEDTEMP_TEMP_CTRL 0xf | ||
| 408 | #define BF_POWER_SPEEDTEMP_TEMP_CTRL(v) (((v) << 0) & 0xf) | ||
| 409 | |||
| 410 | /** | ||
| 411 | * Register: HW_POWER_BATTMONITOR | ||
| 412 | * Address: 0xb0 | ||
| 413 | * SCT: no | ||
| 414 | */ | ||
| 415 | #define HW_POWER_BATTMONITOR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0)) | ||
| 416 | #define BP_POWER_BATTMONITOR_BATT_VAL 16 | ||
| 417 | #define BM_POWER_BATTMONITOR_BATT_VAL 0x3ff0000 | ||
| 418 | #define BF_POWER_BATTMONITOR_BATT_VAL(v) (((v) << 16) & 0x3ff0000) | ||
| 419 | #define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT 9 | ||
| 420 | #define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT 0x200 | ||
| 421 | #define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v) (((v) << 9) & 0x200) | ||
| 422 | #define BP_POWER_BATTMONITOR_BRWNOUT_PWD 8 | ||
| 423 | #define BM_POWER_BATTMONITOR_BRWNOUT_PWD 0x100 | ||
| 424 | #define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v) (((v) << 8) & 0x100) | ||
| 425 | #define BP_POWER_BATTMONITOR_BRWNOUT_LVL 0 | ||
| 426 | #define BM_POWER_BATTMONITOR_BRWNOUT_LVL 0xf | ||
| 427 | #define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v) (((v) << 0) & 0xf) | ||
| 428 | |||
| 429 | /** | ||
| 430 | * Register: HW_POWER_RESET | ||
| 431 | * Address: 0xc0 | ||
| 432 | * SCT: yes | ||
| 433 | */ | ||
| 434 | #define HW_POWER_RESET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x0)) | ||
| 435 | #define HW_POWER_RESET_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x4)) | ||
| 436 | #define HW_POWER_RESET_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x8)) | ||
| 437 | #define HW_POWER_RESET_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0xc)) | ||
| 438 | #define BP_POWER_RESET_UNLOCK 16 | ||
| 439 | #define BM_POWER_RESET_UNLOCK 0xffff0000 | ||
| 440 | #define BV_POWER_RESET_UNLOCK__KEY 0x3e77 | ||
| 441 | #define BF_POWER_RESET_UNLOCK(v) (((v) << 16) & 0xffff0000) | ||
| 442 | #define BF_POWER_RESET_UNLOCK_V(v) ((BV_POWER_RESET_UNLOCK__##v << 16) & 0xffff0000) | ||
| 443 | #define BP_POWER_RESET_PWD_OFF 4 | ||
| 444 | #define BM_POWER_RESET_PWD_OFF 0x10 | ||
| 445 | #define BF_POWER_RESET_PWD_OFF(v) (((v) << 4) & 0x10) | ||
| 446 | #define BP_POWER_RESET_POR 3 | ||
| 447 | #define BM_POWER_RESET_POR 0x8 | ||
| 448 | #define BF_POWER_RESET_POR(v) (((v) << 3) & 0x8) | ||
| 449 | #define BP_POWER_RESET_PWD 2 | ||
| 450 | #define BM_POWER_RESET_PWD 0x4 | ||
| 451 | #define BF_POWER_RESET_PWD(v) (((v) << 2) & 0x4) | ||
| 452 | #define BP_POWER_RESET_RST_DIG 1 | ||
| 453 | #define BM_POWER_RESET_RST_DIG 0x2 | ||
| 454 | #define BF_POWER_RESET_RST_DIG(v) (((v) << 1) & 0x2) | ||
| 455 | #define BP_POWER_RESET_RST_ALL 0 | ||
| 456 | #define BM_POWER_RESET_RST_ALL 0x1 | ||
| 457 | #define BF_POWER_RESET_RST_ALL(v) (((v) << 0) & 0x1) | ||
| 458 | |||
| 459 | /** | ||
| 460 | * Register: HW_POWER_DEBUG | ||
| 461 | * Address: 0xd0 | ||
| 462 | * SCT: yes | ||
| 463 | */ | ||
| 464 | #define HW_POWER_DEBUG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x0)) | ||
| 465 | #define HW_POWER_DEBUG_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x4)) | ||
| 466 | #define HW_POWER_DEBUG_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x8)) | ||
| 467 | #define HW_POWER_DEBUG_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0xc)) | ||
| 468 | #define BP_POWER_DEBUG_ENCTRLVBUS 4 | ||
| 469 | #define BM_POWER_DEBUG_ENCTRLVBUS 0x10 | ||
| 470 | #define BF_POWER_DEBUG_ENCTRLVBUS(v) (((v) << 4) & 0x10) | ||
| 471 | #define BP_POWER_DEBUG_VBUSVALIDPIOLOCK 3 | ||
| 472 | #define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x8 | ||
| 473 | #define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v) (((v) << 3) & 0x8) | ||
| 474 | #define BP_POWER_DEBUG_AVALIDPIOLOCK 2 | ||
| 475 | #define BM_POWER_DEBUG_AVALIDPIOLOCK 0x4 | ||
| 476 | #define BF_POWER_DEBUG_AVALIDPIOLOCK(v) (((v) << 2) & 0x4) | ||
| 477 | #define BP_POWER_DEBUG_BVALIDPIOLOCK 1 | ||
| 478 | #define BM_POWER_DEBUG_BVALIDPIOLOCK 0x2 | ||
| 479 | #define BF_POWER_DEBUG_BVALIDPIOLOCK(v) (((v) << 1) & 0x2) | ||
| 480 | #define BP_POWER_DEBUG_SESSENDPIOLOCK 0 | ||
| 481 | #define BM_POWER_DEBUG_SESSENDPIOLOCK 0x1 | ||
| 482 | #define BF_POWER_DEBUG_SESSENDPIOLOCK(v) (((v) << 0) & 0x1) | ||
| 483 | |||
| 484 | #endif /* __HEADERGEN__STMP3600__POWER__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-pwm.h b/firmware/target/arm/imx233/regs/stmp3600/regs-pwm.h new file mode 100644 index 0000000000..72d456fd10 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-pwm.h | |||
| @@ -0,0 +1,134 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__PWM__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__PWM__H__ | ||
| 25 | |||
| 26 | #define REGS_PWM_BASE (0x80064000) | ||
| 27 | |||
| 28 | #define REGS_PWM_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_PWM_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_PWM_CTRL (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_PWM_CTRL_SET (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_PWM_CTRL_CLR (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_PWM_CTRL_TOG (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_PWM_CTRL_SFTRST 31 | ||
| 40 | #define BM_PWM_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_PWM_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_PWM_CTRL_CLKGATE 30 | ||
| 43 | #define BM_PWM_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_PWM_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_PWM_CTRL_PWM4_PRESENT 29 | ||
| 46 | #define BM_PWM_CTRL_PWM4_PRESENT 0x20000000 | ||
| 47 | #define BF_PWM_CTRL_PWM4_PRESENT(v) (((v) << 29) & 0x20000000) | ||
| 48 | #define BP_PWM_CTRL_PWM3_PRESENT 28 | ||
| 49 | #define BM_PWM_CTRL_PWM3_PRESENT 0x10000000 | ||
| 50 | #define BF_PWM_CTRL_PWM3_PRESENT(v) (((v) << 28) & 0x10000000) | ||
| 51 | #define BP_PWM_CTRL_PWM2_PRESENT 27 | ||
| 52 | #define BM_PWM_CTRL_PWM2_PRESENT 0x8000000 | ||
| 53 | #define BF_PWM_CTRL_PWM2_PRESENT(v) (((v) << 27) & 0x8000000) | ||
| 54 | #define BP_PWM_CTRL_PWM1_PRESENT 26 | ||
| 55 | #define BM_PWM_CTRL_PWM1_PRESENT 0x4000000 | ||
| 56 | #define BF_PWM_CTRL_PWM1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
| 57 | #define BP_PWM_CTRL_PWM0_PRESENT 25 | ||
| 58 | #define BM_PWM_CTRL_PWM0_PRESENT 0x2000000 | ||
| 59 | #define BF_PWM_CTRL_PWM0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
| 60 | #define BP_PWM_CTRL_PWM4_ENABLE 4 | ||
| 61 | #define BM_PWM_CTRL_PWM4_ENABLE 0x10 | ||
| 62 | #define BF_PWM_CTRL_PWM4_ENABLE(v) (((v) << 4) & 0x10) | ||
| 63 | #define BP_PWM_CTRL_PWM3_ENABLE 3 | ||
| 64 | #define BM_PWM_CTRL_PWM3_ENABLE 0x8 | ||
| 65 | #define BF_PWM_CTRL_PWM3_ENABLE(v) (((v) << 3) & 0x8) | ||
| 66 | #define BP_PWM_CTRL_PWM2_ENABLE 2 | ||
| 67 | #define BM_PWM_CTRL_PWM2_ENABLE 0x4 | ||
| 68 | #define BF_PWM_CTRL_PWM2_ENABLE(v) (((v) << 2) & 0x4) | ||
| 69 | #define BP_PWM_CTRL_PWM1_ENABLE 1 | ||
| 70 | #define BM_PWM_CTRL_PWM1_ENABLE 0x2 | ||
| 71 | #define BF_PWM_CTRL_PWM1_ENABLE(v) (((v) << 1) & 0x2) | ||
| 72 | #define BP_PWM_CTRL_PWM0_ENABLE 0 | ||
| 73 | #define BM_PWM_CTRL_PWM0_ENABLE 0x1 | ||
| 74 | #define BF_PWM_CTRL_PWM0_ENABLE(v) (((v) << 0) & 0x1) | ||
| 75 | |||
| 76 | /** | ||
| 77 | * Register: HW_PWM_ACTIVEn | ||
| 78 | * Address: 0x10+n*0x20 | ||
| 79 | * SCT: yes | ||
| 80 | */ | ||
| 81 | #define HW_PWM_ACTIVEn(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x0)) | ||
| 82 | #define HW_PWM_ACTIVEn_SET(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x4)) | ||
| 83 | #define HW_PWM_ACTIVEn_CLR(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x8)) | ||
| 84 | #define HW_PWM_ACTIVEn_TOG(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0xc)) | ||
| 85 | #define BP_PWM_ACTIVEn_INACTIVE 16 | ||
| 86 | #define BM_PWM_ACTIVEn_INACTIVE 0xffff0000 | ||
| 87 | #define BF_PWM_ACTIVEn_INACTIVE(v) (((v) << 16) & 0xffff0000) | ||
| 88 | #define BP_PWM_ACTIVEn_ACTIVE 0 | ||
| 89 | #define BM_PWM_ACTIVEn_ACTIVE 0xffff | ||
| 90 | #define BF_PWM_ACTIVEn_ACTIVE(v) (((v) << 0) & 0xffff) | ||
| 91 | |||
| 92 | /** | ||
| 93 | * Register: HW_PWM_PERIODn | ||
| 94 | * Address: 0x20+n*0x20 | ||
| 95 | * SCT: yes | ||
| 96 | */ | ||
| 97 | #define HW_PWM_PERIODn(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x0)) | ||
| 98 | #define HW_PWM_PERIODn_SET(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x4)) | ||
| 99 | #define HW_PWM_PERIODn_CLR(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x8)) | ||
| 100 | #define HW_PWM_PERIODn_TOG(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0xc)) | ||
| 101 | #define BP_PWM_PERIODn_MATT 23 | ||
| 102 | #define BM_PWM_PERIODn_MATT 0x800000 | ||
| 103 | #define BF_PWM_PERIODn_MATT(v) (((v) << 23) & 0x800000) | ||
| 104 | #define BP_PWM_PERIODn_CDIV 20 | ||
| 105 | #define BM_PWM_PERIODn_CDIV 0x700000 | ||
| 106 | #define BV_PWM_PERIODn_CDIV__DIV_1 0x0 | ||
| 107 | #define BV_PWM_PERIODn_CDIV__DIV_2 0x1 | ||
| 108 | #define BV_PWM_PERIODn_CDIV__DIV_4 0x2 | ||
| 109 | #define BV_PWM_PERIODn_CDIV__DIV_8 0x3 | ||
| 110 | #define BV_PWM_PERIODn_CDIV__DIV_16 0x4 | ||
| 111 | #define BV_PWM_PERIODn_CDIV__DIV_64 0x5 | ||
| 112 | #define BV_PWM_PERIODn_CDIV__DIV_256 0x6 | ||
| 113 | #define BV_PWM_PERIODn_CDIV__DIV_1024 0x7 | ||
| 114 | #define BF_PWM_PERIODn_CDIV(v) (((v) << 20) & 0x700000) | ||
| 115 | #define BF_PWM_PERIODn_CDIV_V(v) ((BV_PWM_PERIODn_CDIV__##v << 20) & 0x700000) | ||
| 116 | #define BP_PWM_PERIODn_INACTIVE_STATE 18 | ||
| 117 | #define BM_PWM_PERIODn_INACTIVE_STATE 0xc0000 | ||
| 118 | #define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0 | ||
| 119 | #define BV_PWM_PERIODn_INACTIVE_STATE__0 0x2 | ||
| 120 | #define BV_PWM_PERIODn_INACTIVE_STATE__1 0x3 | ||
| 121 | #define BF_PWM_PERIODn_INACTIVE_STATE(v) (((v) << 18) & 0xc0000) | ||
| 122 | #define BF_PWM_PERIODn_INACTIVE_STATE_V(v) ((BV_PWM_PERIODn_INACTIVE_STATE__##v << 18) & 0xc0000) | ||
| 123 | #define BP_PWM_PERIODn_ACTIVE_STATE 16 | ||
| 124 | #define BM_PWM_PERIODn_ACTIVE_STATE 0x30000 | ||
| 125 | #define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z 0x0 | ||
| 126 | #define BV_PWM_PERIODn_ACTIVE_STATE__0 0x2 | ||
| 127 | #define BV_PWM_PERIODn_ACTIVE_STATE__1 0x3 | ||
| 128 | #define BF_PWM_PERIODn_ACTIVE_STATE(v) (((v) << 16) & 0x30000) | ||
| 129 | #define BF_PWM_PERIODn_ACTIVE_STATE_V(v) ((BV_PWM_PERIODn_ACTIVE_STATE__##v << 16) & 0x30000) | ||
| 130 | #define BP_PWM_PERIODn_PERIOD 0 | ||
| 131 | #define BM_PWM_PERIODn_PERIOD 0xffff | ||
| 132 | #define BF_PWM_PERIODn_PERIOD(v) (((v) << 0) & 0xffff) | ||
| 133 | |||
| 134 | #endif /* __HEADERGEN__STMP3600__PWM__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h new file mode 100644 index 0000000000..8661e75706 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h | |||
| @@ -0,0 +1,304 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__RTC__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__RTC__H__ | ||
| 25 | |||
| 26 | #define REGS_RTC_BASE (0x8005c000) | ||
| 27 | |||
| 28 | #define REGS_RTC_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_RTC_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_RTC_CTRL (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_RTC_CTRL_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_RTC_CTRL_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_RTC_CTRL_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_RTC_CTRL_SFTRST 31 | ||
| 40 | #define BM_RTC_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_RTC_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_RTC_CTRL_CLKGATE 30 | ||
| 43 | #define BM_RTC_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_RTC_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_RTC_CTRL_CLKDIV 24 | ||
| 46 | #define BM_RTC_CTRL_CLKDIV 0xf000000 | ||
| 47 | #define BF_RTC_CTRL_CLKDIV(v) (((v) << 24) & 0xf000000) | ||
| 48 | #define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG 6 | ||
| 49 | #define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG 0x40 | ||
| 50 | #define BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__NORMAL 0x0 | ||
| 51 | #define BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__NO_COPY 0x1 | ||
| 52 | #define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v) (((v) << 6) & 0x40) | ||
| 53 | #define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG_V(v) ((BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__##v << 6) & 0x40) | ||
| 54 | #define BP_RTC_CTRL_FORCE_UPDATE 5 | ||
| 55 | #define BM_RTC_CTRL_FORCE_UPDATE 0x20 | ||
| 56 | #define BV_RTC_CTRL_FORCE_UPDATE__NORMAL 0x0 | ||
| 57 | #define BV_RTC_CTRL_FORCE_UPDATE__FORCE_COPY 0x1 | ||
| 58 | #define BF_RTC_CTRL_FORCE_UPDATE(v) (((v) << 5) & 0x20) | ||
| 59 | #define BF_RTC_CTRL_FORCE_UPDATE_V(v) ((BV_RTC_CTRL_FORCE_UPDATE__##v << 5) & 0x20) | ||
| 60 | #define BP_RTC_CTRL_WATCHDOGEN 4 | ||
| 61 | #define BM_RTC_CTRL_WATCHDOGEN 0x10 | ||
| 62 | #define BF_RTC_CTRL_WATCHDOGEN(v) (((v) << 4) & 0x10) | ||
| 63 | #define BP_RTC_CTRL_ONEMSEC_IRQ 3 | ||
| 64 | #define BM_RTC_CTRL_ONEMSEC_IRQ 0x8 | ||
| 65 | #define BF_RTC_CTRL_ONEMSEC_IRQ(v) (((v) << 3) & 0x8) | ||
| 66 | #define BP_RTC_CTRL_ALARM_IRQ 2 | ||
| 67 | #define BM_RTC_CTRL_ALARM_IRQ 0x4 | ||
| 68 | #define BF_RTC_CTRL_ALARM_IRQ(v) (((v) << 2) & 0x4) | ||
| 69 | #define BP_RTC_CTRL_ONEMSEC_IRQ_EN 1 | ||
| 70 | #define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x2 | ||
| 71 | #define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v) (((v) << 1) & 0x2) | ||
| 72 | #define BP_RTC_CTRL_ALARM_IRQ_EN 0 | ||
| 73 | #define BM_RTC_CTRL_ALARM_IRQ_EN 0x1 | ||
| 74 | #define BF_RTC_CTRL_ALARM_IRQ_EN(v) (((v) << 0) & 0x1) | ||
| 75 | |||
| 76 | /** | ||
| 77 | * Register: HW_RTC_STAT | ||
| 78 | * Address: 0x10 | ||
| 79 | * SCT: no | ||
| 80 | */ | ||
| 81 | #define HW_RTC_STAT (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10)) | ||
| 82 | #define BP_RTC_STAT_RTC_PRESENT 31 | ||
| 83 | #define BM_RTC_STAT_RTC_PRESENT 0x80000000 | ||
| 84 | #define BF_RTC_STAT_RTC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 85 | #define BP_RTC_STAT_ALARM_PRESENT 30 | ||
| 86 | #define BM_RTC_STAT_ALARM_PRESENT 0x40000000 | ||
| 87 | #define BF_RTC_STAT_ALARM_PRESENT(v) (((v) << 30) & 0x40000000) | ||
| 88 | #define BP_RTC_STAT_WATCHDOG_PRESENT 29 | ||
| 89 | #define BM_RTC_STAT_WATCHDOG_PRESENT 0x20000000 | ||
| 90 | #define BF_RTC_STAT_WATCHDOG_PRESENT(v) (((v) << 29) & 0x20000000) | ||
| 91 | #define BP_RTC_STAT_XTAL32768_PRESENT 28 | ||
| 92 | #define BM_RTC_STAT_XTAL32768_PRESENT 0x10000000 | ||
| 93 | #define BF_RTC_STAT_XTAL32768_PRESENT(v) (((v) << 28) & 0x10000000) | ||
| 94 | #define BP_RTC_STAT_STALE_REGS 16 | ||
| 95 | #define BM_RTC_STAT_STALE_REGS 0x3f0000 | ||
| 96 | #define BF_RTC_STAT_STALE_REGS(v) (((v) << 16) & 0x3f0000) | ||
| 97 | #define BP_RTC_STAT_NEW_REGS 8 | ||
| 98 | #define BM_RTC_STAT_NEW_REGS 0x3f00 | ||
| 99 | #define BF_RTC_STAT_NEW_REGS(v) (((v) << 8) & 0x3f00) | ||
| 100 | #define BP_RTC_STAT_FUSE_UNLOCK 1 | ||
| 101 | #define BM_RTC_STAT_FUSE_UNLOCK 0x2 | ||
| 102 | #define BF_RTC_STAT_FUSE_UNLOCK(v) (((v) << 1) & 0x2) | ||
| 103 | #define BP_RTC_STAT_FUSE_DONE 0 | ||
| 104 | #define BM_RTC_STAT_FUSE_DONE 0x1 | ||
| 105 | #define BF_RTC_STAT_FUSE_DONE(v) (((v) << 0) & 0x1) | ||
| 106 | |||
| 107 | /** | ||
| 108 | * Register: HW_RTC_MILLISECONDS | ||
| 109 | * Address: 0x20 | ||
| 110 | * SCT: yes | ||
| 111 | */ | ||
| 112 | #define HW_RTC_MILLISECONDS (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x0)) | ||
| 113 | #define HW_RTC_MILLISECONDS_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x4)) | ||
| 114 | #define HW_RTC_MILLISECONDS_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x8)) | ||
| 115 | #define HW_RTC_MILLISECONDS_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0xc)) | ||
| 116 | #define BP_RTC_MILLISECONDS_COUNT 0 | ||
| 117 | #define BM_RTC_MILLISECONDS_COUNT 0xffffffff | ||
| 118 | #define BF_RTC_MILLISECONDS_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 119 | |||
| 120 | /** | ||
| 121 | * Register: HW_RTC_SECONDS | ||
| 122 | * Address: 0x30 | ||
| 123 | * SCT: yes | ||
| 124 | */ | ||
| 125 | #define HW_RTC_SECONDS (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x0)) | ||
| 126 | #define HW_RTC_SECONDS_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x4)) | ||
| 127 | #define HW_RTC_SECONDS_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x8)) | ||
| 128 | #define HW_RTC_SECONDS_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0xc)) | ||
| 129 | #define BP_RTC_SECONDS_COUNT 0 | ||
| 130 | #define BM_RTC_SECONDS_COUNT 0xffffffff | ||
| 131 | #define BF_RTC_SECONDS_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 132 | |||
| 133 | /** | ||
| 134 | * Register: HW_RTC_ALARM | ||
| 135 | * Address: 0x40 | ||
| 136 | * SCT: yes | ||
| 137 | */ | ||
| 138 | #define HW_RTC_ALARM (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x0)) | ||
| 139 | #define HW_RTC_ALARM_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x4)) | ||
| 140 | #define HW_RTC_ALARM_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x8)) | ||
| 141 | #define HW_RTC_ALARM_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0xc)) | ||
| 142 | #define BP_RTC_ALARM_VALUE 0 | ||
| 143 | #define BM_RTC_ALARM_VALUE 0xffffffff | ||
| 144 | #define BF_RTC_ALARM_VALUE(v) (((v) << 0) & 0xffffffff) | ||
| 145 | |||
| 146 | /** | ||
| 147 | * Register: HW_RTC_WATCHDOG | ||
| 148 | * Address: 0x50 | ||
| 149 | * SCT: yes | ||
| 150 | */ | ||
| 151 | #define HW_RTC_WATCHDOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x0)) | ||
| 152 | #define HW_RTC_WATCHDOG_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x4)) | ||
| 153 | #define HW_RTC_WATCHDOG_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x8)) | ||
| 154 | #define HW_RTC_WATCHDOG_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0xc)) | ||
| 155 | #define BP_RTC_WATCHDOG_COUNT 0 | ||
| 156 | #define BM_RTC_WATCHDOG_COUNT 0xffffffff | ||
| 157 | #define BF_RTC_WATCHDOG_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 158 | |||
| 159 | /** | ||
| 160 | * Register: HW_RTC_PERSISTENT0 | ||
| 161 | * Address: 0x60 | ||
| 162 | * SCT: yes | ||
| 163 | */ | ||
| 164 | #define HW_RTC_PERSISTENT0 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x0)) | ||
| 165 | #define HW_RTC_PERSISTENT0_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x4)) | ||
| 166 | #define HW_RTC_PERSISTENT0_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x8)) | ||
| 167 | #define HW_RTC_PERSISTENT0_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0xc)) | ||
| 168 | #define BP_RTC_PERSISTENT0_GENERAL 16 | ||
| 169 | #define BM_RTC_PERSISTENT0_GENERAL 0xffff0000 | ||
| 170 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_BOOT 0x8000 | ||
| 171 | #define BV_RTC_PERSISTENT0_GENERAL__ENUMERATE_500MA_TWICE 0x4000 | ||
| 172 | #define BV_RTC_PERSISTENT0_GENERAL__USB_BOOT_PLAYER_MODE 0x2000 | ||
| 173 | #define BV_RTC_PERSISTENT0_GENERAL__SKIP_CHECKDISK 0x1000 | ||
| 174 | #define BV_RTC_PERSISTENT0_GENERAL__USB_LOW_POWER_MODE 0x800 | ||
| 175 | #define BV_RTC_PERSISTENT0_GENERAL__OTG_HNP_BIT 0x400 | ||
| 176 | #define BV_RTC_PERSISTENT0_GENERAL__OTG_ATL_ROLE_BIT 0x200 | ||
| 177 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_CS_HI 0x100 | ||
| 178 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_CS_LO 0x80 | ||
| 179 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_3 0x40 | ||
| 180 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_2 0x20 | ||
| 181 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_1 0x10 | ||
| 182 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_0 0x8 | ||
| 183 | #define BV_RTC_PERSISTENT0_GENERAL__ETM_ENABLE 0x4 | ||
| 184 | #define BF_RTC_PERSISTENT0_GENERAL(v) (((v) << 16) & 0xffff0000) | ||
| 185 | #define BF_RTC_PERSISTENT0_GENERAL_V(v) ((BV_RTC_PERSISTENT0_GENERAL__##v << 16) & 0xffff0000) | ||
| 186 | #define BP_RTC_PERSISTENT0_DCDC_CTRL 6 | ||
| 187 | #define BM_RTC_PERSISTENT0_DCDC_CTRL 0xffc0 | ||
| 188 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__SD_PRESENT 0x200 | ||
| 189 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__LOWBAT_3P0 0x100 | ||
| 190 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__SELFBIAS_PWRUP 0x80 | ||
| 191 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__AUTO_RESTART 0x40 | ||
| 192 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__DETECT_LOWBAT 0x20 | ||
| 193 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__DROP_BIAS1 0x10 | ||
| 194 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__DROP_BIAS2 0x8 | ||
| 195 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__SPARE 0x4 | ||
| 196 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__DISABLE_XTALSTOP 0x2 | ||
| 197 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__SPARE2 0x1 | ||
| 198 | #define BF_RTC_PERSISTENT0_DCDC_CTRL(v) (((v) << 6) & 0xffc0) | ||
| 199 | #define BF_RTC_PERSISTENT0_DCDC_CTRL_V(v) ((BV_RTC_PERSISTENT0_DCDC_CTRL__##v << 6) & 0xffc0) | ||
| 200 | #define BP_RTC_PERSISTENT0_XTAL32_PDOWN 5 | ||
| 201 | #define BM_RTC_PERSISTENT0_XTAL32_PDOWN 0x20 | ||
| 202 | #define BF_RTC_PERSISTENT0_XTAL32_PDOWN(v) (((v) << 5) & 0x20) | ||
| 203 | #define BP_RTC_PERSISTENT0_XTAL24_PDOWN 4 | ||
| 204 | #define BM_RTC_PERSISTENT0_XTAL24_PDOWN 0x10 | ||
| 205 | #define BF_RTC_PERSISTENT0_XTAL24_PDOWN(v) (((v) << 4) & 0x10) | ||
| 206 | #define BP_RTC_PERSISTENT0_ALARM_WAKE_EN 3 | ||
| 207 | #define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x8 | ||
| 208 | #define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v) (((v) << 3) & 0x8) | ||
| 209 | #define BP_RTC_PERSISTENT0_ALARM_EN 2 | ||
| 210 | #define BM_RTC_PERSISTENT0_ALARM_EN 0x4 | ||
| 211 | #define BF_RTC_PERSISTENT0_ALARM_EN(v) (((v) << 2) & 0x4) | ||
| 212 | #define BP_RTC_PERSISTENT0_ALARM_WAKE 1 | ||
| 213 | #define BM_RTC_PERSISTENT0_ALARM_WAKE 0x2 | ||
| 214 | #define BF_RTC_PERSISTENT0_ALARM_WAKE(v) (((v) << 1) & 0x2) | ||
| 215 | #define BP_RTC_PERSISTENT0_CLOCKSOURCE 0 | ||
| 216 | #define BM_RTC_PERSISTENT0_CLOCKSOURCE 0x1 | ||
| 217 | #define BF_RTC_PERSISTENT0_CLOCKSOURCE(v) (((v) << 0) & 0x1) | ||
| 218 | |||
| 219 | /** | ||
| 220 | * Register: HW_RTC_PERSISTENT1 | ||
| 221 | * Address: 0x70 | ||
| 222 | * SCT: yes | ||
| 223 | */ | ||
| 224 | #define HW_RTC_PERSISTENT1 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x0)) | ||
| 225 | #define HW_RTC_PERSISTENT1_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x4)) | ||
| 226 | #define HW_RTC_PERSISTENT1_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x8)) | ||
| 227 | #define HW_RTC_PERSISTENT1_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0xc)) | ||
| 228 | #define BP_RTC_PERSISTENT1_GENERAL 0 | ||
| 229 | #define BM_RTC_PERSISTENT1_GENERAL 0xffffffff | ||
| 230 | #define BF_RTC_PERSISTENT1_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
| 231 | |||
| 232 | /** | ||
| 233 | * Register: HW_RTC_PERSISTENT2 | ||
| 234 | * Address: 0x80 | ||
| 235 | * SCT: yes | ||
| 236 | */ | ||
| 237 | #define HW_RTC_PERSISTENT2 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x0)) | ||
| 238 | #define HW_RTC_PERSISTENT2_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x4)) | ||
| 239 | #define HW_RTC_PERSISTENT2_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x8)) | ||
| 240 | #define HW_RTC_PERSISTENT2_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0xc)) | ||
| 241 | #define BP_RTC_PERSISTENT2_SRAM_LO 0 | ||
| 242 | #define BM_RTC_PERSISTENT2_SRAM_LO 0xffffffff | ||
| 243 | #define BV_RTC_PERSISTENT2_SRAM_LO__WARM_BOOT 0x80000000 | ||
| 244 | #define BF_RTC_PERSISTENT2_SRAM_LO(v) (((v) << 0) & 0xffffffff) | ||
| 245 | #define BF_RTC_PERSISTENT2_SRAM_LO_V(v) ((BV_RTC_PERSISTENT2_SRAM_LO__##v << 0) & 0xffffffff) | ||
| 246 | |||
| 247 | /** | ||
| 248 | * Register: HW_RTC_PERSISTENT3 | ||
| 249 | * Address: 0x90 | ||
| 250 | * SCT: yes | ||
| 251 | */ | ||
| 252 | #define HW_RTC_PERSISTENT3 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x0)) | ||
| 253 | #define HW_RTC_PERSISTENT3_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x4)) | ||
| 254 | #define HW_RTC_PERSISTENT3_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x8)) | ||
| 255 | #define HW_RTC_PERSISTENT3_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0xc)) | ||
| 256 | #define BP_RTC_PERSISTENT3_SRAM_HI 0 | ||
| 257 | #define BM_RTC_PERSISTENT3_SRAM_HI 0xffffffff | ||
| 258 | #define BF_RTC_PERSISTENT3_SRAM_HI(v) (((v) << 0) & 0xffffffff) | ||
| 259 | |||
| 260 | /** | ||
| 261 | * Register: HW_RTC_DEBUG | ||
| 262 | * Address: 0xa0 | ||
| 263 | * SCT: yes | ||
| 264 | */ | ||
| 265 | #define HW_RTC_DEBUG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x0)) | ||
| 266 | #define HW_RTC_DEBUG_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x4)) | ||
| 267 | #define HW_RTC_DEBUG_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x8)) | ||
| 268 | #define HW_RTC_DEBUG_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0xc)) | ||
| 269 | #define BP_RTC_DEBUG_WATCHDOG_RESET_MASK 1 | ||
| 270 | #define BM_RTC_DEBUG_WATCHDOG_RESET_MASK 0x2 | ||
| 271 | #define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v) (((v) << 1) & 0x2) | ||
| 272 | #define BP_RTC_DEBUG_WATCHDOG_RESET 0 | ||
| 273 | #define BM_RTC_DEBUG_WATCHDOG_RESET 0x1 | ||
| 274 | #define BF_RTC_DEBUG_WATCHDOG_RESET(v) (((v) << 0) & 0x1) | ||
| 275 | |||
| 276 | /** | ||
| 277 | * Register: HW_RTC_UNLOCK | ||
| 278 | * Address: 0x200 | ||
| 279 | * SCT: yes | ||
| 280 | */ | ||
| 281 | #define HW_RTC_UNLOCK (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0x0)) | ||
| 282 | #define HW_RTC_UNLOCK_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0x4)) | ||
| 283 | #define HW_RTC_UNLOCK_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0x8)) | ||
| 284 | #define HW_RTC_UNLOCK_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0xc)) | ||
| 285 | #define BP_RTC_UNLOCK_KEY 0 | ||
| 286 | #define BM_RTC_UNLOCK_KEY 0xffffffff | ||
| 287 | #define BV_RTC_UNLOCK_KEY__VAL 0xc6a83957 | ||
| 288 | #define BF_RTC_UNLOCK_KEY(v) (((v) << 0) & 0xffffffff) | ||
| 289 | #define BF_RTC_UNLOCK_KEY_V(v) ((BV_RTC_UNLOCK_KEY__##v << 0) & 0xffffffff) | ||
| 290 | |||
| 291 | /** | ||
| 292 | * Register: HW_RTC_LASERFUSEn | ||
| 293 | * Address: 0x300+n*0x10 | ||
| 294 | * SCT: yes | ||
| 295 | */ | ||
| 296 | #define HW_RTC_LASERFUSEn(n) (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0x0)) | ||
| 297 | #define HW_RTC_LASERFUSEn_SET(n) (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0x4)) | ||
| 298 | #define HW_RTC_LASERFUSEn_CLR(n) (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0x8)) | ||
| 299 | #define HW_RTC_LASERFUSEn_TOG(n) (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0xc)) | ||
| 300 | #define BP_RTC_LASERFUSEn_BITS 0 | ||
| 301 | #define BM_RTC_LASERFUSEn_BITS 0xffffffff | ||
| 302 | #define BF_RTC_LASERFUSEn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 303 | |||
| 304 | #endif /* __HEADERGEN__STMP3600__RTC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-spdif.h b/firmware/target/arm/imx233/regs/stmp3600/regs-spdif.h new file mode 100644 index 0000000000..32e88b37cd --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-spdif.h | |||
| @@ -0,0 +1,165 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__SPDIF__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__SPDIF__H__ | ||
| 25 | |||
| 26 | #define REGS_SPDIF_BASE (0x80054000) | ||
| 27 | |||
| 28 | #define REGS_SPDIF_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_SPDIF_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_SPDIF_CTRL (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_SPDIF_CTRL_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_SPDIF_CTRL_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_SPDIF_CTRL_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_SPDIF_CTRL_SFTRST 31 | ||
| 40 | #define BM_SPDIF_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_SPDIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_SPDIF_CTRL_CLKGATE 30 | ||
| 43 | #define BM_SPDIF_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_SPDIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_SPDIF_CTRL_DMAWAIT_COUNT 16 | ||
| 46 | #define BM_SPDIF_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
| 47 | #define BF_SPDIF_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
| 48 | #define BP_SPDIF_CTRL_WAIT_END_XFER 5 | ||
| 49 | #define BM_SPDIF_CTRL_WAIT_END_XFER 0x20 | ||
| 50 | #define BF_SPDIF_CTRL_WAIT_END_XFER(v) (((v) << 5) & 0x20) | ||
| 51 | #define BP_SPDIF_CTRL_WORD_LENGTH 4 | ||
| 52 | #define BM_SPDIF_CTRL_WORD_LENGTH 0x10 | ||
| 53 | #define BF_SPDIF_CTRL_WORD_LENGTH(v) (((v) << 4) & 0x10) | ||
| 54 | #define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 3 | ||
| 55 | #define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x8 | ||
| 56 | #define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
| 57 | #define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 2 | ||
| 58 | #define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x4 | ||
| 59 | #define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) | ||
| 60 | #define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 1 | ||
| 61 | #define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x2 | ||
| 62 | #define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
| 63 | #define BP_SPDIF_CTRL_RUN 0 | ||
| 64 | #define BM_SPDIF_CTRL_RUN 0x1 | ||
| 65 | #define BF_SPDIF_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
| 66 | |||
| 67 | /** | ||
| 68 | * Register: HW_SPDIF_STAT | ||
| 69 | * Address: 0x10 | ||
| 70 | * SCT: no | ||
| 71 | */ | ||
| 72 | #define HW_SPDIF_STAT (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10)) | ||
| 73 | #define BP_SPDIF_STAT_PRESENT 31 | ||
| 74 | #define BM_SPDIF_STAT_PRESENT 0x80000000 | ||
| 75 | #define BF_SPDIF_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 76 | #define BP_SPDIF_STAT_END_XFER 0 | ||
| 77 | #define BM_SPDIF_STAT_END_XFER 0x1 | ||
| 78 | #define BF_SPDIF_STAT_END_XFER(v) (((v) << 0) & 0x1) | ||
| 79 | |||
| 80 | /** | ||
| 81 | * Register: HW_SPDIF_FRAMECTRL | ||
| 82 | * Address: 0x20 | ||
| 83 | * SCT: yes | ||
| 84 | */ | ||
| 85 | #define HW_SPDIF_FRAMECTRL (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x0)) | ||
| 86 | #define HW_SPDIF_FRAMECTRL_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x4)) | ||
| 87 | #define HW_SPDIF_FRAMECTRL_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x8)) | ||
| 88 | #define HW_SPDIF_FRAMECTRL_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0xc)) | ||
| 89 | #define BP_SPDIF_FRAMECTRL_V_CONFIG 17 | ||
| 90 | #define BM_SPDIF_FRAMECTRL_V_CONFIG 0x20000 | ||
| 91 | #define BF_SPDIF_FRAMECTRL_V_CONFIG(v) (((v) << 17) & 0x20000) | ||
| 92 | #define BP_SPDIF_FRAMECTRL_AUTO_MUTE 16 | ||
| 93 | #define BM_SPDIF_FRAMECTRL_AUTO_MUTE 0x10000 | ||
| 94 | #define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v) (((v) << 16) & 0x10000) | ||
| 95 | #define BP_SPDIF_FRAMECTRL_USER_DATA 14 | ||
| 96 | #define BM_SPDIF_FRAMECTRL_USER_DATA 0x4000 | ||
| 97 | #define BF_SPDIF_FRAMECTRL_USER_DATA(v) (((v) << 14) & 0x4000) | ||
| 98 | #define BP_SPDIF_FRAMECTRL_V 13 | ||
| 99 | #define BM_SPDIF_FRAMECTRL_V 0x2000 | ||
| 100 | #define BF_SPDIF_FRAMECTRL_V(v) (((v) << 13) & 0x2000) | ||
| 101 | #define BP_SPDIF_FRAMECTRL_L 12 | ||
| 102 | #define BM_SPDIF_FRAMECTRL_L 0x1000 | ||
| 103 | #define BF_SPDIF_FRAMECTRL_L(v) (((v) << 12) & 0x1000) | ||
| 104 | #define BP_SPDIF_FRAMECTRL_CC 4 | ||
| 105 | #define BM_SPDIF_FRAMECTRL_CC 0x7f0 | ||
| 106 | #define BF_SPDIF_FRAMECTRL_CC(v) (((v) << 4) & 0x7f0) | ||
| 107 | #define BP_SPDIF_FRAMECTRL_PRE 3 | ||
| 108 | #define BM_SPDIF_FRAMECTRL_PRE 0x8 | ||
| 109 | #define BF_SPDIF_FRAMECTRL_PRE(v) (((v) << 3) & 0x8) | ||
| 110 | #define BP_SPDIF_FRAMECTRL_COPY 2 | ||
| 111 | #define BM_SPDIF_FRAMECTRL_COPY 0x4 | ||
| 112 | #define BF_SPDIF_FRAMECTRL_COPY(v) (((v) << 2) & 0x4) | ||
| 113 | #define BP_SPDIF_FRAMECTRL_AUDIO 1 | ||
| 114 | #define BM_SPDIF_FRAMECTRL_AUDIO 0x2 | ||
| 115 | #define BF_SPDIF_FRAMECTRL_AUDIO(v) (((v) << 1) & 0x2) | ||
| 116 | #define BP_SPDIF_FRAMECTRL_PRO 0 | ||
| 117 | #define BM_SPDIF_FRAMECTRL_PRO 0x1 | ||
| 118 | #define BF_SPDIF_FRAMECTRL_PRO(v) (((v) << 0) & 0x1) | ||
| 119 | |||
| 120 | /** | ||
| 121 | * Register: HW_SPDIF_SRR | ||
| 122 | * Address: 0x30 | ||
| 123 | * SCT: yes | ||
| 124 | */ | ||
| 125 | #define HW_SPDIF_SRR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x0)) | ||
| 126 | #define HW_SPDIF_SRR_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x4)) | ||
| 127 | #define HW_SPDIF_SRR_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x8)) | ||
| 128 | #define HW_SPDIF_SRR_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0xc)) | ||
| 129 | #define BP_SPDIF_SRR_BASEMULT 28 | ||
| 130 | #define BM_SPDIF_SRR_BASEMULT 0x70000000 | ||
| 131 | #define BF_SPDIF_SRR_BASEMULT(v) (((v) << 28) & 0x70000000) | ||
| 132 | #define BP_SPDIF_SRR_RATE 0 | ||
| 133 | #define BM_SPDIF_SRR_RATE 0xfffff | ||
| 134 | #define BF_SPDIF_SRR_RATE(v) (((v) << 0) & 0xfffff) | ||
| 135 | |||
| 136 | /** | ||
| 137 | * Register: HW_SPDIF_DEBUG | ||
| 138 | * Address: 0x40 | ||
| 139 | * SCT: no | ||
| 140 | */ | ||
| 141 | #define HW_SPDIF_DEBUG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40)) | ||
| 142 | #define BP_SPDIF_DEBUG_DMA_PREQ 1 | ||
| 143 | #define BM_SPDIF_DEBUG_DMA_PREQ 0x2 | ||
| 144 | #define BF_SPDIF_DEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) | ||
| 145 | #define BP_SPDIF_DEBUG_FIFO_STATUS 0 | ||
| 146 | #define BM_SPDIF_DEBUG_FIFO_STATUS 0x1 | ||
| 147 | #define BF_SPDIF_DEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) | ||
| 148 | |||
| 149 | /** | ||
| 150 | * Register: HW_SPDIF_DATA | ||
| 151 | * Address: 0x50 | ||
| 152 | * SCT: yes | ||
| 153 | */ | ||
| 154 | #define HW_SPDIF_DATA (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x0)) | ||
| 155 | #define HW_SPDIF_DATA_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x4)) | ||
| 156 | #define HW_SPDIF_DATA_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x8)) | ||
| 157 | #define HW_SPDIF_DATA_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0xc)) | ||
| 158 | #define BP_SPDIF_DATA_HIGH 16 | ||
| 159 | #define BM_SPDIF_DATA_HIGH 0xffff0000 | ||
| 160 | #define BF_SPDIF_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
| 161 | #define BP_SPDIF_DATA_LOW 0 | ||
| 162 | #define BM_SPDIF_DATA_LOW 0xffff | ||
| 163 | #define BF_SPDIF_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
| 164 | |||
| 165 | #endif /* __HEADERGEN__STMP3600__SPDIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-ssp.h b/firmware/target/arm/imx233/regs/stmp3600/regs-ssp.h new file mode 100644 index 0000000000..2c589f5256 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-ssp.h | |||
| @@ -0,0 +1,541 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__SSP__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__SSP__H__ | ||
| 25 | |||
| 26 | #define REGS_SSP_BASE (0x80010000) | ||
| 27 | |||
| 28 | #define REGS_SSP_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_SSP_CTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_SSP_CTRL0 (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_SSP_CTRL0_SET (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_SSP_CTRL0_CLR (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_SSP_CTRL0_TOG (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_SSP_CTRL0_SFTRST 31 | ||
| 40 | #define BM_SSP_CTRL0_SFTRST 0x80000000 | ||
| 41 | #define BF_SSP_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_SSP_CTRL0_CLKGATE 30 | ||
| 43 | #define BM_SSP_CTRL0_CLKGATE 0x40000000 | ||
| 44 | #define BF_SSP_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_SSP_CTRL0_RUN 29 | ||
| 46 | #define BM_SSP_CTRL0_RUN 0x20000000 | ||
| 47 | #define BF_SSP_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
| 48 | #define BP_SSP_CTRL0_HALF_DUPLEX 28 | ||
| 49 | #define BM_SSP_CTRL0_HALF_DUPLEX 0x10000000 | ||
| 50 | #define BF_SSP_CTRL0_HALF_DUPLEX(v) (((v) << 28) & 0x10000000) | ||
| 51 | #define BP_SSP_CTRL0_LOCK_CS 27 | ||
| 52 | #define BM_SSP_CTRL0_LOCK_CS 0x8000000 | ||
| 53 | #define BF_SSP_CTRL0_LOCK_CS(v) (((v) << 27) & 0x8000000) | ||
| 54 | #define BP_SSP_CTRL0_IGNORE_CRC 26 | ||
| 55 | #define BM_SSP_CTRL0_IGNORE_CRC 0x4000000 | ||
| 56 | #define BF_SSP_CTRL0_IGNORE_CRC(v) (((v) << 26) & 0x4000000) | ||
| 57 | #define BP_SSP_CTRL0_READ 25 | ||
| 58 | #define BM_SSP_CTRL0_READ 0x2000000 | ||
| 59 | #define BF_SSP_CTRL0_READ(v) (((v) << 25) & 0x2000000) | ||
| 60 | #define BP_SSP_CTRL0_DATA_XFER 24 | ||
| 61 | #define BM_SSP_CTRL0_DATA_XFER 0x1000000 | ||
| 62 | #define BF_SSP_CTRL0_DATA_XFER(v) (((v) << 24) & 0x1000000) | ||
| 63 | #define BP_SSP_CTRL0_SDIO_IRQ 23 | ||
| 64 | #define BM_SSP_CTRL0_SDIO_IRQ 0x800000 | ||
| 65 | #define BF_SSP_CTRL0_SDIO_IRQ(v) (((v) << 23) & 0x800000) | ||
| 66 | #define BP_SSP_CTRL0_BUS_WIDTH 22 | ||
| 67 | #define BM_SSP_CTRL0_BUS_WIDTH 0x400000 | ||
| 68 | #define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0 | ||
| 69 | #define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1 | ||
| 70 | #define BF_SSP_CTRL0_BUS_WIDTH(v) (((v) << 22) & 0x400000) | ||
| 71 | #define BF_SSP_CTRL0_BUS_WIDTH_V(v) ((BV_SSP_CTRL0_BUS_WIDTH__##v << 22) & 0x400000) | ||
| 72 | #define BP_SSP_CTRL0_WAIT_FOR_IRQ 21 | ||
| 73 | #define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x200000 | ||
| 74 | #define BF_SSP_CTRL0_WAIT_FOR_IRQ(v) (((v) << 21) & 0x200000) | ||
| 75 | #define BP_SSP_CTRL0_WAIT_FOR_CMD 20 | ||
| 76 | #define BM_SSP_CTRL0_WAIT_FOR_CMD 0x100000 | ||
| 77 | #define BF_SSP_CTRL0_WAIT_FOR_CMD(v) (((v) << 20) & 0x100000) | ||
| 78 | #define BP_SSP_CTRL0_LONG_RESP 19 | ||
| 79 | #define BM_SSP_CTRL0_LONG_RESP 0x80000 | ||
| 80 | #define BF_SSP_CTRL0_LONG_RESP(v) (((v) << 19) & 0x80000) | ||
| 81 | #define BP_SSP_CTRL0_CHECK_RESP 18 | ||
| 82 | #define BM_SSP_CTRL0_CHECK_RESP 0x40000 | ||
| 83 | #define BF_SSP_CTRL0_CHECK_RESP(v) (((v) << 18) & 0x40000) | ||
| 84 | #define BP_SSP_CTRL0_GET_RESP 17 | ||
| 85 | #define BM_SSP_CTRL0_GET_RESP 0x20000 | ||
| 86 | #define BF_SSP_CTRL0_GET_RESP(v) (((v) << 17) & 0x20000) | ||
| 87 | #define BP_SSP_CTRL0_ENABLE 16 | ||
| 88 | #define BM_SSP_CTRL0_ENABLE 0x10000 | ||
| 89 | #define BF_SSP_CTRL0_ENABLE(v) (((v) << 16) & 0x10000) | ||
| 90 | #define BP_SSP_CTRL0_XFER_COUNT 0 | ||
| 91 | #define BM_SSP_CTRL0_XFER_COUNT 0xffff | ||
| 92 | #define BF_SSP_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
| 93 | |||
| 94 | /** | ||
| 95 | * Register: HW_SSP_CMD0 | ||
| 96 | * Address: 0x10 | ||
| 97 | * SCT: yes | ||
| 98 | */ | ||
| 99 | #define HW_SSP_CMD0 (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0x0)) | ||
| 100 | #define HW_SSP_CMD0_SET (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0x4)) | ||
| 101 | #define HW_SSP_CMD0_CLR (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0x8)) | ||
| 102 | #define HW_SSP_CMD0_TOG (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0xc)) | ||
| 103 | #define BP_SSP_CMD0_CMD 0 | ||
| 104 | #define BM_SSP_CMD0_CMD 0xff | ||
| 105 | #define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x0 | ||
| 106 | #define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x1 | ||
| 107 | #define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x2 | ||
| 108 | #define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x3 | ||
| 109 | #define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x4 | ||
| 110 | #define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x5 | ||
| 111 | #define BV_SSP_CMD0_CMD__MMC_SWITCH 0x6 | ||
| 112 | #define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x7 | ||
| 113 | #define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x8 | ||
| 114 | #define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x9 | ||
| 115 | #define BV_SSP_CMD0_CMD__MMC_SEND_CID 0xa | ||
| 116 | #define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0xb | ||
| 117 | #define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0xc | ||
| 118 | #define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0xd | ||
| 119 | #define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0xe | ||
| 120 | #define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0xf | ||
| 121 | #define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10 | ||
| 122 | #define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11 | ||
| 123 | #define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12 | ||
| 124 | #define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13 | ||
| 125 | #define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14 | ||
| 126 | #define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17 | ||
| 127 | #define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18 | ||
| 128 | #define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19 | ||
| 129 | #define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1a | ||
| 130 | #define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1b | ||
| 131 | #define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1c | ||
| 132 | #define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1d | ||
| 133 | #define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1e | ||
| 134 | #define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23 | ||
| 135 | #define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24 | ||
| 136 | #define BV_SSP_CMD0_CMD__MMC_ERASE 0x26 | ||
| 137 | #define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27 | ||
| 138 | #define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28 | ||
| 139 | #define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2a | ||
| 140 | #define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37 | ||
| 141 | #define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38 | ||
| 142 | #define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x0 | ||
| 143 | #define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x2 | ||
| 144 | #define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x3 | ||
| 145 | #define BV_SSP_CMD0_CMD__SD_SET_DSR 0x4 | ||
| 146 | #define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x5 | ||
| 147 | #define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x7 | ||
| 148 | #define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x9 | ||
| 149 | #define BV_SSP_CMD0_CMD__SD_SEND_CID 0xa | ||
| 150 | #define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0xc | ||
| 151 | #define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0xd | ||
| 152 | #define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0xf | ||
| 153 | #define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10 | ||
| 154 | #define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11 | ||
| 155 | #define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12 | ||
| 156 | #define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18 | ||
| 157 | #define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19 | ||
| 158 | #define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1b | ||
| 159 | #define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1c | ||
| 160 | #define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1d | ||
| 161 | #define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1e | ||
| 162 | #define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20 | ||
| 163 | #define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21 | ||
| 164 | #define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23 | ||
| 165 | #define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24 | ||
| 166 | #define BV_SSP_CMD0_CMD__SD_ERASE 0x26 | ||
| 167 | #define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2a | ||
| 168 | #define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34 | ||
| 169 | #define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35 | ||
| 170 | #define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37 | ||
| 171 | #define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38 | ||
| 172 | #define BF_SSP_CMD0_CMD(v) (((v) << 0) & 0xff) | ||
| 173 | #define BF_SSP_CMD0_CMD_V(v) ((BV_SSP_CMD0_CMD__##v << 0) & 0xff) | ||
| 174 | |||
| 175 | /** | ||
| 176 | * Register: HW_SSP_CMD1 | ||
| 177 | * Address: 0x20 | ||
| 178 | * SCT: no | ||
| 179 | */ | ||
| 180 | #define HW_SSP_CMD1 (*(volatile unsigned long *)(REGS_SSP_BASE + 0x20)) | ||
| 181 | #define BP_SSP_CMD1_CMD_ARG 0 | ||
| 182 | #define BM_SSP_CMD1_CMD_ARG 0xffffffff | ||
| 183 | #define BF_SSP_CMD1_CMD_ARG(v) (((v) << 0) & 0xffffffff) | ||
| 184 | |||
| 185 | /** | ||
| 186 | * Register: HW_SSP_COMPREF | ||
| 187 | * Address: 0x30 | ||
| 188 | * SCT: no | ||
| 189 | */ | ||
| 190 | #define HW_SSP_COMPREF (*(volatile unsigned long *)(REGS_SSP_BASE + 0x30)) | ||
| 191 | #define BP_SSP_COMPREF_REFERENCE 0 | ||
| 192 | #define BM_SSP_COMPREF_REFERENCE 0xffffffff | ||
| 193 | #define BF_SSP_COMPREF_REFERENCE(v) (((v) << 0) & 0xffffffff) | ||
| 194 | |||
| 195 | /** | ||
| 196 | * Register: HW_SSP_COMPMASK | ||
| 197 | * Address: 0x40 | ||
| 198 | * SCT: no | ||
| 199 | */ | ||
| 200 | #define HW_SSP_COMPMASK (*(volatile unsigned long *)(REGS_SSP_BASE + 0x40)) | ||
| 201 | #define BP_SSP_COMPMASK_MASK 0 | ||
| 202 | #define BM_SSP_COMPMASK_MASK 0xffffffff | ||
| 203 | #define BF_SSP_COMPMASK_MASK(v) (((v) << 0) & 0xffffffff) | ||
| 204 | |||
| 205 | /** | ||
| 206 | * Register: HW_SSP_TIMING | ||
| 207 | * Address: 0x50 | ||
| 208 | * SCT: no | ||
| 209 | */ | ||
| 210 | #define HW_SSP_TIMING (*(volatile unsigned long *)(REGS_SSP_BASE + 0x50)) | ||
| 211 | #define BP_SSP_TIMING_TIMEOUT 16 | ||
| 212 | #define BM_SSP_TIMING_TIMEOUT 0xffff0000 | ||
| 213 | #define BF_SSP_TIMING_TIMEOUT(v) (((v) << 16) & 0xffff0000) | ||
| 214 | #define BP_SSP_TIMING_CLOCK_DIVIDE 8 | ||
| 215 | #define BM_SSP_TIMING_CLOCK_DIVIDE 0xff00 | ||
| 216 | #define BF_SSP_TIMING_CLOCK_DIVIDE(v) (((v) << 8) & 0xff00) | ||
| 217 | #define BP_SSP_TIMING_CLOCK_RATE 0 | ||
| 218 | #define BM_SSP_TIMING_CLOCK_RATE 0xff | ||
| 219 | #define BF_SSP_TIMING_CLOCK_RATE(v) (((v) << 0) & 0xff) | ||
| 220 | |||
| 221 | /** | ||
| 222 | * Register: HW_SSP_CTRL1 | ||
| 223 | * Address: 0x60 | ||
| 224 | * SCT: yes | ||
| 225 | */ | ||
| 226 | #define HW_SSP_CTRL1 (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0x0)) | ||
| 227 | #define HW_SSP_CTRL1_SET (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0x4)) | ||
| 228 | #define HW_SSP_CTRL1_CLR (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0x8)) | ||
| 229 | #define HW_SSP_CTRL1_TOG (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0xc)) | ||
| 230 | #define BP_SSP_CTRL1_SDIO_IRQ 31 | ||
| 231 | #define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 | ||
| 232 | #define BF_SSP_CTRL1_SDIO_IRQ(v) (((v) << 31) & 0x80000000) | ||
| 233 | #define BP_SSP_CTRL1_SDIO_IRQ_EN 30 | ||
| 234 | #define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000 | ||
| 235 | #define BF_SSP_CTRL1_SDIO_IRQ_EN(v) (((v) << 30) & 0x40000000) | ||
| 236 | #define BP_SSP_CTRL1_RESP_ERR_IRQ 29 | ||
| 237 | #define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 | ||
| 238 | #define BF_SSP_CTRL1_RESP_ERR_IRQ(v) (((v) << 29) & 0x20000000) | ||
| 239 | #define BP_SSP_CTRL1_RESP_ERR_IRQ_EN 28 | ||
| 240 | #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 | ||
| 241 | #define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v) (((v) << 28) & 0x10000000) | ||
| 242 | #define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ 27 | ||
| 243 | #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x8000000 | ||
| 244 | #define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v) (((v) << 27) & 0x8000000) | ||
| 245 | #define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 26 | ||
| 246 | #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x4000000 | ||
| 247 | #define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v) (((v) << 26) & 0x4000000) | ||
| 248 | #define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ 25 | ||
| 249 | #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x2000000 | ||
| 250 | #define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v) (((v) << 25) & 0x2000000) | ||
| 251 | #define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 24 | ||
| 252 | #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x1000000 | ||
| 253 | #define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v) (((v) << 24) & 0x1000000) | ||
| 254 | #define BP_SSP_CTRL1_DATA_CRC_IRQ 23 | ||
| 255 | #define BM_SSP_CTRL1_DATA_CRC_IRQ 0x800000 | ||
| 256 | #define BF_SSP_CTRL1_DATA_CRC_IRQ(v) (((v) << 23) & 0x800000) | ||
| 257 | #define BP_SSP_CTRL1_DATA_CRC_IRQ_EN 22 | ||
| 258 | #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x400000 | ||
| 259 | #define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
| 260 | #define BP_SSP_CTRL1_XMIT_IRQ 21 | ||
| 261 | #define BM_SSP_CTRL1_XMIT_IRQ 0x200000 | ||
| 262 | #define BF_SSP_CTRL1_XMIT_IRQ(v) (((v) << 21) & 0x200000) | ||
| 263 | #define BP_SSP_CTRL1_XMIT_IRQ_EN 20 | ||
| 264 | #define BM_SSP_CTRL1_XMIT_IRQ_EN 0x100000 | ||
| 265 | #define BF_SSP_CTRL1_XMIT_IRQ_EN(v) (((v) << 20) & 0x100000) | ||
| 266 | #define BP_SSP_CTRL1_RECV_IRQ 19 | ||
| 267 | #define BM_SSP_CTRL1_RECV_IRQ 0x80000 | ||
| 268 | #define BF_SSP_CTRL1_RECV_IRQ(v) (((v) << 19) & 0x80000) | ||
| 269 | #define BP_SSP_CTRL1_RECV_IRQ_EN 18 | ||
| 270 | #define BM_SSP_CTRL1_RECV_IRQ_EN 0x40000 | ||
| 271 | #define BF_SSP_CTRL1_RECV_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
| 272 | #define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ 17 | ||
| 273 | #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x20000 | ||
| 274 | #define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v) (((v) << 17) & 0x20000) | ||
| 275 | #define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 16 | ||
| 276 | #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x10000 | ||
| 277 | #define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
| 278 | #define BP_SSP_CTRL1_RECV_OVRFLW_IRQ 15 | ||
| 279 | #define BM_SSP_CTRL1_RECV_OVRFLW_IRQ 0x8000 | ||
| 280 | #define BF_SSP_CTRL1_RECV_OVRFLW_IRQ(v) (((v) << 15) & 0x8000) | ||
| 281 | #define BP_SSP_CTRL1_RECV_OVRFLW_IRQ_EN 14 | ||
| 282 | #define BM_SSP_CTRL1_RECV_OVRFLW_IRQ_EN 0x4000 | ||
| 283 | #define BF_SSP_CTRL1_RECV_OVRFLW_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
| 284 | #define BP_SSP_CTRL1_DMA_ENABLE 13 | ||
| 285 | #define BM_SSP_CTRL1_DMA_ENABLE 0x2000 | ||
| 286 | #define BF_SSP_CTRL1_DMA_ENABLE(v) (((v) << 13) & 0x2000) | ||
| 287 | #define BP_SSP_CTRL1_LOOPBACK 12 | ||
| 288 | #define BM_SSP_CTRL1_LOOPBACK 0x1000 | ||
| 289 | #define BF_SSP_CTRL1_LOOPBACK(v) (((v) << 12) & 0x1000) | ||
| 290 | #define BP_SSP_CTRL1_SLAVE_OUT_DISABLE 11 | ||
| 291 | #define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x800 | ||
| 292 | #define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v) (((v) << 11) & 0x800) | ||
| 293 | #define BP_SSP_CTRL1_PHASE 10 | ||
| 294 | #define BM_SSP_CTRL1_PHASE 0x400 | ||
| 295 | #define BF_SSP_CTRL1_PHASE(v) (((v) << 10) & 0x400) | ||
| 296 | #define BP_SSP_CTRL1_POLARITY 9 | ||
| 297 | #define BM_SSP_CTRL1_POLARITY 0x200 | ||
| 298 | #define BF_SSP_CTRL1_POLARITY(v) (((v) << 9) & 0x200) | ||
| 299 | #define BP_SSP_CTRL1_SLAVE_MODE 8 | ||
| 300 | #define BM_SSP_CTRL1_SLAVE_MODE 0x100 | ||
| 301 | #define BF_SSP_CTRL1_SLAVE_MODE(v) (((v) << 8) & 0x100) | ||
| 302 | #define BP_SSP_CTRL1_WORD_LENGTH 4 | ||
| 303 | #define BM_SSP_CTRL1_WORD_LENGTH 0xf0 | ||
| 304 | #define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0 | ||
| 305 | #define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1 | ||
| 306 | #define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2 | ||
| 307 | #define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3 | ||
| 308 | #define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7 | ||
| 309 | #define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xf | ||
| 310 | #define BF_SSP_CTRL1_WORD_LENGTH(v) (((v) << 4) & 0xf0) | ||
| 311 | #define BF_SSP_CTRL1_WORD_LENGTH_V(v) ((BV_SSP_CTRL1_WORD_LENGTH__##v << 4) & 0xf0) | ||
| 312 | #define BP_SSP_CTRL1_SSP_MODE 0 | ||
| 313 | #define BM_SSP_CTRL1_SSP_MODE 0xf | ||
| 314 | #define BV_SSP_CTRL1_SSP_MODE__SPI 0x0 | ||
| 315 | #define BV_SSP_CTRL1_SSP_MODE__SSI 0x1 | ||
| 316 | #define BV_SSP_CTRL1_SSP_MODE__MICROWIRE 0x2 | ||
| 317 | #define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3 | ||
| 318 | #define BV_SSP_CTRL1_SSP_MODE__MS 0x4 | ||
| 319 | #define BF_SSP_CTRL1_SSP_MODE(v) (((v) << 0) & 0xf) | ||
| 320 | #define BF_SSP_CTRL1_SSP_MODE_V(v) ((BV_SSP_CTRL1_SSP_MODE__##v << 0) & 0xf) | ||
| 321 | |||
| 322 | /** | ||
| 323 | * Register: HW_SSP_DATA | ||
| 324 | * Address: 0x70 | ||
| 325 | * SCT: no | ||
| 326 | */ | ||
| 327 | #define HW_SSP_DATA (*(volatile unsigned long *)(REGS_SSP_BASE + 0x70)) | ||
| 328 | #define BP_SSP_DATA_DATA 0 | ||
| 329 | #define BM_SSP_DATA_DATA 0xffffffff | ||
| 330 | #define BF_SSP_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 331 | |||
| 332 | /** | ||
| 333 | * Register: HW_SSP_SDRESP0 | ||
| 334 | * Address: 0x80 | ||
| 335 | * SCT: no | ||
| 336 | */ | ||
| 337 | #define HW_SSP_SDRESP0 (*(volatile unsigned long *)(REGS_SSP_BASE + 0x80)) | ||
| 338 | #define BP_SSP_SDRESP0_RESP0 0 | ||
| 339 | #define BM_SSP_SDRESP0_RESP0 0xffffffff | ||
| 340 | #define BF_SSP_SDRESP0_RESP0(v) (((v) << 0) & 0xffffffff) | ||
| 341 | |||
| 342 | /** | ||
| 343 | * Register: HW_SSP_SDRESP1 | ||
| 344 | * Address: 0x90 | ||
| 345 | * SCT: no | ||
| 346 | */ | ||
| 347 | #define HW_SSP_SDRESP1 (*(volatile unsigned long *)(REGS_SSP_BASE + 0x90)) | ||
| 348 | #define BP_SSP_SDRESP1_RESP1 0 | ||
| 349 | #define BM_SSP_SDRESP1_RESP1 0xffffffff | ||
| 350 | #define BF_SSP_SDRESP1_RESP1(v) (((v) << 0) & 0xffffffff) | ||
| 351 | |||
| 352 | /** | ||
| 353 | * Register: HW_SSP_SDRESP2 | ||
| 354 | * Address: 0xa0 | ||
| 355 | * SCT: no | ||
| 356 | */ | ||
| 357 | #define HW_SSP_SDRESP2 (*(volatile unsigned long *)(REGS_SSP_BASE + 0xa0)) | ||
| 358 | #define BP_SSP_SDRESP2_RESP2 0 | ||
| 359 | #define BM_SSP_SDRESP2_RESP2 0xffffffff | ||
| 360 | #define BF_SSP_SDRESP2_RESP2(v) (((v) << 0) & 0xffffffff) | ||
| 361 | |||
| 362 | /** | ||
| 363 | * Register: HW_SSP_SDRESP3 | ||
| 364 | * Address: 0xb0 | ||
| 365 | * SCT: no | ||
| 366 | */ | ||
| 367 | #define HW_SSP_SDRESP3 (*(volatile unsigned long *)(REGS_SSP_BASE + 0xb0)) | ||
| 368 | #define BP_SSP_SDRESP3_RESP3 0 | ||
| 369 | #define BM_SSP_SDRESP3_RESP3 0xffffffff | ||
| 370 | #define BF_SSP_SDRESP3_RESP3(v) (((v) << 0) & 0xffffffff) | ||
| 371 | |||
| 372 | /** | ||
| 373 | * Register: HW_SSP_STATUS | ||
| 374 | * Address: 0xc0 | ||
| 375 | * SCT: no | ||
| 376 | */ | ||
| 377 | #define HW_SSP_STATUS (*(volatile unsigned long *)(REGS_SSP_BASE + 0xc0)) | ||
| 378 | #define BP_SSP_STATUS_PRESENT 31 | ||
| 379 | #define BM_SSP_STATUS_PRESENT 0x80000000 | ||
| 380 | #define BF_SSP_STATUS_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 381 | #define BP_SSP_STATUS_MS_PRESENT 30 | ||
| 382 | #define BM_SSP_STATUS_MS_PRESENT 0x40000000 | ||
| 383 | #define BF_SSP_STATUS_MS_PRESENT(v) (((v) << 30) & 0x40000000) | ||
| 384 | #define BP_SSP_STATUS_SD_PRESENT 29 | ||
| 385 | #define BM_SSP_STATUS_SD_PRESENT 0x20000000 | ||
| 386 | #define BF_SSP_STATUS_SD_PRESENT(v) (((v) << 29) & 0x20000000) | ||
| 387 | #define BP_SSP_STATUS_CARD_DETECT 28 | ||
| 388 | #define BM_SSP_STATUS_CARD_DETECT 0x10000000 | ||
| 389 | #define BF_SSP_STATUS_CARD_DETECT(v) (((v) << 28) & 0x10000000) | ||
| 390 | #define BP_SSP_STATUS_RECV_COUNT 24 | ||
| 391 | #define BM_SSP_STATUS_RECV_COUNT 0xf000000 | ||
| 392 | #define BF_SSP_STATUS_RECV_COUNT(v) (((v) << 24) & 0xf000000) | ||
| 393 | #define BP_SSP_STATUS_XMIT_COUNT 20 | ||
| 394 | #define BM_SSP_STATUS_XMIT_COUNT 0xf00000 | ||
| 395 | #define BF_SSP_STATUS_XMIT_COUNT(v) (((v) << 20) & 0xf00000) | ||
| 396 | #define BP_SSP_STATUS_DMAREQ 19 | ||
| 397 | #define BM_SSP_STATUS_DMAREQ 0x80000 | ||
| 398 | #define BF_SSP_STATUS_DMAREQ(v) (((v) << 19) & 0x80000) | ||
| 399 | #define BP_SSP_STATUS_DMAEND 18 | ||
| 400 | #define BM_SSP_STATUS_DMAEND 0x40000 | ||
| 401 | #define BF_SSP_STATUS_DMAEND(v) (((v) << 18) & 0x40000) | ||
| 402 | #define BP_SSP_STATUS_SDIO_IRQ 17 | ||
| 403 | #define BM_SSP_STATUS_SDIO_IRQ 0x20000 | ||
| 404 | #define BF_SSP_STATUS_SDIO_IRQ(v) (((v) << 17) & 0x20000) | ||
| 405 | #define BP_SSP_STATUS_RESP_CRC_ERR 16 | ||
| 406 | #define BM_SSP_STATUS_RESP_CRC_ERR 0x10000 | ||
| 407 | #define BF_SSP_STATUS_RESP_CRC_ERR(v) (((v) << 16) & 0x10000) | ||
| 408 | #define BP_SSP_STATUS_RESP_ERR 15 | ||
| 409 | #define BM_SSP_STATUS_RESP_ERR 0x8000 | ||
| 410 | #define BF_SSP_STATUS_RESP_ERR(v) (((v) << 15) & 0x8000) | ||
| 411 | #define BP_SSP_STATUS_RESP_TIMEOUT 14 | ||
| 412 | #define BM_SSP_STATUS_RESP_TIMEOUT 0x4000 | ||
| 413 | #define BF_SSP_STATUS_RESP_TIMEOUT(v) (((v) << 14) & 0x4000) | ||
| 414 | #define BP_SSP_STATUS_DATA_CRC_ERR 13 | ||
| 415 | #define BM_SSP_STATUS_DATA_CRC_ERR 0x2000 | ||
| 416 | #define BF_SSP_STATUS_DATA_CRC_ERR(v) (((v) << 13) & 0x2000) | ||
| 417 | #define BP_SSP_STATUS_TIMEOUT 12 | ||
| 418 | #define BM_SSP_STATUS_TIMEOUT 0x1000 | ||
| 419 | #define BF_SSP_STATUS_TIMEOUT(v) (((v) << 12) & 0x1000) | ||
| 420 | #define BP_SSP_STATUS_RECV_TIMEOUT_STAT 11 | ||
| 421 | #define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x800 | ||
| 422 | #define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v) (((v) << 11) & 0x800) | ||
| 423 | #define BP_SSP_STATUS_RECV_DATA_STAT 10 | ||
| 424 | #define BM_SSP_STATUS_RECV_DATA_STAT 0x400 | ||
| 425 | #define BF_SSP_STATUS_RECV_DATA_STAT(v) (((v) << 10) & 0x400) | ||
| 426 | #define BP_SSP_STATUS_RECV_OVRFLW 9 | ||
| 427 | #define BM_SSP_STATUS_RECV_OVRFLW 0x200 | ||
| 428 | #define BF_SSP_STATUS_RECV_OVRFLW(v) (((v) << 9) & 0x200) | ||
| 429 | #define BP_SSP_STATUS_RECV_FULL 8 | ||
| 430 | #define BM_SSP_STATUS_RECV_FULL 0x100 | ||
| 431 | #define BF_SSP_STATUS_RECV_FULL(v) (((v) << 8) & 0x100) | ||
| 432 | #define BP_SSP_STATUS_RECV_NOT_EMPTY 7 | ||
| 433 | #define BM_SSP_STATUS_RECV_NOT_EMPTY 0x80 | ||
| 434 | #define BF_SSP_STATUS_RECV_NOT_EMPTY(v) (((v) << 7) & 0x80) | ||
| 435 | #define BP_SSP_STATUS_XMIT_NOT_FULL 6 | ||
| 436 | #define BM_SSP_STATUS_XMIT_NOT_FULL 0x40 | ||
| 437 | #define BF_SSP_STATUS_XMIT_NOT_FULL(v) (((v) << 6) & 0x40) | ||
| 438 | #define BP_SSP_STATUS_XMIT_EMPTY 5 | ||
| 439 | #define BM_SSP_STATUS_XMIT_EMPTY 0x20 | ||
| 440 | #define BF_SSP_STATUS_XMIT_EMPTY(v) (((v) << 5) & 0x20) | ||
| 441 | #define BP_SSP_STATUS_XMIT_UNDRFLW 4 | ||
| 442 | #define BM_SSP_STATUS_XMIT_UNDRFLW 0x10 | ||
| 443 | #define BF_SSP_STATUS_XMIT_UNDRFLW(v) (((v) << 4) & 0x10) | ||
| 444 | #define BP_SSP_STATUS_CMD_BUSY 3 | ||
| 445 | #define BM_SSP_STATUS_CMD_BUSY 0x8 | ||
| 446 | #define BF_SSP_STATUS_CMD_BUSY(v) (((v) << 3) & 0x8) | ||
| 447 | #define BP_SSP_STATUS_DATA_BUSY 2 | ||
| 448 | #define BM_SSP_STATUS_DATA_BUSY 0x4 | ||
| 449 | #define BF_SSP_STATUS_DATA_BUSY(v) (((v) << 2) & 0x4) | ||
| 450 | #define BP_SSP_STATUS_DATA_XFER 1 | ||
| 451 | #define BM_SSP_STATUS_DATA_XFER 0x2 | ||
| 452 | #define BF_SSP_STATUS_DATA_XFER(v) (((v) << 1) & 0x2) | ||
| 453 | #define BP_SSP_STATUS_BUSY 0 | ||
| 454 | #define BM_SSP_STATUS_BUSY 0x1 | ||
| 455 | #define BF_SSP_STATUS_BUSY(v) (((v) << 0) & 0x1) | ||
| 456 | |||
| 457 | /** | ||
| 458 | * Register: HW_SSP_DEBUG | ||
| 459 | * Address: 0x100 | ||
| 460 | * SCT: no | ||
| 461 | */ | ||
| 462 | #define HW_SSP_DEBUG (*(volatile unsigned long *)(REGS_SSP_BASE + 0x100)) | ||
| 463 | #define BP_SSP_DEBUG_DATACRC_ERR 28 | ||
| 464 | #define BM_SSP_DEBUG_DATACRC_ERR 0xf0000000 | ||
| 465 | #define BF_SSP_DEBUG_DATACRC_ERR(v) (((v) << 28) & 0xf0000000) | ||
| 466 | #define BP_SSP_DEBUG_DATA_STALL 27 | ||
| 467 | #define BM_SSP_DEBUG_DATA_STALL 0x8000000 | ||
| 468 | #define BF_SSP_DEBUG_DATA_STALL(v) (((v) << 27) & 0x8000000) | ||
| 469 | #define BP_SSP_DEBUG_DAT_SM 24 | ||
| 470 | #define BM_SSP_DEBUG_DAT_SM 0x7000000 | ||
| 471 | #define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0 | ||
| 472 | #define BV_SSP_DEBUG_DAT_SM__DSM_START 0x1 | ||
| 473 | #define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2 | ||
| 474 | #define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3 | ||
| 475 | #define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4 | ||
| 476 | #define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5 | ||
| 477 | #define BV_SSP_DEBUG_DAT_SM__DSM_RXDLY 0x6 | ||
| 478 | #define BF_SSP_DEBUG_DAT_SM(v) (((v) << 24) & 0x7000000) | ||
| 479 | #define BF_SSP_DEBUG_DAT_SM_V(v) ((BV_SSP_DEBUG_DAT_SM__##v << 24) & 0x7000000) | ||
| 480 | #define BP_SSP_DEBUG_MSTK_SM 20 | ||
| 481 | #define BM_SSP_DEBUG_MSTK_SM 0xf00000 | ||
| 482 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0 | ||
| 483 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1 | ||
| 484 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2 | ||
| 485 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3 | ||
| 486 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4 | ||
| 487 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5 | ||
| 488 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6 | ||
| 489 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7 | ||
| 490 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8 | ||
| 491 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9 | ||
| 492 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xa | ||
| 493 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xb | ||
| 494 | #define BF_SSP_DEBUG_MSTK_SM(v) (((v) << 20) & 0xf00000) | ||
| 495 | #define BF_SSP_DEBUG_MSTK_SM_V(v) ((BV_SSP_DEBUG_MSTK_SM__##v << 20) & 0xf00000) | ||
| 496 | #define BP_SSP_DEBUG_CMD_OE 19 | ||
| 497 | #define BM_SSP_DEBUG_CMD_OE 0x80000 | ||
| 498 | #define BF_SSP_DEBUG_CMD_OE(v) (((v) << 19) & 0x80000) | ||
| 499 | #define BP_SSP_DEBUG_CMD_SM 16 | ||
| 500 | #define BM_SSP_DEBUG_CMD_SM 0x70000 | ||
| 501 | #define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0 | ||
| 502 | #define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1 | ||
| 503 | #define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2 | ||
| 504 | #define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3 | ||
| 505 | #define BF_SSP_DEBUG_CMD_SM(v) (((v) << 16) & 0x70000) | ||
| 506 | #define BF_SSP_DEBUG_CMD_SM_V(v) ((BV_SSP_DEBUG_CMD_SM__##v << 16) & 0x70000) | ||
| 507 | #define BP_SSP_DEBUG_CLK_OE 15 | ||
| 508 | #define BM_SSP_DEBUG_CLK_OE 0x8000 | ||
| 509 | #define BF_SSP_DEBUG_CLK_OE(v) (((v) << 15) & 0x8000) | ||
| 510 | #define BP_SSP_DEBUG_MMC_SM 12 | ||
| 511 | #define BM_SSP_DEBUG_MMC_SM 0x7000 | ||
| 512 | #define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0 | ||
| 513 | #define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1 | ||
| 514 | #define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2 | ||
| 515 | #define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3 | ||
| 516 | #define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4 | ||
| 517 | #define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5 | ||
| 518 | #define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6 | ||
| 519 | #define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7 | ||
| 520 | #define BF_SSP_DEBUG_MMC_SM(v) (((v) << 12) & 0x7000) | ||
| 521 | #define BF_SSP_DEBUG_MMC_SM_V(v) ((BV_SSP_DEBUG_MMC_SM__##v << 12) & 0x7000) | ||
| 522 | #define BP_SSP_DEBUG_DAT0_OE 11 | ||
| 523 | #define BM_SSP_DEBUG_DAT0_OE 0x800 | ||
| 524 | #define BF_SSP_DEBUG_DAT0_OE(v) (((v) << 11) & 0x800) | ||
| 525 | #define BP_SSP_DEBUG_DAT321_OE 10 | ||
| 526 | #define BM_SSP_DEBUG_DAT321_OE 0x400 | ||
| 527 | #define BF_SSP_DEBUG_DAT321_OE(v) (((v) << 10) & 0x400) | ||
| 528 | #define BP_SSP_DEBUG_SSP_CMD 9 | ||
| 529 | #define BM_SSP_DEBUG_SSP_CMD 0x200 | ||
| 530 | #define BF_SSP_DEBUG_SSP_CMD(v) (((v) << 9) & 0x200) | ||
| 531 | #define BP_SSP_DEBUG_SSP_RESP 8 | ||
| 532 | #define BM_SSP_DEBUG_SSP_RESP 0x100 | ||
| 533 | #define BF_SSP_DEBUG_SSP_RESP(v) (((v) << 8) & 0x100) | ||
| 534 | #define BP_SSP_DEBUG_SSP_TXD 4 | ||
| 535 | #define BM_SSP_DEBUG_SSP_TXD 0xf0 | ||
| 536 | #define BF_SSP_DEBUG_SSP_TXD(v) (((v) << 4) & 0xf0) | ||
| 537 | #define BP_SSP_DEBUG_SSP_RXD 0 | ||
| 538 | #define BM_SSP_DEBUG_SSP_RXD 0xf | ||
| 539 | #define BF_SSP_DEBUG_SSP_RXD(v) (((v) << 0) & 0xf) | ||
| 540 | |||
| 541 | #endif /* __HEADERGEN__STMP3600__SSP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h b/firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h new file mode 100644 index 0000000000..a726662ac8 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h | |||
| @@ -0,0 +1,267 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__TIMROT__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__TIMROT__H__ | ||
| 25 | |||
| 26 | #define REGS_TIMROT_BASE (0x80068000) | ||
| 27 | |||
| 28 | #define REGS_TIMROT_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_TIMROT_ROTCTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_TIMROT_ROTCTRL (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_TIMROT_ROTCTRL_SET (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_TIMROT_ROTCTRL_CLR (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_TIMROT_ROTCTRL_TOG (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_TIMROT_ROTCTRL_SFTRST 31 | ||
| 40 | #define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_TIMROT_ROTCTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_TIMROT_ROTCTRL_CLKGATE 30 | ||
| 43 | #define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_TIMROT_ROTCTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_TIMROT_ROTCTRL_ROTARY_PRESENT 29 | ||
| 46 | #define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 | ||
| 47 | #define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v) (((v) << 29) & 0x20000000) | ||
| 48 | #define BP_TIMROT_ROTCTRL_TIM3_PRESENT 28 | ||
| 49 | #define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 | ||
| 50 | #define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v) (((v) << 28) & 0x10000000) | ||
| 51 | #define BP_TIMROT_ROTCTRL_TIM2_PRESENT 27 | ||
| 52 | #define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x8000000 | ||
| 53 | #define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v) (((v) << 27) & 0x8000000) | ||
| 54 | #define BP_TIMROT_ROTCTRL_TIM1_PRESENT 26 | ||
| 55 | #define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x4000000 | ||
| 56 | #define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
| 57 | #define BP_TIMROT_ROTCTRL_TIM0_PRESENT 25 | ||
| 58 | #define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x2000000 | ||
| 59 | #define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
| 60 | #define BP_TIMROT_ROTCTRL_STATE 22 | ||
| 61 | #define BM_TIMROT_ROTCTRL_STATE 0x1c00000 | ||
| 62 | #define BF_TIMROT_ROTCTRL_STATE(v) (((v) << 22) & 0x1c00000) | ||
| 63 | #define BP_TIMROT_ROTCTRL_DIVIDER 16 | ||
| 64 | #define BM_TIMROT_ROTCTRL_DIVIDER 0x3f0000 | ||
| 65 | #define BF_TIMROT_ROTCTRL_DIVIDER(v) (((v) << 16) & 0x3f0000) | ||
| 66 | #define BP_TIMROT_ROTCTRL_RELATIVE 12 | ||
| 67 | #define BM_TIMROT_ROTCTRL_RELATIVE 0x1000 | ||
| 68 | #define BF_TIMROT_ROTCTRL_RELATIVE(v) (((v) << 12) & 0x1000) | ||
| 69 | #define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 | ||
| 70 | #define BM_TIMROT_ROTCTRL_OVERSAMPLE 0xc00 | ||
| 71 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 | ||
| 72 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 | ||
| 73 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 | ||
| 74 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 | ||
| 75 | #define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) (((v) << 10) & 0xc00) | ||
| 76 | #define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(v) ((BV_TIMROT_ROTCTRL_OVERSAMPLE__##v << 10) & 0xc00) | ||
| 77 | #define BP_TIMROT_ROTCTRL_POLARITY_B 9 | ||
| 78 | #define BM_TIMROT_ROTCTRL_POLARITY_B 0x200 | ||
| 79 | #define BF_TIMROT_ROTCTRL_POLARITY_B(v) (((v) << 9) & 0x200) | ||
| 80 | #define BP_TIMROT_ROTCTRL_POLARITY_A 8 | ||
| 81 | #define BM_TIMROT_ROTCTRL_POLARITY_A 0x100 | ||
| 82 | #define BF_TIMROT_ROTCTRL_POLARITY_A(v) (((v) << 8) & 0x100) | ||
| 83 | #define BP_TIMROT_ROTCTRL_SELECT_B 4 | ||
| 84 | #define BM_TIMROT_ROTCTRL_SELECT_B 0x70 | ||
| 85 | #define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 | ||
| 86 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 | ||
| 87 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 | ||
| 88 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 | ||
| 89 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 | ||
| 90 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 | ||
| 91 | #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x6 | ||
| 92 | #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0x7 | ||
| 93 | #define BF_TIMROT_ROTCTRL_SELECT_B(v) (((v) << 4) & 0x70) | ||
| 94 | #define BF_TIMROT_ROTCTRL_SELECT_B_V(v) ((BV_TIMROT_ROTCTRL_SELECT_B__##v << 4) & 0x70) | ||
| 95 | #define BP_TIMROT_ROTCTRL_SELECT_A 0 | ||
| 96 | #define BM_TIMROT_ROTCTRL_SELECT_A 0x7 | ||
| 97 | #define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 | ||
| 98 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 | ||
| 99 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 | ||
| 100 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 | ||
| 101 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 | ||
| 102 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 | ||
| 103 | #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x6 | ||
| 104 | #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0x7 | ||
| 105 | #define BF_TIMROT_ROTCTRL_SELECT_A(v) (((v) << 0) & 0x7) | ||
| 106 | #define BF_TIMROT_ROTCTRL_SELECT_A_V(v) ((BV_TIMROT_ROTCTRL_SELECT_A__##v << 0) & 0x7) | ||
| 107 | |||
| 108 | /** | ||
| 109 | * Register: HW_TIMROT_ROTCOUNT | ||
| 110 | * Address: 0x10 | ||
| 111 | * SCT: no | ||
| 112 | */ | ||
| 113 | #define HW_TIMROT_ROTCOUNT (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x10)) | ||
| 114 | #define BP_TIMROT_ROTCOUNT_UPDOWN 0 | ||
| 115 | #define BM_TIMROT_ROTCOUNT_UPDOWN 0xffff | ||
| 116 | #define BF_TIMROT_ROTCOUNT_UPDOWN(v) (((v) << 0) & 0xffff) | ||
| 117 | |||
| 118 | /** | ||
| 119 | * Register: HW_TIMROT_TIMCTRL3 | ||
| 120 | * Address: 0x80 | ||
| 121 | * SCT: yes | ||
| 122 | */ | ||
| 123 | #define HW_TIMROT_TIMCTRL3 (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x0)) | ||
| 124 | #define HW_TIMROT_TIMCTRL3_SET (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x4)) | ||
| 125 | #define HW_TIMROT_TIMCTRL3_CLR (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x8)) | ||
| 126 | #define HW_TIMROT_TIMCTRL3_TOG (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0xc)) | ||
| 127 | #define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 | ||
| 128 | #define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0xf0000 | ||
| 129 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 | ||
| 130 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 | ||
| 131 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 | ||
| 132 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 | ||
| 133 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 | ||
| 134 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 | ||
| 135 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x6 | ||
| 136 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0x7 | ||
| 137 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0x8 | ||
| 138 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0x9 | ||
| 139 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xa | ||
| 140 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xb | ||
| 141 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc | ||
| 142 | #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) (((v) << 16) & 0xf0000) | ||
| 143 | #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v) ((BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##v << 16) & 0xf0000) | ||
| 144 | #define BP_TIMROT_TIMCTRL3_IRQ 15 | ||
| 145 | #define BM_TIMROT_TIMCTRL3_IRQ 0x8000 | ||
| 146 | #define BF_TIMROT_TIMCTRL3_IRQ(v) (((v) << 15) & 0x8000) | ||
| 147 | #define BP_TIMROT_TIMCTRL3_IRQ_EN 14 | ||
| 148 | #define BM_TIMROT_TIMCTRL3_IRQ_EN 0x4000 | ||
| 149 | #define BF_TIMROT_TIMCTRL3_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
| 150 | #define BP_TIMROT_TIMCTRL3_DUTY_VALID 10 | ||
| 151 | #define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x400 | ||
| 152 | #define BF_TIMROT_TIMCTRL3_DUTY_VALID(v) (((v) << 10) & 0x400) | ||
| 153 | #define BP_TIMROT_TIMCTRL3_DUTY_CYCLE 9 | ||
| 154 | #define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x200 | ||
| 155 | #define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v) (((v) << 9) & 0x200) | ||
| 156 | #define BP_TIMROT_TIMCTRL3_POLARITY 8 | ||
| 157 | #define BM_TIMROT_TIMCTRL3_POLARITY 0x100 | ||
| 158 | #define BF_TIMROT_TIMCTRL3_POLARITY(v) (((v) << 8) & 0x100) | ||
| 159 | #define BP_TIMROT_TIMCTRL3_UPDATE 7 | ||
| 160 | #define BM_TIMROT_TIMCTRL3_UPDATE 0x80 | ||
| 161 | #define BF_TIMROT_TIMCTRL3_UPDATE(v) (((v) << 7) & 0x80) | ||
| 162 | #define BP_TIMROT_TIMCTRL3_RELOAD 6 | ||
| 163 | #define BM_TIMROT_TIMCTRL3_RELOAD 0x40 | ||
| 164 | #define BF_TIMROT_TIMCTRL3_RELOAD(v) (((v) << 6) & 0x40) | ||
| 165 | #define BP_TIMROT_TIMCTRL3_PRESCALE 4 | ||
| 166 | #define BM_TIMROT_TIMCTRL3_PRESCALE 0x30 | ||
| 167 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 | ||
| 168 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 | ||
| 169 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 | ||
| 170 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 | ||
| 171 | #define BF_TIMROT_TIMCTRL3_PRESCALE(v) (((v) << 4) & 0x30) | ||
| 172 | #define BF_TIMROT_TIMCTRL3_PRESCALE_V(v) ((BV_TIMROT_TIMCTRL3_PRESCALE__##v << 4) & 0x30) | ||
| 173 | #define BP_TIMROT_TIMCTRL3_SELECT 0 | ||
| 174 | #define BM_TIMROT_TIMCTRL3_SELECT 0xf | ||
| 175 | #define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 | ||
| 176 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 | ||
| 177 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 | ||
| 178 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 | ||
| 179 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 | ||
| 180 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 | ||
| 181 | #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x6 | ||
| 182 | #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0x7 | ||
| 183 | #define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0x8 | ||
| 184 | #define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0x9 | ||
| 185 | #define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xa | ||
| 186 | #define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xb | ||
| 187 | #define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xc | ||
| 188 | #define BF_TIMROT_TIMCTRL3_SELECT(v) (((v) << 0) & 0xf) | ||
| 189 | #define BF_TIMROT_TIMCTRL3_SELECT_V(v) ((BV_TIMROT_TIMCTRL3_SELECT__##v << 0) & 0xf) | ||
| 190 | |||
| 191 | /** | ||
| 192 | * Register: HW_TIMROT_TIMCOUNT3 | ||
| 193 | * Address: 0x90 | ||
| 194 | * SCT: no | ||
| 195 | */ | ||
| 196 | #define HW_TIMROT_TIMCOUNT3 (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x90)) | ||
| 197 | #define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 16 | ||
| 198 | #define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 0xffff0000 | ||
| 199 | #define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v) (((v) << 16) & 0xffff0000) | ||
| 200 | #define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0 | ||
| 201 | #define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0xffff | ||
| 202 | #define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v) (((v) << 0) & 0xffff) | ||
| 203 | |||
| 204 | /** | ||
| 205 | * Register: HW_TIMROT_TIMCOUNTn | ||
| 206 | * Address: 0x30+n*0x20 | ||
| 207 | * SCT: no | ||
| 208 | */ | ||
| 209 | #define HW_TIMROT_TIMCOUNTn(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x30+(n)*0x20)) | ||
| 210 | #define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT 16 | ||
| 211 | #define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT 0xffff0000 | ||
| 212 | #define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v) (((v) << 16) & 0xffff0000) | ||
| 213 | #define BP_TIMROT_TIMCOUNTn_FIXED_COUNT 0 | ||
| 214 | #define BM_TIMROT_TIMCOUNTn_FIXED_COUNT 0xffff | ||
| 215 | #define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v) (((v) << 0) & 0xffff) | ||
| 216 | |||
| 217 | /** | ||
| 218 | * Register: HW_TIMROT_TIMCTRLn | ||
| 219 | * Address: 0x20+n*0x20 | ||
| 220 | * SCT: yes | ||
| 221 | */ | ||
| 222 | #define HW_TIMROT_TIMCTRLn(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x0)) | ||
| 223 | #define HW_TIMROT_TIMCTRLn_SET(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x4)) | ||
| 224 | #define HW_TIMROT_TIMCTRLn_CLR(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x8)) | ||
| 225 | #define HW_TIMROT_TIMCTRLn_TOG(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0xc)) | ||
| 226 | #define BP_TIMROT_TIMCTRLn_IRQ 15 | ||
| 227 | #define BM_TIMROT_TIMCTRLn_IRQ 0x8000 | ||
| 228 | #define BF_TIMROT_TIMCTRLn_IRQ(v) (((v) << 15) & 0x8000) | ||
| 229 | #define BP_TIMROT_TIMCTRLn_IRQ_EN 14 | ||
| 230 | #define BM_TIMROT_TIMCTRLn_IRQ_EN 0x4000 | ||
| 231 | #define BF_TIMROT_TIMCTRLn_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
| 232 | #define BP_TIMROT_TIMCTRLn_POLARITY 8 | ||
| 233 | #define BM_TIMROT_TIMCTRLn_POLARITY 0x100 | ||
| 234 | #define BF_TIMROT_TIMCTRLn_POLARITY(v) (((v) << 8) & 0x100) | ||
| 235 | #define BP_TIMROT_TIMCTRLn_UPDATE 7 | ||
| 236 | #define BM_TIMROT_TIMCTRLn_UPDATE 0x80 | ||
| 237 | #define BF_TIMROT_TIMCTRLn_UPDATE(v) (((v) << 7) & 0x80) | ||
| 238 | #define BP_TIMROT_TIMCTRLn_RELOAD 6 | ||
| 239 | #define BM_TIMROT_TIMCTRLn_RELOAD 0x40 | ||
| 240 | #define BF_TIMROT_TIMCTRLn_RELOAD(v) (((v) << 6) & 0x40) | ||
| 241 | #define BP_TIMROT_TIMCTRLn_PRESCALE 4 | ||
| 242 | #define BM_TIMROT_TIMCTRLn_PRESCALE 0x30 | ||
| 243 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 | ||
| 244 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 | ||
| 245 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 | ||
| 246 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 | ||
| 247 | #define BF_TIMROT_TIMCTRLn_PRESCALE(v) (((v) << 4) & 0x30) | ||
| 248 | #define BF_TIMROT_TIMCTRLn_PRESCALE_V(v) ((BV_TIMROT_TIMCTRLn_PRESCALE__##v << 4) & 0x30) | ||
| 249 | #define BP_TIMROT_TIMCTRLn_SELECT 0 | ||
| 250 | #define BM_TIMROT_TIMCTRLn_SELECT 0xf | ||
| 251 | #define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 | ||
| 252 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 | ||
| 253 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 | ||
| 254 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 | ||
| 255 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 | ||
| 256 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 | ||
| 257 | #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x6 | ||
| 258 | #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0x7 | ||
| 259 | #define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 | ||
| 260 | #define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0x9 | ||
| 261 | #define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xa | ||
| 262 | #define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xb | ||
| 263 | #define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xc | ||
| 264 | #define BF_TIMROT_TIMCTRLn_SELECT(v) (((v) << 0) & 0xf) | ||
| 265 | #define BF_TIMROT_TIMCTRLn_SELECT_V(v) ((BV_TIMROT_TIMCTRLn_SELECT__##v << 0) & 0xf) | ||
| 266 | |||
| 267 | #endif /* __HEADERGEN__STMP3600__TIMROT__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-uartapp.h b/firmware/target/arm/imx233/regs/stmp3600/regs-uartapp.h new file mode 100644 index 0000000000..62442f3ef3 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-uartapp.h | |||
| @@ -0,0 +1,371 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__UARTAPP__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__UARTAPP__H__ | ||
| 25 | |||
| 26 | #define REGS_UARTAPP_BASE (0x8006c000) | ||
| 27 | |||
| 28 | #define REGS_UARTAPP_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_UARTAPP_CTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_UARTAPP_CTRL0 (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_UARTAPP_CTRL0_SET (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_UARTAPP_CTRL0_CLR (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_UARTAPP_CTRL0_TOG (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_UARTAPP_CTRL0_SFTRST 31 | ||
| 40 | #define BM_UARTAPP_CTRL0_SFTRST 0x80000000 | ||
| 41 | #define BF_UARTAPP_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_UARTAPP_CTRL0_CLKGATE 30 | ||
| 43 | #define BM_UARTAPP_CTRL0_CLKGATE 0x40000000 | ||
| 44 | #define BF_UARTAPP_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_UARTAPP_CTRL0_RUN 28 | ||
| 46 | #define BM_UARTAPP_CTRL0_RUN 0x10000000 | ||
| 47 | #define BF_UARTAPP_CTRL0_RUN(v) (((v) << 28) & 0x10000000) | ||
| 48 | #define BP_UARTAPP_CTRL0_RX_SOURCE 25 | ||
| 49 | #define BM_UARTAPP_CTRL0_RX_SOURCE 0x2000000 | ||
| 50 | #define BF_UARTAPP_CTRL0_RX_SOURCE(v) (((v) << 25) & 0x2000000) | ||
| 51 | #define BP_UARTAPP_CTRL0_RXTO_ENABLE 24 | ||
| 52 | #define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x1000000 | ||
| 53 | #define BF_UARTAPP_CTRL0_RXTO_ENABLE(v) (((v) << 24) & 0x1000000) | ||
| 54 | #define BP_UARTAPP_CTRL0_RXTIMEOUT 16 | ||
| 55 | #define BM_UARTAPP_CTRL0_RXTIMEOUT 0xff0000 | ||
| 56 | #define BF_UARTAPP_CTRL0_RXTIMEOUT(v) (((v) << 16) & 0xff0000) | ||
| 57 | #define BP_UARTAPP_CTRL0_XFER_COUNT 0 | ||
| 58 | #define BM_UARTAPP_CTRL0_XFER_COUNT 0xffff | ||
| 59 | #define BF_UARTAPP_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
| 60 | |||
| 61 | /** | ||
| 62 | * Register: HW_UARTAPP_CTRL1 | ||
| 63 | * Address: 0x10 | ||
| 64 | * SCT: yes | ||
| 65 | */ | ||
| 66 | #define HW_UARTAPP_CTRL1 (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0x0)) | ||
| 67 | #define HW_UARTAPP_CTRL1_SET (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0x4)) | ||
| 68 | #define HW_UARTAPP_CTRL1_CLR (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0x8)) | ||
| 69 | #define HW_UARTAPP_CTRL1_TOG (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0xc)) | ||
| 70 | #define BP_UARTAPP_CTRL1_RUN 28 | ||
| 71 | #define BM_UARTAPP_CTRL1_RUN 0x10000000 | ||
| 72 | #define BF_UARTAPP_CTRL1_RUN(v) (((v) << 28) & 0x10000000) | ||
| 73 | #define BP_UARTAPP_CTRL1_XFER_COUNT 0 | ||
| 74 | #define BM_UARTAPP_CTRL1_XFER_COUNT 0xffff | ||
| 75 | #define BF_UARTAPP_CTRL1_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
| 76 | |||
| 77 | /** | ||
| 78 | * Register: HW_UARTAPP_CTRL2 | ||
| 79 | * Address: 0x20 | ||
| 80 | * SCT: yes | ||
| 81 | */ | ||
| 82 | #define HW_UARTAPP_CTRL2 (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0x0)) | ||
| 83 | #define HW_UARTAPP_CTRL2_SET (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0x4)) | ||
| 84 | #define HW_UARTAPP_CTRL2_CLR (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0x8)) | ||
| 85 | #define HW_UARTAPP_CTRL2_TOG (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0xc)) | ||
| 86 | #define BP_UARTAPP_CTRL2_INVERT_RTS 31 | ||
| 87 | #define BM_UARTAPP_CTRL2_INVERT_RTS 0x80000000 | ||
| 88 | #define BF_UARTAPP_CTRL2_INVERT_RTS(v) (((v) << 31) & 0x80000000) | ||
| 89 | #define BP_UARTAPP_CTRL2_INVERT_CTS 30 | ||
| 90 | #define BM_UARTAPP_CTRL2_INVERT_CTS 0x40000000 | ||
| 91 | #define BF_UARTAPP_CTRL2_INVERT_CTS(v) (((v) << 30) & 0x40000000) | ||
| 92 | #define BP_UARTAPP_CTRL2_INVERT_TX 29 | ||
| 93 | #define BM_UARTAPP_CTRL2_INVERT_TX 0x20000000 | ||
| 94 | #define BF_UARTAPP_CTRL2_INVERT_TX(v) (((v) << 29) & 0x20000000) | ||
| 95 | #define BP_UARTAPP_CTRL2_INVERT_RX 28 | ||
| 96 | #define BM_UARTAPP_CTRL2_INVERT_RX 0x10000000 | ||
| 97 | #define BF_UARTAPP_CTRL2_INVERT_RX(v) (((v) << 28) & 0x10000000) | ||
| 98 | #define BP_UARTAPP_CTRL2_DMAONERR 26 | ||
| 99 | #define BM_UARTAPP_CTRL2_DMAONERR 0x4000000 | ||
| 100 | #define BF_UARTAPP_CTRL2_DMAONERR(v) (((v) << 26) & 0x4000000) | ||
| 101 | #define BP_UARTAPP_CTRL2_TXDMAE 25 | ||
| 102 | #define BM_UARTAPP_CTRL2_TXDMAE 0x2000000 | ||
| 103 | #define BF_UARTAPP_CTRL2_TXDMAE(v) (((v) << 25) & 0x2000000) | ||
| 104 | #define BP_UARTAPP_CTRL2_RXDMAE 24 | ||
| 105 | #define BM_UARTAPP_CTRL2_RXDMAE 0x1000000 | ||
| 106 | #define BF_UARTAPP_CTRL2_RXDMAE(v) (((v) << 24) & 0x1000000) | ||
| 107 | #define BP_UARTAPP_CTRL2_RXIFLSEL 20 | ||
| 108 | #define BM_UARTAPP_CTRL2_RXIFLSEL 0x700000 | ||
| 109 | #define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY 0x0 | ||
| 110 | #define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER 0x1 | ||
| 111 | #define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF 0x2 | ||
| 112 | #define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS 0x3 | ||
| 113 | #define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
| 114 | #define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5 0x5 | ||
| 115 | #define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6 0x6 | ||
| 116 | #define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7 0x7 | ||
| 117 | #define BF_UARTAPP_CTRL2_RXIFLSEL(v) (((v) << 20) & 0x700000) | ||
| 118 | #define BF_UARTAPP_CTRL2_RXIFLSEL_V(v) ((BV_UARTAPP_CTRL2_RXIFLSEL__##v << 20) & 0x700000) | ||
| 119 | #define BP_UARTAPP_CTRL2_TXIFLSEL 16 | ||
| 120 | #define BM_UARTAPP_CTRL2_TXIFLSEL 0x70000 | ||
| 121 | #define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY 0x0 | ||
| 122 | #define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER 0x1 | ||
| 123 | #define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF 0x2 | ||
| 124 | #define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS 0x3 | ||
| 125 | #define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
| 126 | #define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5 0x5 | ||
| 127 | #define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6 0x6 | ||
| 128 | #define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7 0x7 | ||
| 129 | #define BF_UARTAPP_CTRL2_TXIFLSEL(v) (((v) << 16) & 0x70000) | ||
| 130 | #define BF_UARTAPP_CTRL2_TXIFLSEL_V(v) ((BV_UARTAPP_CTRL2_TXIFLSEL__##v << 16) & 0x70000) | ||
| 131 | #define BP_UARTAPP_CTRL2_CTSEN 15 | ||
| 132 | #define BM_UARTAPP_CTRL2_CTSEN 0x8000 | ||
| 133 | #define BF_UARTAPP_CTRL2_CTSEN(v) (((v) << 15) & 0x8000) | ||
| 134 | #define BP_UARTAPP_CTRL2_RTSEN 14 | ||
| 135 | #define BM_UARTAPP_CTRL2_RTSEN 0x4000 | ||
| 136 | #define BF_UARTAPP_CTRL2_RTSEN(v) (((v) << 14) & 0x4000) | ||
| 137 | #define BP_UARTAPP_CTRL2_OUT2 13 | ||
| 138 | #define BM_UARTAPP_CTRL2_OUT2 0x2000 | ||
| 139 | #define BF_UARTAPP_CTRL2_OUT2(v) (((v) << 13) & 0x2000) | ||
| 140 | #define BP_UARTAPP_CTRL2_OUT1 12 | ||
| 141 | #define BM_UARTAPP_CTRL2_OUT1 0x1000 | ||
| 142 | #define BF_UARTAPP_CTRL2_OUT1(v) (((v) << 12) & 0x1000) | ||
| 143 | #define BP_UARTAPP_CTRL2_RTS 11 | ||
| 144 | #define BM_UARTAPP_CTRL2_RTS 0x800 | ||
| 145 | #define BF_UARTAPP_CTRL2_RTS(v) (((v) << 11) & 0x800) | ||
| 146 | #define BP_UARTAPP_CTRL2_DTR 10 | ||
| 147 | #define BM_UARTAPP_CTRL2_DTR 0x400 | ||
| 148 | #define BF_UARTAPP_CTRL2_DTR(v) (((v) << 10) & 0x400) | ||
| 149 | #define BP_UARTAPP_CTRL2_RXE 9 | ||
| 150 | #define BM_UARTAPP_CTRL2_RXE 0x200 | ||
| 151 | #define BF_UARTAPP_CTRL2_RXE(v) (((v) << 9) & 0x200) | ||
| 152 | #define BP_UARTAPP_CTRL2_TXE 8 | ||
| 153 | #define BM_UARTAPP_CTRL2_TXE 0x100 | ||
| 154 | #define BF_UARTAPP_CTRL2_TXE(v) (((v) << 8) & 0x100) | ||
| 155 | #define BP_UARTAPP_CTRL2_LBE 7 | ||
| 156 | #define BM_UARTAPP_CTRL2_LBE 0x80 | ||
| 157 | #define BF_UARTAPP_CTRL2_LBE(v) (((v) << 7) & 0x80) | ||
| 158 | #define BP_UARTAPP_CTRL2_SIRLP 2 | ||
| 159 | #define BM_UARTAPP_CTRL2_SIRLP 0x4 | ||
| 160 | #define BF_UARTAPP_CTRL2_SIRLP(v) (((v) << 2) & 0x4) | ||
| 161 | #define BP_UARTAPP_CTRL2_SIREN 1 | ||
| 162 | #define BM_UARTAPP_CTRL2_SIREN 0x2 | ||
| 163 | #define BF_UARTAPP_CTRL2_SIREN(v) (((v) << 1) & 0x2) | ||
| 164 | #define BP_UARTAPP_CTRL2_UARTEN 0 | ||
| 165 | #define BM_UARTAPP_CTRL2_UARTEN 0x1 | ||
| 166 | #define BF_UARTAPP_CTRL2_UARTEN(v) (((v) << 0) & 0x1) | ||
| 167 | |||
| 168 | /** | ||
| 169 | * Register: HW_UARTAPP_LINECTRL | ||
| 170 | * Address: 0x30 | ||
| 171 | * SCT: yes | ||
| 172 | */ | ||
| 173 | #define HW_UARTAPP_LINECTRL (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0x0)) | ||
| 174 | #define HW_UARTAPP_LINECTRL_SET (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0x4)) | ||
| 175 | #define HW_UARTAPP_LINECTRL_CLR (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0x8)) | ||
| 176 | #define HW_UARTAPP_LINECTRL_TOG (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0xc)) | ||
| 177 | #define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16 | ||
| 178 | #define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xffff0000 | ||
| 179 | #define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v) (((v) << 16) & 0xffff0000) | ||
| 180 | #define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8 | ||
| 181 | #define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x3f00 | ||
| 182 | #define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v) (((v) << 8) & 0x3f00) | ||
| 183 | #define BP_UARTAPP_LINECTRL_SPS 7 | ||
| 184 | #define BM_UARTAPP_LINECTRL_SPS 0x80 | ||
| 185 | #define BF_UARTAPP_LINECTRL_SPS(v) (((v) << 7) & 0x80) | ||
| 186 | #define BP_UARTAPP_LINECTRL_WLEN 5 | ||
| 187 | #define BM_UARTAPP_LINECTRL_WLEN 0x60 | ||
| 188 | #define BF_UARTAPP_LINECTRL_WLEN(v) (((v) << 5) & 0x60) | ||
| 189 | #define BP_UARTAPP_LINECTRL_FEN 4 | ||
| 190 | #define BM_UARTAPP_LINECTRL_FEN 0x10 | ||
| 191 | #define BF_UARTAPP_LINECTRL_FEN(v) (((v) << 4) & 0x10) | ||
| 192 | #define BP_UARTAPP_LINECTRL_STP2 3 | ||
| 193 | #define BM_UARTAPP_LINECTRL_STP2 0x8 | ||
| 194 | #define BF_UARTAPP_LINECTRL_STP2(v) (((v) << 3) & 0x8) | ||
| 195 | #define BP_UARTAPP_LINECTRL_EPS 2 | ||
| 196 | #define BM_UARTAPP_LINECTRL_EPS 0x4 | ||
| 197 | #define BF_UARTAPP_LINECTRL_EPS(v) (((v) << 2) & 0x4) | ||
| 198 | #define BP_UARTAPP_LINECTRL_PEN 1 | ||
| 199 | #define BM_UARTAPP_LINECTRL_PEN 0x2 | ||
| 200 | #define BF_UARTAPP_LINECTRL_PEN(v) (((v) << 1) & 0x2) | ||
| 201 | #define BP_UARTAPP_LINECTRL_BRK 0 | ||
| 202 | #define BM_UARTAPP_LINECTRL_BRK 0x1 | ||
| 203 | #define BF_UARTAPP_LINECTRL_BRK(v) (((v) << 0) & 0x1) | ||
| 204 | |||
| 205 | /** | ||
| 206 | * Register: HW_UARTAPP_INTR | ||
| 207 | * Address: 0x40 | ||
| 208 | * SCT: yes | ||
| 209 | */ | ||
| 210 | #define HW_UARTAPP_INTR (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0x0)) | ||
| 211 | #define HW_UARTAPP_INTR_SET (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0x4)) | ||
| 212 | #define HW_UARTAPP_INTR_CLR (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0x8)) | ||
| 213 | #define HW_UARTAPP_INTR_TOG (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0xc)) | ||
| 214 | #define BP_UARTAPP_INTR_OEIEN 26 | ||
| 215 | #define BM_UARTAPP_INTR_OEIEN 0x4000000 | ||
| 216 | #define BF_UARTAPP_INTR_OEIEN(v) (((v) << 26) & 0x4000000) | ||
| 217 | #define BP_UARTAPP_INTR_BEIEN 25 | ||
| 218 | #define BM_UARTAPP_INTR_BEIEN 0x2000000 | ||
| 219 | #define BF_UARTAPP_INTR_BEIEN(v) (((v) << 25) & 0x2000000) | ||
| 220 | #define BP_UARTAPP_INTR_PEIEN 24 | ||
| 221 | #define BM_UARTAPP_INTR_PEIEN 0x1000000 | ||
| 222 | #define BF_UARTAPP_INTR_PEIEN(v) (((v) << 24) & 0x1000000) | ||
| 223 | #define BP_UARTAPP_INTR_FEIEN 23 | ||
| 224 | #define BM_UARTAPP_INTR_FEIEN 0x800000 | ||
| 225 | #define BF_UARTAPP_INTR_FEIEN(v) (((v) << 23) & 0x800000) | ||
| 226 | #define BP_UARTAPP_INTR_RTIEN 22 | ||
| 227 | #define BM_UARTAPP_INTR_RTIEN 0x400000 | ||
| 228 | #define BF_UARTAPP_INTR_RTIEN(v) (((v) << 22) & 0x400000) | ||
| 229 | #define BP_UARTAPP_INTR_TXIEN 21 | ||
| 230 | #define BM_UARTAPP_INTR_TXIEN 0x200000 | ||
| 231 | #define BF_UARTAPP_INTR_TXIEN(v) (((v) << 21) & 0x200000) | ||
| 232 | #define BP_UARTAPP_INTR_RXIEN 20 | ||
| 233 | #define BM_UARTAPP_INTR_RXIEN 0x100000 | ||
| 234 | #define BF_UARTAPP_INTR_RXIEN(v) (((v) << 20) & 0x100000) | ||
| 235 | #define BP_UARTAPP_INTR_DSRMIEN 19 | ||
| 236 | #define BM_UARTAPP_INTR_DSRMIEN 0x80000 | ||
| 237 | #define BF_UARTAPP_INTR_DSRMIEN(v) (((v) << 19) & 0x80000) | ||
| 238 | #define BP_UARTAPP_INTR_DCDMIEN 18 | ||
| 239 | #define BM_UARTAPP_INTR_DCDMIEN 0x40000 | ||
| 240 | #define BF_UARTAPP_INTR_DCDMIEN(v) (((v) << 18) & 0x40000) | ||
| 241 | #define BP_UARTAPP_INTR_CTSMIEN 17 | ||
| 242 | #define BM_UARTAPP_INTR_CTSMIEN 0x20000 | ||
| 243 | #define BF_UARTAPP_INTR_CTSMIEN(v) (((v) << 17) & 0x20000) | ||
| 244 | #define BP_UARTAPP_INTR_RIMIEN 16 | ||
| 245 | #define BM_UARTAPP_INTR_RIMIEN 0x10000 | ||
| 246 | #define BF_UARTAPP_INTR_RIMIEN(v) (((v) << 16) & 0x10000) | ||
| 247 | #define BP_UARTAPP_INTR_OEIS 10 | ||
| 248 | #define BM_UARTAPP_INTR_OEIS 0x400 | ||
| 249 | #define BF_UARTAPP_INTR_OEIS(v) (((v) << 10) & 0x400) | ||
| 250 | #define BP_UARTAPP_INTR_BEIS 9 | ||
| 251 | #define BM_UARTAPP_INTR_BEIS 0x200 | ||
| 252 | #define BF_UARTAPP_INTR_BEIS(v) (((v) << 9) & 0x200) | ||
| 253 | #define BP_UARTAPP_INTR_PEIS 8 | ||
| 254 | #define BM_UARTAPP_INTR_PEIS 0x100 | ||
| 255 | #define BF_UARTAPP_INTR_PEIS(v) (((v) << 8) & 0x100) | ||
| 256 | #define BP_UARTAPP_INTR_FEIS 7 | ||
| 257 | #define BM_UARTAPP_INTR_FEIS 0x80 | ||
| 258 | #define BF_UARTAPP_INTR_FEIS(v) (((v) << 7) & 0x80) | ||
| 259 | #define BP_UARTAPP_INTR_RTIS 6 | ||
| 260 | #define BM_UARTAPP_INTR_RTIS 0x40 | ||
| 261 | #define BF_UARTAPP_INTR_RTIS(v) (((v) << 6) & 0x40) | ||
| 262 | #define BP_UARTAPP_INTR_TXIS 5 | ||
| 263 | #define BM_UARTAPP_INTR_TXIS 0x20 | ||
| 264 | #define BF_UARTAPP_INTR_TXIS(v) (((v) << 5) & 0x20) | ||
| 265 | #define BP_UARTAPP_INTR_RXIS 4 | ||
| 266 | #define BM_UARTAPP_INTR_RXIS 0x10 | ||
| 267 | #define BF_UARTAPP_INTR_RXIS(v) (((v) << 4) & 0x10) | ||
| 268 | #define BP_UARTAPP_INTR_DSRMIS 3 | ||
| 269 | #define BM_UARTAPP_INTR_DSRMIS 0x8 | ||
| 270 | #define BF_UARTAPP_INTR_DSRMIS(v) (((v) << 3) & 0x8) | ||
| 271 | #define BP_UARTAPP_INTR_DCDMIS 2 | ||
| 272 | #define BM_UARTAPP_INTR_DCDMIS 0x4 | ||
| 273 | #define BF_UARTAPP_INTR_DCDMIS(v) (((v) << 2) & 0x4) | ||
| 274 | #define BP_UARTAPP_INTR_CTSMIS 1 | ||
| 275 | #define BM_UARTAPP_INTR_CTSMIS 0x2 | ||
| 276 | #define BF_UARTAPP_INTR_CTSMIS(v) (((v) << 1) & 0x2) | ||
| 277 | #define BP_UARTAPP_INTR_RIMIS 0 | ||
| 278 | #define BM_UARTAPP_INTR_RIMIS 0x1 | ||
| 279 | #define BF_UARTAPP_INTR_RIMIS(v) (((v) << 0) & 0x1) | ||
| 280 | |||
| 281 | /** | ||
| 282 | * Register: HW_UARTAPP_DATA | ||
| 283 | * Address: 0x50 | ||
| 284 | * SCT: no | ||
| 285 | */ | ||
| 286 | #define HW_UARTAPP_DATA (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x50)) | ||
| 287 | #define BP_UARTAPP_DATA_DATA 0 | ||
| 288 | #define BM_UARTAPP_DATA_DATA 0xffffffff | ||
| 289 | #define BF_UARTAPP_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 290 | |||
| 291 | /** | ||
| 292 | * Register: HW_UARTAPP_STAT | ||
| 293 | * Address: 0x60 | ||
| 294 | * SCT: no | ||
| 295 | */ | ||
| 296 | #define HW_UARTAPP_STAT (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x60)) | ||
| 297 | #define BP_UARTAPP_STAT_PRESENT 31 | ||
| 298 | #define BM_UARTAPP_STAT_PRESENT 0x80000000 | ||
| 299 | #define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE 0x0 | ||
| 300 | #define BV_UARTAPP_STAT_PRESENT__AVAILABLE 0x1 | ||
| 301 | #define BF_UARTAPP_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 302 | #define BF_UARTAPP_STAT_PRESENT_V(v) ((BV_UARTAPP_STAT_PRESENT__##v << 31) & 0x80000000) | ||
| 303 | #define BP_UARTAPP_STAT_HISPEED 30 | ||
| 304 | #define BM_UARTAPP_STAT_HISPEED 0x40000000 | ||
| 305 | #define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE 0x0 | ||
| 306 | #define BV_UARTAPP_STAT_HISPEED__AVAILABLE 0x1 | ||
| 307 | #define BF_UARTAPP_STAT_HISPEED(v) (((v) << 30) & 0x40000000) | ||
| 308 | #define BF_UARTAPP_STAT_HISPEED_V(v) ((BV_UARTAPP_STAT_HISPEED__##v << 30) & 0x40000000) | ||
| 309 | #define BP_UARTAPP_STAT_BUSY 29 | ||
| 310 | #define BM_UARTAPP_STAT_BUSY 0x20000000 | ||
| 311 | #define BF_UARTAPP_STAT_BUSY(v) (((v) << 29) & 0x20000000) | ||
| 312 | #define BP_UARTAPP_STAT_CTS 28 | ||
| 313 | #define BM_UARTAPP_STAT_CTS 0x10000000 | ||
| 314 | #define BF_UARTAPP_STAT_CTS(v) (((v) << 28) & 0x10000000) | ||
| 315 | #define BP_UARTAPP_STAT_TXFE 27 | ||
| 316 | #define BM_UARTAPP_STAT_TXFE 0x8000000 | ||
| 317 | #define BF_UARTAPP_STAT_TXFE(v) (((v) << 27) & 0x8000000) | ||
| 318 | #define BP_UARTAPP_STAT_RXFF 26 | ||
| 319 | #define BM_UARTAPP_STAT_RXFF 0x4000000 | ||
| 320 | #define BF_UARTAPP_STAT_RXFF(v) (((v) << 26) & 0x4000000) | ||
| 321 | #define BP_UARTAPP_STAT_TXFF 25 | ||
| 322 | #define BM_UARTAPP_STAT_TXFF 0x2000000 | ||
| 323 | #define BF_UARTAPP_STAT_TXFF(v) (((v) << 25) & 0x2000000) | ||
| 324 | #define BP_UARTAPP_STAT_RXFE 24 | ||
| 325 | #define BM_UARTAPP_STAT_RXFE 0x1000000 | ||
| 326 | #define BF_UARTAPP_STAT_RXFE(v) (((v) << 24) & 0x1000000) | ||
| 327 | #define BP_UARTAPP_STAT_RXBYTE_INVALID 20 | ||
| 328 | #define BM_UARTAPP_STAT_RXBYTE_INVALID 0xf00000 | ||
| 329 | #define BF_UARTAPP_STAT_RXBYTE_INVALID(v) (((v) << 20) & 0xf00000) | ||
| 330 | #define BP_UARTAPP_STAT_OERR 19 | ||
| 331 | #define BM_UARTAPP_STAT_OERR 0x80000 | ||
| 332 | #define BF_UARTAPP_STAT_OERR(v) (((v) << 19) & 0x80000) | ||
| 333 | #define BP_UARTAPP_STAT_BERR 18 | ||
| 334 | #define BM_UARTAPP_STAT_BERR 0x40000 | ||
| 335 | #define BF_UARTAPP_STAT_BERR(v) (((v) << 18) & 0x40000) | ||
| 336 | #define BP_UARTAPP_STAT_PERR 17 | ||
| 337 | #define BM_UARTAPP_STAT_PERR 0x20000 | ||
| 338 | #define BF_UARTAPP_STAT_PERR(v) (((v) << 17) & 0x20000) | ||
| 339 | #define BP_UARTAPP_STAT_FERR 16 | ||
| 340 | #define BM_UARTAPP_STAT_FERR 0x10000 | ||
| 341 | #define BF_UARTAPP_STAT_FERR(v) (((v) << 16) & 0x10000) | ||
| 342 | #define BP_UARTAPP_STAT_RXCOUNT 0 | ||
| 343 | #define BM_UARTAPP_STAT_RXCOUNT 0xffff | ||
| 344 | #define BF_UARTAPP_STAT_RXCOUNT(v) (((v) << 0) & 0xffff) | ||
| 345 | |||
| 346 | /** | ||
| 347 | * Register: HW_UARTAPP_DEBUG | ||
| 348 | * Address: 0x70 | ||
| 349 | * SCT: no | ||
| 350 | */ | ||
| 351 | #define HW_UARTAPP_DEBUG (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x70)) | ||
| 352 | #define BP_UARTAPP_DEBUG_TXDMARUN 5 | ||
| 353 | #define BM_UARTAPP_DEBUG_TXDMARUN 0x20 | ||
| 354 | #define BF_UARTAPP_DEBUG_TXDMARUN(v) (((v) << 5) & 0x20) | ||
| 355 | #define BP_UARTAPP_DEBUG_RXDMARUN 4 | ||
| 356 | #define BM_UARTAPP_DEBUG_RXDMARUN 0x10 | ||
| 357 | #define BF_UARTAPP_DEBUG_RXDMARUN(v) (((v) << 4) & 0x10) | ||
| 358 | #define BP_UARTAPP_DEBUG_TXCMDEND 3 | ||
| 359 | #define BM_UARTAPP_DEBUG_TXCMDEND 0x8 | ||
| 360 | #define BF_UARTAPP_DEBUG_TXCMDEND(v) (((v) << 3) & 0x8) | ||
| 361 | #define BP_UARTAPP_DEBUG_RXCMDEND 2 | ||
| 362 | #define BM_UARTAPP_DEBUG_RXCMDEND 0x4 | ||
| 363 | #define BF_UARTAPP_DEBUG_RXCMDEND(v) (((v) << 2) & 0x4) | ||
| 364 | #define BP_UARTAPP_DEBUG_TXDMARQ 1 | ||
| 365 | #define BM_UARTAPP_DEBUG_TXDMARQ 0x2 | ||
| 366 | #define BF_UARTAPP_DEBUG_TXDMARQ(v) (((v) << 1) & 0x2) | ||
| 367 | #define BP_UARTAPP_DEBUG_RXDMARQ 0 | ||
| 368 | #define BM_UARTAPP_DEBUG_RXDMARQ 0x1 | ||
| 369 | #define BF_UARTAPP_DEBUG_RXDMARQ(v) (((v) << 0) & 0x1) | ||
| 370 | |||
| 371 | #endif /* __HEADERGEN__STMP3600__UARTAPP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h b/firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h new file mode 100644 index 0000000000..9750330d9d --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h | |||
| @@ -0,0 +1,491 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__UARTDBG__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__UARTDBG__H__ | ||
| 25 | |||
| 26 | #define REGS_UARTDBG_BASE (0x80070000) | ||
| 27 | |||
| 28 | #define REGS_UARTDBG_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_UARTDBG_DR | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: no | ||
| 34 | */ | ||
| 35 | #define HW_UARTDBG_DR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x0)) | ||
| 36 | #define BP_UARTDBG_DR_UNAVAILABLE 16 | ||
| 37 | #define BM_UARTDBG_DR_UNAVAILABLE 0xffff0000 | ||
| 38 | #define BF_UARTDBG_DR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 39 | #define BP_UARTDBG_DR_RESERVED 12 | ||
| 40 | #define BM_UARTDBG_DR_RESERVED 0xf000 | ||
| 41 | #define BF_UARTDBG_DR_RESERVED(v) (((v) << 12) & 0xf000) | ||
| 42 | #define BP_UARTDBG_DR_OE 11 | ||
| 43 | #define BM_UARTDBG_DR_OE 0x800 | ||
| 44 | #define BF_UARTDBG_DR_OE(v) (((v) << 11) & 0x800) | ||
| 45 | #define BP_UARTDBG_DR_BE 10 | ||
| 46 | #define BM_UARTDBG_DR_BE 0x400 | ||
| 47 | #define BF_UARTDBG_DR_BE(v) (((v) << 10) & 0x400) | ||
| 48 | #define BP_UARTDBG_DR_PE 9 | ||
| 49 | #define BM_UARTDBG_DR_PE 0x200 | ||
| 50 | #define BF_UARTDBG_DR_PE(v) (((v) << 9) & 0x200) | ||
| 51 | #define BP_UARTDBG_DR_FE 8 | ||
| 52 | #define BM_UARTDBG_DR_FE 0x100 | ||
| 53 | #define BF_UARTDBG_DR_FE(v) (((v) << 8) & 0x100) | ||
| 54 | #define BP_UARTDBG_DR_DATA 0 | ||
| 55 | #define BM_UARTDBG_DR_DATA 0xff | ||
| 56 | #define BF_UARTDBG_DR_DATA(v) (((v) << 0) & 0xff) | ||
| 57 | |||
| 58 | /** | ||
| 59 | * Register: HW_UARTDBG_RSR_ECR | ||
| 60 | * Address: 0x4 | ||
| 61 | * SCT: no | ||
| 62 | */ | ||
| 63 | #define HW_UARTDBG_RSR_ECR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x4)) | ||
| 64 | #define BP_UARTDBG_RSR_ECR_UNAVAILABLE 8 | ||
| 65 | #define BM_UARTDBG_RSR_ECR_UNAVAILABLE 0xffffff00 | ||
| 66 | #define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
| 67 | #define BP_UARTDBG_RSR_ECR_EC 4 | ||
| 68 | #define BM_UARTDBG_RSR_ECR_EC 0xf0 | ||
| 69 | #define BF_UARTDBG_RSR_ECR_EC(v) (((v) << 4) & 0xf0) | ||
| 70 | #define BP_UARTDBG_RSR_ECR_OE 3 | ||
| 71 | #define BM_UARTDBG_RSR_ECR_OE 0x8 | ||
| 72 | #define BF_UARTDBG_RSR_ECR_OE(v) (((v) << 3) & 0x8) | ||
| 73 | #define BP_UARTDBG_RSR_ECR_BE 2 | ||
| 74 | #define BM_UARTDBG_RSR_ECR_BE 0x4 | ||
| 75 | #define BF_UARTDBG_RSR_ECR_BE(v) (((v) << 2) & 0x4) | ||
| 76 | #define BP_UARTDBG_RSR_ECR_PE 1 | ||
| 77 | #define BM_UARTDBG_RSR_ECR_PE 0x2 | ||
| 78 | #define BF_UARTDBG_RSR_ECR_PE(v) (((v) << 1) & 0x2) | ||
| 79 | #define BP_UARTDBG_RSR_ECR_FE 0 | ||
| 80 | #define BM_UARTDBG_RSR_ECR_FE 0x1 | ||
| 81 | #define BF_UARTDBG_RSR_ECR_FE(v) (((v) << 0) & 0x1) | ||
| 82 | |||
| 83 | /** | ||
| 84 | * Register: HW_UARTDBG_FR | ||
| 85 | * Address: 0x18 | ||
| 86 | * SCT: no | ||
| 87 | */ | ||
| 88 | #define HW_UARTDBG_FR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x18)) | ||
| 89 | #define BP_UARTDBG_FR_UNAVAILABLE 16 | ||
| 90 | #define BM_UARTDBG_FR_UNAVAILABLE 0xffff0000 | ||
| 91 | #define BF_UARTDBG_FR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 92 | #define BP_UARTDBG_FR_RESERVED 9 | ||
| 93 | #define BM_UARTDBG_FR_RESERVED 0xfe00 | ||
| 94 | #define BF_UARTDBG_FR_RESERVED(v) (((v) << 9) & 0xfe00) | ||
| 95 | #define BP_UARTDBG_FR_RI 8 | ||
| 96 | #define BM_UARTDBG_FR_RI 0x100 | ||
| 97 | #define BF_UARTDBG_FR_RI(v) (((v) << 8) & 0x100) | ||
| 98 | #define BP_UARTDBG_FR_TXFE 7 | ||
| 99 | #define BM_UARTDBG_FR_TXFE 0x80 | ||
| 100 | #define BF_UARTDBG_FR_TXFE(v) (((v) << 7) & 0x80) | ||
| 101 | #define BP_UARTDBG_FR_RXFF 6 | ||
| 102 | #define BM_UARTDBG_FR_RXFF 0x40 | ||
| 103 | #define BF_UARTDBG_FR_RXFF(v) (((v) << 6) & 0x40) | ||
| 104 | #define BP_UARTDBG_FR_TXFF 5 | ||
| 105 | #define BM_UARTDBG_FR_TXFF 0x20 | ||
| 106 | #define BF_UARTDBG_FR_TXFF(v) (((v) << 5) & 0x20) | ||
| 107 | #define BP_UARTDBG_FR_RXFE 4 | ||
| 108 | #define BM_UARTDBG_FR_RXFE 0x10 | ||
| 109 | #define BF_UARTDBG_FR_RXFE(v) (((v) << 4) & 0x10) | ||
| 110 | #define BP_UARTDBG_FR_BUSY 3 | ||
| 111 | #define BM_UARTDBG_FR_BUSY 0x8 | ||
| 112 | #define BF_UARTDBG_FR_BUSY(v) (((v) << 3) & 0x8) | ||
| 113 | #define BP_UARTDBG_FR_DCD 2 | ||
| 114 | #define BM_UARTDBG_FR_DCD 0x4 | ||
| 115 | #define BF_UARTDBG_FR_DCD(v) (((v) << 2) & 0x4) | ||
| 116 | #define BP_UARTDBG_FR_DSR 1 | ||
| 117 | #define BM_UARTDBG_FR_DSR 0x2 | ||
| 118 | #define BF_UARTDBG_FR_DSR(v) (((v) << 1) & 0x2) | ||
| 119 | #define BP_UARTDBG_FR_CTS 0 | ||
| 120 | #define BM_UARTDBG_FR_CTS 0x1 | ||
| 121 | #define BF_UARTDBG_FR_CTS(v) (((v) << 0) & 0x1) | ||
| 122 | |||
| 123 | /** | ||
| 124 | * Register: HW_UARTDBG_ILPR | ||
| 125 | * Address: 0x20 | ||
| 126 | * SCT: no | ||
| 127 | */ | ||
| 128 | #define HW_UARTDBG_ILPR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x20)) | ||
| 129 | #define BP_UARTDBG_ILPR_UNAVAILABLE 8 | ||
| 130 | #define BM_UARTDBG_ILPR_UNAVAILABLE 0xffffff00 | ||
| 131 | #define BF_UARTDBG_ILPR_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
| 132 | #define BP_UARTDBG_ILPR_ILPDVSR 0 | ||
| 133 | #define BM_UARTDBG_ILPR_ILPDVSR 0xff | ||
| 134 | #define BF_UARTDBG_ILPR_ILPDVSR(v) (((v) << 0) & 0xff) | ||
| 135 | |||
| 136 | /** | ||
| 137 | * Register: HW_UARTDBG_IBRD | ||
| 138 | * Address: 0x24 | ||
| 139 | * SCT: no | ||
| 140 | */ | ||
| 141 | #define HW_UARTDBG_IBRD (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x24)) | ||
| 142 | #define BP_UARTDBG_IBRD_UNAVAILABLE 16 | ||
| 143 | #define BM_UARTDBG_IBRD_UNAVAILABLE 0xffff0000 | ||
| 144 | #define BF_UARTDBG_IBRD_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 145 | #define BP_UARTDBG_IBRD_BAUD_DIVINT 0 | ||
| 146 | #define BM_UARTDBG_IBRD_BAUD_DIVINT 0xffff | ||
| 147 | #define BF_UARTDBG_IBRD_BAUD_DIVINT(v) (((v) << 0) & 0xffff) | ||
| 148 | |||
| 149 | /** | ||
| 150 | * Register: HW_UARTDBG_FBRD | ||
| 151 | * Address: 0x28 | ||
| 152 | * SCT: no | ||
| 153 | */ | ||
| 154 | #define HW_UARTDBG_FBRD (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x28)) | ||
| 155 | #define BP_UARTDBG_FBRD_UNAVAILABLE 8 | ||
| 156 | #define BM_UARTDBG_FBRD_UNAVAILABLE 0xffffff00 | ||
| 157 | #define BF_UARTDBG_FBRD_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
| 158 | #define BP_UARTDBG_FBRD_RESERVED 6 | ||
| 159 | #define BM_UARTDBG_FBRD_RESERVED 0xc0 | ||
| 160 | #define BF_UARTDBG_FBRD_RESERVED(v) (((v) << 6) & 0xc0) | ||
| 161 | #define BP_UARTDBG_FBRD_BAUD_DIVFRAC 0 | ||
| 162 | #define BM_UARTDBG_FBRD_BAUD_DIVFRAC 0x3f | ||
| 163 | #define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v) (((v) << 0) & 0x3f) | ||
| 164 | |||
| 165 | /** | ||
| 166 | * Register: HW_UARTDBG_LCR_H | ||
| 167 | * Address: 0x2c | ||
| 168 | * SCT: no | ||
| 169 | */ | ||
| 170 | #define HW_UARTDBG_LCR_H (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x2c)) | ||
| 171 | #define BP_UARTDBG_LCR_H_UNAVAILABLE 16 | ||
| 172 | #define BM_UARTDBG_LCR_H_UNAVAILABLE 0xffff0000 | ||
| 173 | #define BF_UARTDBG_LCR_H_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 174 | #define BP_UARTDBG_LCR_H_RESERVED 8 | ||
| 175 | #define BM_UARTDBG_LCR_H_RESERVED 0xff00 | ||
| 176 | #define BF_UARTDBG_LCR_H_RESERVED(v) (((v) << 8) & 0xff00) | ||
| 177 | #define BP_UARTDBG_LCR_H_SPS 7 | ||
| 178 | #define BM_UARTDBG_LCR_H_SPS 0x80 | ||
| 179 | #define BF_UARTDBG_LCR_H_SPS(v) (((v) << 7) & 0x80) | ||
| 180 | #define BP_UARTDBG_LCR_H_WLEN 5 | ||
| 181 | #define BM_UARTDBG_LCR_H_WLEN 0x60 | ||
| 182 | #define BF_UARTDBG_LCR_H_WLEN(v) (((v) << 5) & 0x60) | ||
| 183 | #define BP_UARTDBG_LCR_H_FEN 4 | ||
| 184 | #define BM_UARTDBG_LCR_H_FEN 0x10 | ||
| 185 | #define BF_UARTDBG_LCR_H_FEN(v) (((v) << 4) & 0x10) | ||
| 186 | #define BP_UARTDBG_LCR_H_STP2 3 | ||
| 187 | #define BM_UARTDBG_LCR_H_STP2 0x8 | ||
| 188 | #define BF_UARTDBG_LCR_H_STP2(v) (((v) << 3) & 0x8) | ||
| 189 | #define BP_UARTDBG_LCR_H_EPS 2 | ||
| 190 | #define BM_UARTDBG_LCR_H_EPS 0x4 | ||
| 191 | #define BF_UARTDBG_LCR_H_EPS(v) (((v) << 2) & 0x4) | ||
| 192 | #define BP_UARTDBG_LCR_H_PEN 1 | ||
| 193 | #define BM_UARTDBG_LCR_H_PEN 0x2 | ||
| 194 | #define BF_UARTDBG_LCR_H_PEN(v) (((v) << 1) & 0x2) | ||
| 195 | #define BP_UARTDBG_LCR_H_BRK 0 | ||
| 196 | #define BM_UARTDBG_LCR_H_BRK 0x1 | ||
| 197 | #define BF_UARTDBG_LCR_H_BRK(v) (((v) << 0) & 0x1) | ||
| 198 | |||
| 199 | /** | ||
| 200 | * Register: HW_UARTDBG_CR | ||
| 201 | * Address: 0x30 | ||
| 202 | * SCT: no | ||
| 203 | */ | ||
| 204 | #define HW_UARTDBG_CR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x30)) | ||
| 205 | #define BP_UARTDBG_CR_UNAVAILABLE 16 | ||
| 206 | #define BM_UARTDBG_CR_UNAVAILABLE 0xffff0000 | ||
| 207 | #define BF_UARTDBG_CR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 208 | #define BP_UARTDBG_CR_CTSEN 15 | ||
| 209 | #define BM_UARTDBG_CR_CTSEN 0x8000 | ||
| 210 | #define BF_UARTDBG_CR_CTSEN(v) (((v) << 15) & 0x8000) | ||
| 211 | #define BP_UARTDBG_CR_RTSEN 14 | ||
| 212 | #define BM_UARTDBG_CR_RTSEN 0x4000 | ||
| 213 | #define BF_UARTDBG_CR_RTSEN(v) (((v) << 14) & 0x4000) | ||
| 214 | #define BP_UARTDBG_CR_OUT2 13 | ||
| 215 | #define BM_UARTDBG_CR_OUT2 0x2000 | ||
| 216 | #define BF_UARTDBG_CR_OUT2(v) (((v) << 13) & 0x2000) | ||
| 217 | #define BP_UARTDBG_CR_OUT1 12 | ||
| 218 | #define BM_UARTDBG_CR_OUT1 0x1000 | ||
| 219 | #define BF_UARTDBG_CR_OUT1(v) (((v) << 12) & 0x1000) | ||
| 220 | #define BP_UARTDBG_CR_RTS 11 | ||
| 221 | #define BM_UARTDBG_CR_RTS 0x800 | ||
| 222 | #define BF_UARTDBG_CR_RTS(v) (((v) << 11) & 0x800) | ||
| 223 | #define BP_UARTDBG_CR_DTR 10 | ||
| 224 | #define BM_UARTDBG_CR_DTR 0x400 | ||
| 225 | #define BF_UARTDBG_CR_DTR(v) (((v) << 10) & 0x400) | ||
| 226 | #define BP_UARTDBG_CR_RXE 9 | ||
| 227 | #define BM_UARTDBG_CR_RXE 0x200 | ||
| 228 | #define BF_UARTDBG_CR_RXE(v) (((v) << 9) & 0x200) | ||
| 229 | #define BP_UARTDBG_CR_TXE 8 | ||
| 230 | #define BM_UARTDBG_CR_TXE 0x100 | ||
| 231 | #define BF_UARTDBG_CR_TXE(v) (((v) << 8) & 0x100) | ||
| 232 | #define BP_UARTDBG_CR_LBE 7 | ||
| 233 | #define BM_UARTDBG_CR_LBE 0x80 | ||
| 234 | #define BF_UARTDBG_CR_LBE(v) (((v) << 7) & 0x80) | ||
| 235 | #define BP_UARTDBG_CR_RESERVED 3 | ||
| 236 | #define BM_UARTDBG_CR_RESERVED 0x78 | ||
| 237 | #define BF_UARTDBG_CR_RESERVED(v) (((v) << 3) & 0x78) | ||
| 238 | #define BP_UARTDBG_CR_SIRLP 2 | ||
| 239 | #define BM_UARTDBG_CR_SIRLP 0x4 | ||
| 240 | #define BF_UARTDBG_CR_SIRLP(v) (((v) << 2) & 0x4) | ||
| 241 | #define BP_UARTDBG_CR_SIREN 1 | ||
| 242 | #define BM_UARTDBG_CR_SIREN 0x2 | ||
| 243 | #define BF_UARTDBG_CR_SIREN(v) (((v) << 1) & 0x2) | ||
| 244 | #define BP_UARTDBG_CR_UARTEN 0 | ||
| 245 | #define BM_UARTDBG_CR_UARTEN 0x1 | ||
| 246 | #define BF_UARTDBG_CR_UARTEN(v) (((v) << 0) & 0x1) | ||
| 247 | |||
| 248 | /** | ||
| 249 | * Register: HW_UARTDBG_IFLS | ||
| 250 | * Address: 0x34 | ||
| 251 | * SCT: no | ||
| 252 | */ | ||
| 253 | #define HW_UARTDBG_IFLS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x34)) | ||
| 254 | #define BP_UARTDBG_IFLS_UNAVAILABLE 16 | ||
| 255 | #define BM_UARTDBG_IFLS_UNAVAILABLE 0xffff0000 | ||
| 256 | #define BF_UARTDBG_IFLS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 257 | #define BP_UARTDBG_IFLS_RESERVED 6 | ||
| 258 | #define BM_UARTDBG_IFLS_RESERVED 0xffc0 | ||
| 259 | #define BF_UARTDBG_IFLS_RESERVED(v) (((v) << 6) & 0xffc0) | ||
| 260 | #define BP_UARTDBG_IFLS_RXIFLSEL 3 | ||
| 261 | #define BM_UARTDBG_IFLS_RXIFLSEL 0x38 | ||
| 262 | #define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY 0x0 | ||
| 263 | #define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER 0x1 | ||
| 264 | #define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF 0x2 | ||
| 265 | #define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS 0x3 | ||
| 266 | #define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
| 267 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5 0x5 | ||
| 268 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6 0x6 | ||
| 269 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7 0x7 | ||
| 270 | #define BF_UARTDBG_IFLS_RXIFLSEL(v) (((v) << 3) & 0x38) | ||
| 271 | #define BF_UARTDBG_IFLS_RXIFLSEL_V(v) ((BV_UARTDBG_IFLS_RXIFLSEL__##v << 3) & 0x38) | ||
| 272 | #define BP_UARTDBG_IFLS_TXIFLSEL 0 | ||
| 273 | #define BM_UARTDBG_IFLS_TXIFLSEL 0x7 | ||
| 274 | #define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY 0x0 | ||
| 275 | #define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER 0x1 | ||
| 276 | #define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF 0x2 | ||
| 277 | #define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS 0x3 | ||
| 278 | #define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
| 279 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5 0x5 | ||
| 280 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6 0x6 | ||
| 281 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7 0x7 | ||
| 282 | #define BF_UARTDBG_IFLS_TXIFLSEL(v) (((v) << 0) & 0x7) | ||
| 283 | #define BF_UARTDBG_IFLS_TXIFLSEL_V(v) ((BV_UARTDBG_IFLS_TXIFLSEL__##v << 0) & 0x7) | ||
| 284 | |||
| 285 | /** | ||
| 286 | * Register: HW_UARTDBG_IMSC | ||
| 287 | * Address: 0x38 | ||
| 288 | * SCT: no | ||
| 289 | */ | ||
| 290 | #define HW_UARTDBG_IMSC (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x38)) | ||
| 291 | #define BP_UARTDBG_IMSC_UNAVAILABLE 16 | ||
| 292 | #define BM_UARTDBG_IMSC_UNAVAILABLE 0xffff0000 | ||
| 293 | #define BF_UARTDBG_IMSC_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 294 | #define BP_UARTDBG_IMSC_RESERVED 11 | ||
| 295 | #define BM_UARTDBG_IMSC_RESERVED 0xf800 | ||
| 296 | #define BF_UARTDBG_IMSC_RESERVED(v) (((v) << 11) & 0xf800) | ||
| 297 | #define BP_UARTDBG_IMSC_OEIM 10 | ||
| 298 | #define BM_UARTDBG_IMSC_OEIM 0x400 | ||
| 299 | #define BF_UARTDBG_IMSC_OEIM(v) (((v) << 10) & 0x400) | ||
| 300 | #define BP_UARTDBG_IMSC_BEIM 9 | ||
| 301 | #define BM_UARTDBG_IMSC_BEIM 0x200 | ||
| 302 | #define BF_UARTDBG_IMSC_BEIM(v) (((v) << 9) & 0x200) | ||
| 303 | #define BP_UARTDBG_IMSC_PEIM 8 | ||
| 304 | #define BM_UARTDBG_IMSC_PEIM 0x100 | ||
| 305 | #define BF_UARTDBG_IMSC_PEIM(v) (((v) << 8) & 0x100) | ||
| 306 | #define BP_UARTDBG_IMSC_FEIM 7 | ||
| 307 | #define BM_UARTDBG_IMSC_FEIM 0x80 | ||
| 308 | #define BF_UARTDBG_IMSC_FEIM(v) (((v) << 7) & 0x80) | ||
| 309 | #define BP_UARTDBG_IMSC_RTIM 6 | ||
| 310 | #define BM_UARTDBG_IMSC_RTIM 0x40 | ||
| 311 | #define BF_UARTDBG_IMSC_RTIM(v) (((v) << 6) & 0x40) | ||
| 312 | #define BP_UARTDBG_IMSC_TXIM 5 | ||
| 313 | #define BM_UARTDBG_IMSC_TXIM 0x20 | ||
| 314 | #define BF_UARTDBG_IMSC_TXIM(v) (((v) << 5) & 0x20) | ||
| 315 | #define BP_UARTDBG_IMSC_RXIM 4 | ||
| 316 | #define BM_UARTDBG_IMSC_RXIM 0x10 | ||
| 317 | #define BF_UARTDBG_IMSC_RXIM(v) (((v) << 4) & 0x10) | ||
| 318 | #define BP_UARTDBG_IMSC_DSRMIM 3 | ||
| 319 | #define BM_UARTDBG_IMSC_DSRMIM 0x8 | ||
| 320 | #define BF_UARTDBG_IMSC_DSRMIM(v) (((v) << 3) & 0x8) | ||
| 321 | #define BP_UARTDBG_IMSC_DCDMIM 2 | ||
| 322 | #define BM_UARTDBG_IMSC_DCDMIM 0x4 | ||
| 323 | #define BF_UARTDBG_IMSC_DCDMIM(v) (((v) << 2) & 0x4) | ||
| 324 | #define BP_UARTDBG_IMSC_CTSMIM 1 | ||
| 325 | #define BM_UARTDBG_IMSC_CTSMIM 0x2 | ||
| 326 | #define BF_UARTDBG_IMSC_CTSMIM(v) (((v) << 1) & 0x2) | ||
| 327 | #define BP_UARTDBG_IMSC_RIMIM 0 | ||
| 328 | #define BM_UARTDBG_IMSC_RIMIM 0x1 | ||
| 329 | #define BF_UARTDBG_IMSC_RIMIM(v) (((v) << 0) & 0x1) | ||
| 330 | |||
| 331 | /** | ||
| 332 | * Register: HW_UARTDBG_RIS | ||
| 333 | * Address: 0x3c | ||
| 334 | * SCT: no | ||
| 335 | */ | ||
| 336 | #define HW_UARTDBG_RIS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x3c)) | ||
| 337 | #define BP_UARTDBG_RIS_UNAVAILABLE 16 | ||
| 338 | #define BM_UARTDBG_RIS_UNAVAILABLE 0xffff0000 | ||
| 339 | #define BF_UARTDBG_RIS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 340 | #define BP_UARTDBG_RIS_RESERVED 11 | ||
| 341 | #define BM_UARTDBG_RIS_RESERVED 0xf800 | ||
| 342 | #define BF_UARTDBG_RIS_RESERVED(v) (((v) << 11) & 0xf800) | ||
| 343 | #define BP_UARTDBG_RIS_OERIS 10 | ||
| 344 | #define BM_UARTDBG_RIS_OERIS 0x400 | ||
| 345 | #define BF_UARTDBG_RIS_OERIS(v) (((v) << 10) & 0x400) | ||
| 346 | #define BP_UARTDBG_RIS_BERIS 9 | ||
| 347 | #define BM_UARTDBG_RIS_BERIS 0x200 | ||
| 348 | #define BF_UARTDBG_RIS_BERIS(v) (((v) << 9) & 0x200) | ||
| 349 | #define BP_UARTDBG_RIS_PERIS 8 | ||
| 350 | #define BM_UARTDBG_RIS_PERIS 0x100 | ||
| 351 | #define BF_UARTDBG_RIS_PERIS(v) (((v) << 8) & 0x100) | ||
| 352 | #define BP_UARTDBG_RIS_FERIS 7 | ||
| 353 | #define BM_UARTDBG_RIS_FERIS 0x80 | ||
| 354 | #define BF_UARTDBG_RIS_FERIS(v) (((v) << 7) & 0x80) | ||
| 355 | #define BP_UARTDBG_RIS_RTRIS 6 | ||
| 356 | #define BM_UARTDBG_RIS_RTRIS 0x40 | ||
| 357 | #define BF_UARTDBG_RIS_RTRIS(v) (((v) << 6) & 0x40) | ||
| 358 | #define BP_UARTDBG_RIS_TXRIS 5 | ||
| 359 | #define BM_UARTDBG_RIS_TXRIS 0x20 | ||
| 360 | #define BF_UARTDBG_RIS_TXRIS(v) (((v) << 5) & 0x20) | ||
| 361 | #define BP_UARTDBG_RIS_RXRIS 4 | ||
| 362 | #define BM_UARTDBG_RIS_RXRIS 0x10 | ||
| 363 | #define BF_UARTDBG_RIS_RXRIS(v) (((v) << 4) & 0x10) | ||
| 364 | #define BP_UARTDBG_RIS_DSRRMIS 3 | ||
| 365 | #define BM_UARTDBG_RIS_DSRRMIS 0x8 | ||
| 366 | #define BF_UARTDBG_RIS_DSRRMIS(v) (((v) << 3) & 0x8) | ||
| 367 | #define BP_UARTDBG_RIS_DCDRMIS 2 | ||
| 368 | #define BM_UARTDBG_RIS_DCDRMIS 0x4 | ||
| 369 | #define BF_UARTDBG_RIS_DCDRMIS(v) (((v) << 2) & 0x4) | ||
| 370 | #define BP_UARTDBG_RIS_CTSRMIS 1 | ||
| 371 | #define BM_UARTDBG_RIS_CTSRMIS 0x2 | ||
| 372 | #define BF_UARTDBG_RIS_CTSRMIS(v) (((v) << 1) & 0x2) | ||
| 373 | #define BP_UARTDBG_RIS_RIRMIS 0 | ||
| 374 | #define BM_UARTDBG_RIS_RIRMIS 0x1 | ||
| 375 | #define BF_UARTDBG_RIS_RIRMIS(v) (((v) << 0) & 0x1) | ||
| 376 | |||
| 377 | /** | ||
| 378 | * Register: HW_UARTDBG_MIS | ||
| 379 | * Address: 0x40 | ||
| 380 | * SCT: no | ||
| 381 | */ | ||
| 382 | #define HW_UARTDBG_MIS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x40)) | ||
| 383 | #define BP_UARTDBG_MIS_UNAVAILABLE 16 | ||
| 384 | #define BM_UARTDBG_MIS_UNAVAILABLE 0xffff0000 | ||
| 385 | #define BF_UARTDBG_MIS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 386 | #define BP_UARTDBG_MIS_RESERVED 11 | ||
| 387 | #define BM_UARTDBG_MIS_RESERVED 0xf800 | ||
| 388 | #define BF_UARTDBG_MIS_RESERVED(v) (((v) << 11) & 0xf800) | ||
| 389 | #define BP_UARTDBG_MIS_OEMIS 10 | ||
| 390 | #define BM_UARTDBG_MIS_OEMIS 0x400 | ||
| 391 | #define BF_UARTDBG_MIS_OEMIS(v) (((v) << 10) & 0x400) | ||
| 392 | #define BP_UARTDBG_MIS_BEMIS 9 | ||
| 393 | #define BM_UARTDBG_MIS_BEMIS 0x200 | ||
| 394 | #define BF_UARTDBG_MIS_BEMIS(v) (((v) << 9) & 0x200) | ||
| 395 | #define BP_UARTDBG_MIS_PEMIS 8 | ||
| 396 | #define BM_UARTDBG_MIS_PEMIS 0x100 | ||
| 397 | #define BF_UARTDBG_MIS_PEMIS(v) (((v) << 8) & 0x100) | ||
| 398 | #define BP_UARTDBG_MIS_FEMIS 7 | ||
| 399 | #define BM_UARTDBG_MIS_FEMIS 0x80 | ||
| 400 | #define BF_UARTDBG_MIS_FEMIS(v) (((v) << 7) & 0x80) | ||
| 401 | #define BP_UARTDBG_MIS_RTMIS 6 | ||
| 402 | #define BM_UARTDBG_MIS_RTMIS 0x40 | ||
| 403 | #define BF_UARTDBG_MIS_RTMIS(v) (((v) << 6) & 0x40) | ||
| 404 | #define BP_UARTDBG_MIS_TXMIS 5 | ||
| 405 | #define BM_UARTDBG_MIS_TXMIS 0x20 | ||
| 406 | #define BF_UARTDBG_MIS_TXMIS(v) (((v) << 5) & 0x20) | ||
| 407 | #define BP_UARTDBG_MIS_RXMIS 4 | ||
| 408 | #define BM_UARTDBG_MIS_RXMIS 0x10 | ||
| 409 | #define BF_UARTDBG_MIS_RXMIS(v) (((v) << 4) & 0x10) | ||
| 410 | #define BP_UARTDBG_MIS_DSRMMIS 3 | ||
| 411 | #define BM_UARTDBG_MIS_DSRMMIS 0x8 | ||
| 412 | #define BF_UARTDBG_MIS_DSRMMIS(v) (((v) << 3) & 0x8) | ||
| 413 | #define BP_UARTDBG_MIS_DCDMMIS 2 | ||
| 414 | #define BM_UARTDBG_MIS_DCDMMIS 0x4 | ||
| 415 | #define BF_UARTDBG_MIS_DCDMMIS(v) (((v) << 2) & 0x4) | ||
| 416 | #define BP_UARTDBG_MIS_CTSMMIS 1 | ||
| 417 | #define BM_UARTDBG_MIS_CTSMMIS 0x2 | ||
| 418 | #define BF_UARTDBG_MIS_CTSMMIS(v) (((v) << 1) & 0x2) | ||
| 419 | #define BP_UARTDBG_MIS_RIMMIS 0 | ||
| 420 | #define BM_UARTDBG_MIS_RIMMIS 0x1 | ||
| 421 | #define BF_UARTDBG_MIS_RIMMIS(v) (((v) << 0) & 0x1) | ||
| 422 | |||
| 423 | /** | ||
| 424 | * Register: HW_UARTDBG_ICR | ||
| 425 | * Address: 0x44 | ||
| 426 | * SCT: no | ||
| 427 | */ | ||
| 428 | #define HW_UARTDBG_ICR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x44)) | ||
| 429 | #define BP_UARTDBG_ICR_UNAVAILABLE 16 | ||
| 430 | #define BM_UARTDBG_ICR_UNAVAILABLE 0xffff0000 | ||
| 431 | #define BF_UARTDBG_ICR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 432 | #define BP_UARTDBG_ICR_RESERVED 11 | ||
| 433 | #define BM_UARTDBG_ICR_RESERVED 0xf800 | ||
| 434 | #define BF_UARTDBG_ICR_RESERVED(v) (((v) << 11) & 0xf800) | ||
| 435 | #define BP_UARTDBG_ICR_OEIC 10 | ||
| 436 | #define BM_UARTDBG_ICR_OEIC 0x400 | ||
| 437 | #define BF_UARTDBG_ICR_OEIC(v) (((v) << 10) & 0x400) | ||
| 438 | #define BP_UARTDBG_ICR_BEIC 9 | ||
| 439 | #define BM_UARTDBG_ICR_BEIC 0x200 | ||
| 440 | #define BF_UARTDBG_ICR_BEIC(v) (((v) << 9) & 0x200) | ||
| 441 | #define BP_UARTDBG_ICR_PEIC 8 | ||
| 442 | #define BM_UARTDBG_ICR_PEIC 0x100 | ||
| 443 | #define BF_UARTDBG_ICR_PEIC(v) (((v) << 8) & 0x100) | ||
| 444 | #define BP_UARTDBG_ICR_FEIC 7 | ||
| 445 | #define BM_UARTDBG_ICR_FEIC 0x80 | ||
| 446 | #define BF_UARTDBG_ICR_FEIC(v) (((v) << 7) & 0x80) | ||
| 447 | #define BP_UARTDBG_ICR_RTIC 6 | ||
| 448 | #define BM_UARTDBG_ICR_RTIC 0x40 | ||
| 449 | #define BF_UARTDBG_ICR_RTIC(v) (((v) << 6) & 0x40) | ||
| 450 | #define BP_UARTDBG_ICR_TXIC 5 | ||
| 451 | #define BM_UARTDBG_ICR_TXIC 0x20 | ||
| 452 | #define BF_UARTDBG_ICR_TXIC(v) (((v) << 5) & 0x20) | ||
| 453 | #define BP_UARTDBG_ICR_RXIC 4 | ||
| 454 | #define BM_UARTDBG_ICR_RXIC 0x10 | ||
| 455 | #define BF_UARTDBG_ICR_RXIC(v) (((v) << 4) & 0x10) | ||
| 456 | #define BP_UARTDBG_ICR_DSRMIC 3 | ||
| 457 | #define BM_UARTDBG_ICR_DSRMIC 0x8 | ||
| 458 | #define BF_UARTDBG_ICR_DSRMIC(v) (((v) << 3) & 0x8) | ||
| 459 | #define BP_UARTDBG_ICR_DCDMIC 2 | ||
| 460 | #define BM_UARTDBG_ICR_DCDMIC 0x4 | ||
| 461 | #define BF_UARTDBG_ICR_DCDMIC(v) (((v) << 2) & 0x4) | ||
| 462 | #define BP_UARTDBG_ICR_CTSMIC 1 | ||
| 463 | #define BM_UARTDBG_ICR_CTSMIC 0x2 | ||
| 464 | #define BF_UARTDBG_ICR_CTSMIC(v) (((v) << 1) & 0x2) | ||
| 465 | #define BP_UARTDBG_ICR_RIMIC 0 | ||
| 466 | #define BM_UARTDBG_ICR_RIMIC 0x1 | ||
| 467 | #define BF_UARTDBG_ICR_RIMIC(v) (((v) << 0) & 0x1) | ||
| 468 | |||
| 469 | /** | ||
| 470 | * Register: HW_UARTDBG_DMACR | ||
| 471 | * Address: 0x48 | ||
| 472 | * SCT: no | ||
| 473 | */ | ||
| 474 | #define HW_UARTDBG_DMACR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x48)) | ||
| 475 | #define BP_UARTDBG_DMACR_UNAVAILABLE 16 | ||
| 476 | #define BM_UARTDBG_DMACR_UNAVAILABLE 0xffff0000 | ||
| 477 | #define BF_UARTDBG_DMACR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 478 | #define BP_UARTDBG_DMACR_RESERVED 3 | ||
| 479 | #define BM_UARTDBG_DMACR_RESERVED 0xfff8 | ||
| 480 | #define BF_UARTDBG_DMACR_RESERVED(v) (((v) << 3) & 0xfff8) | ||
| 481 | #define BP_UARTDBG_DMACR_DMAONERR 2 | ||
| 482 | #define BM_UARTDBG_DMACR_DMAONERR 0x4 | ||
| 483 | #define BF_UARTDBG_DMACR_DMAONERR(v) (((v) << 2) & 0x4) | ||
| 484 | #define BP_UARTDBG_DMACR_TXDMAE 1 | ||
| 485 | #define BM_UARTDBG_DMACR_TXDMAE 0x2 | ||
| 486 | #define BF_UARTDBG_DMACR_TXDMAE(v) (((v) << 1) & 0x2) | ||
| 487 | #define BP_UARTDBG_DMACR_RXDMAE 0 | ||
| 488 | #define BM_UARTDBG_DMACR_RXDMAE 0x1 | ||
| 489 | #define BF_UARTDBG_DMACR_RXDMAE(v) (((v) << 0) & 0x1) | ||
| 490 | |||
| 491 | #endif /* __HEADERGEN__STMP3600__UARTDBG__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-usbphy.h b/firmware/target/arm/imx233/regs/stmp3600/regs-usbphy.h new file mode 100644 index 0000000000..f255a3bc6c --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-usbphy.h | |||
| @@ -0,0 +1,405 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3600:2.3.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3600__USBPHY__H__ | ||
| 24 | #define __HEADERGEN__STMP3600__USBPHY__H__ | ||
| 25 | |||
| 26 | #define REGS_USBPHY_BASE (0x8007c000) | ||
| 27 | |||
| 28 | #define REGS_USBPHY_VERSION "2.3.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_USBPHY_PWD | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_USBPHY_PWD (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_USBPHY_PWD_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_USBPHY_PWD_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_USBPHY_PWD_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_USBPHY_PWD_RXPWDRX 20 | ||
| 40 | #define BM_USBPHY_PWD_RXPWDRX 0x100000 | ||
| 41 | #define BF_USBPHY_PWD_RXPWDRX(v) (((v) << 20) & 0x100000) | ||
| 42 | #define BP_USBPHY_PWD_RXPWDDIFF 19 | ||
| 43 | #define BM_USBPHY_PWD_RXPWDDIFF 0x80000 | ||
| 44 | #define BF_USBPHY_PWD_RXPWDDIFF(v) (((v) << 19) & 0x80000) | ||
| 45 | #define BP_USBPHY_PWD_RXPWD1PT1 18 | ||
| 46 | #define BM_USBPHY_PWD_RXPWD1PT1 0x40000 | ||
| 47 | #define BF_USBPHY_PWD_RXPWD1PT1(v) (((v) << 18) & 0x40000) | ||
| 48 | #define BP_USBPHY_PWD_RXPWDENV 17 | ||
| 49 | #define BM_USBPHY_PWD_RXPWDENV 0x20000 | ||
| 50 | #define BF_USBPHY_PWD_RXPWDENV(v) (((v) << 17) & 0x20000) | ||
| 51 | #define BP_USBPHY_PWD_TXPWDCOMP 14 | ||
| 52 | #define BM_USBPHY_PWD_TXPWDCOMP 0x4000 | ||
| 53 | #define BF_USBPHY_PWD_TXPWDCOMP(v) (((v) << 14) & 0x4000) | ||
| 54 | #define BP_USBPHY_PWD_TXPWDVBG 13 | ||
| 55 | #define BM_USBPHY_PWD_TXPWDVBG 0x2000 | ||
| 56 | #define BF_USBPHY_PWD_TXPWDVBG(v) (((v) << 13) & 0x2000) | ||
| 57 | #define BP_USBPHY_PWD_TXPWDV2I 12 | ||
| 58 | #define BM_USBPHY_PWD_TXPWDV2I 0x1000 | ||
| 59 | #define BF_USBPHY_PWD_TXPWDV2I(v) (((v) << 12) & 0x1000) | ||
| 60 | #define BP_USBPHY_PWD_TXPWDIBIAS 11 | ||
| 61 | #define BM_USBPHY_PWD_TXPWDIBIAS 0x800 | ||
| 62 | #define BF_USBPHY_PWD_TXPWDIBIAS(v) (((v) << 11) & 0x800) | ||
| 63 | #define BP_USBPHY_PWD_TXPWDFS 10 | ||
| 64 | #define BM_USBPHY_PWD_TXPWDFS 0x400 | ||
| 65 | #define BF_USBPHY_PWD_TXPWDFS(v) (((v) << 10) & 0x400) | ||
| 66 | |||
| 67 | /** | ||
| 68 | * Register: HW_USBPHY_TX | ||
| 69 | * Address: 0x10 | ||
| 70 | * SCT: yes | ||
| 71 | */ | ||
| 72 | #define HW_USBPHY_TX (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x0)) | ||
| 73 | #define HW_USBPHY_TX_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x4)) | ||
| 74 | #define HW_USBPHY_TX_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x8)) | ||
| 75 | #define HW_USBPHY_TX_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0xc)) | ||
| 76 | #define BP_USBPHY_TX_TXCMPOUT_STATUS 23 | ||
| 77 | #define BM_USBPHY_TX_TXCMPOUT_STATUS 0x800000 | ||
| 78 | #define BF_USBPHY_TX_TXCMPOUT_STATUS(v) (((v) << 23) & 0x800000) | ||
| 79 | #define BP_USBPHY_TX_TXENCAL45DP 21 | ||
| 80 | #define BM_USBPHY_TX_TXENCAL45DP 0x200000 | ||
| 81 | #define BF_USBPHY_TX_TXENCAL45DP(v) (((v) << 21) & 0x200000) | ||
| 82 | #define BP_USBPHY_TX_TXCAL45DP 16 | ||
| 83 | #define BM_USBPHY_TX_TXCAL45DP 0x1f0000 | ||
| 84 | #define BF_USBPHY_TX_TXCAL45DP(v) (((v) << 16) & 0x1f0000) | ||
| 85 | #define BP_USBPHY_TX_TXENCAL45DN 13 | ||
| 86 | #define BM_USBPHY_TX_TXENCAL45DN 0x2000 | ||
| 87 | #define BF_USBPHY_TX_TXENCAL45DN(v) (((v) << 13) & 0x2000) | ||
| 88 | #define BP_USBPHY_TX_TXCAL45DN 8 | ||
| 89 | #define BM_USBPHY_TX_TXCAL45DN 0x1f00 | ||
| 90 | #define BF_USBPHY_TX_TXCAL45DN(v) (((v) << 8) & 0x1f00) | ||
| 91 | #define BP_USBPHY_TX_TXCALIBRATE 7 | ||
| 92 | #define BM_USBPHY_TX_TXCALIBRATE 0x80 | ||
| 93 | #define BF_USBPHY_TX_TXCALIBRATE(v) (((v) << 7) & 0x80) | ||
| 94 | |||
| 95 | /** | ||
| 96 | * Register: HW_USBPHY_RX | ||
| 97 | * Address: 0x20 | ||
| 98 | * SCT: yes | ||
| 99 | */ | ||
| 100 | #define HW_USBPHY_RX (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x0)) | ||
| 101 | #define HW_USBPHY_RX_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x4)) | ||
| 102 | #define HW_USBPHY_RX_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x8)) | ||
| 103 | #define HW_USBPHY_RX_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0xc)) | ||
| 104 | #define BP_USBPHY_RX_RXDBYPASS 22 | ||
| 105 | #define BM_USBPHY_RX_RXDBYPASS 0x400000 | ||
| 106 | #define BF_USBPHY_RX_RXDBYPASS(v) (((v) << 22) & 0x400000) | ||
| 107 | #define BP_USBPHY_RX_DISCONADJ 4 | ||
| 108 | #define BM_USBPHY_RX_DISCONADJ 0x30 | ||
| 109 | #define BF_USBPHY_RX_DISCONADJ(v) (((v) << 4) & 0x30) | ||
| 110 | #define BP_USBPHY_RX_ENVADJ 0 | ||
| 111 | #define BM_USBPHY_RX_ENVADJ 0x3 | ||
| 112 | #define BF_USBPHY_RX_ENVADJ(v) (((v) << 0) & 0x3) | ||
| 113 | |||
| 114 | /** | ||
| 115 | * Register: HW_USBPHY_CTRL | ||
| 116 | * Address: 0x30 | ||
| 117 | * SCT: yes | ||
| 118 | */ | ||
| 119 | #define HW_USBPHY_CTRL (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x0)) | ||
| 120 | #define HW_USBPHY_CTRL_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x4)) | ||
| 121 | #define HW_USBPHY_CTRL_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x8)) | ||
| 122 | #define HW_USBPHY_CTRL_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0xc)) | ||
| 123 | #define BP_USBPHY_CTRL_SFTRST 31 | ||
| 124 | #define BM_USBPHY_CTRL_SFTRST 0x80000000 | ||
| 125 | #define BF_USBPHY_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 126 | #define BP_USBPHY_CTRL_CLKGATE 30 | ||
| 127 | #define BM_USBPHY_CTRL_CLKGATE 0x40000000 | ||
| 128 | #define BF_USBPHY_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 129 | #define BP_USBPHY_CTRL_UTMI_SUSPENDM 29 | ||
| 130 | #define BM_USBPHY_CTRL_UTMI_SUSPENDM 0x20000000 | ||
| 131 | #define BF_USBPHY_CTRL_UTMI_SUSPENDM(v) (((v) << 29) & 0x20000000) | ||
| 132 | #define BP_USBPHY_CTRL_RESUME_IRQ 10 | ||
| 133 | #define BM_USBPHY_CTRL_RESUME_IRQ 0x400 | ||
| 134 | #define BF_USBPHY_CTRL_RESUME_IRQ(v) (((v) << 10) & 0x400) | ||
| 135 | #define BP_USBPHY_CTRL_ENIRQRESUMEDETECT 9 | ||
| 136 | #define BM_USBPHY_CTRL_ENIRQRESUMEDETECT 0x200 | ||
| 137 | #define BF_USBPHY_CTRL_ENIRQRESUMEDETECT(v) (((v) << 9) & 0x200) | ||
| 138 | #define BP_USBPHY_CTRL_ENOTGIDDETECT 7 | ||
| 139 | #define BM_USBPHY_CTRL_ENOTGIDDETECT 0x80 | ||
| 140 | #define BF_USBPHY_CTRL_ENOTGIDDETECT(v) (((v) << 7) & 0x80) | ||
| 141 | #define BP_USBPHY_CTRL_ENDEVPLUGINDETECT 4 | ||
| 142 | #define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x10 | ||
| 143 | #define BF_USBPHY_CTRL_ENDEVPLUGINDETECT(v) (((v) << 4) & 0x10) | ||
| 144 | #define BP_USBPHY_CTRL_HOSTDISCONDETECT_IRQ 3 | ||
| 145 | #define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ 0x8 | ||
| 146 | #define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v) (((v) << 3) & 0x8) | ||
| 147 | #define BP_USBPHY_CTRL_ENIRQHOSTDISCON 2 | ||
| 148 | #define BM_USBPHY_CTRL_ENIRQHOSTDISCON 0x4 | ||
| 149 | #define BF_USBPHY_CTRL_ENIRQHOSTDISCON(v) (((v) << 2) & 0x4) | ||
| 150 | #define BP_USBPHY_CTRL_ENHOSTDISCONDETECT 1 | ||
| 151 | #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x2 | ||
| 152 | #define BF_USBPHY_CTRL_ENHOSTDISCONDETECT(v) (((v) << 1) & 0x2) | ||
| 153 | #define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT 0 | ||
| 154 | #define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT 0x1 | ||
| 155 | #define BF_USBPHY_CTRL_ENHSPRECHARGEXMIT(v) (((v) << 0) & 0x1) | ||
| 156 | |||
| 157 | /** | ||
| 158 | * Register: HW_USBPHY_STATUS | ||
| 159 | * Address: 0x40 | ||
| 160 | * SCT: no | ||
| 161 | */ | ||
| 162 | #define HW_USBPHY_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x40)) | ||
| 163 | #define BP_USBPHY_STATUS_RESUME_STATUS 10 | ||
| 164 | #define BM_USBPHY_STATUS_RESUME_STATUS 0x400 | ||
| 165 | #define BF_USBPHY_STATUS_RESUME_STATUS(v) (((v) << 10) & 0x400) | ||
| 166 | #define BP_USBPHY_STATUS_OTGID_STATUS 8 | ||
| 167 | #define BM_USBPHY_STATUS_OTGID_STATUS 0x100 | ||
| 168 | #define BF_USBPHY_STATUS_OTGID_STATUS(v) (((v) << 8) & 0x100) | ||
| 169 | #define BP_USBPHY_STATUS_DEVPLUGIN_STATUS 6 | ||
| 170 | #define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x40 | ||
| 171 | #define BF_USBPHY_STATUS_DEVPLUGIN_STATUS(v) (((v) << 6) & 0x40) | ||
| 172 | #define BP_USBPHY_STATUS_HOSTDISCONDETECT_STATUS 3 | ||
| 173 | #define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS 0x8 | ||
| 174 | #define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v) (((v) << 3) & 0x8) | ||
| 175 | |||
| 176 | /** | ||
| 177 | * Register: HW_USBPHY_DEBUG | ||
| 178 | * Address: 0x50 | ||
| 179 | * SCT: yes | ||
| 180 | */ | ||
| 181 | #define HW_USBPHY_DEBUG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x0)) | ||
| 182 | #define HW_USBPHY_DEBUG_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x4)) | ||
| 183 | #define HW_USBPHY_DEBUG_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x8)) | ||
| 184 | #define HW_USBPHY_DEBUG_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0xc)) | ||
| 185 | #define BP_USBPHY_DEBUG_CLKGATE 30 | ||
| 186 | #define BM_USBPHY_DEBUG_CLKGATE 0x40000000 | ||
| 187 | #define BF_USBPHY_DEBUG_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 188 | #define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH 25 | ||
| 189 | #define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH 0x1e000000 | ||
| 190 | #define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v) (((v) << 25) & 0x1e000000) | ||
| 191 | #define BP_USBPHY_DEBUG_ENSQUELCHRESET 24 | ||
| 192 | #define BM_USBPHY_DEBUG_ENSQUELCHRESET 0x1000000 | ||
| 193 | #define BF_USBPHY_DEBUG_ENSQUELCHRESET(v) (((v) << 24) & 0x1000000) | ||
| 194 | #define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT 16 | ||
| 195 | #define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT 0x1f0000 | ||
| 196 | #define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v) (((v) << 16) & 0x1f0000) | ||
| 197 | #define BP_USBPHY_DEBUG_ENTX2RXCOUNT 12 | ||
| 198 | #define BM_USBPHY_DEBUG_ENTX2RXCOUNT 0x1000 | ||
| 199 | #define BF_USBPHY_DEBUG_ENTX2RXCOUNT(v) (((v) << 12) & 0x1000) | ||
| 200 | #define BP_USBPHY_DEBUG_TX2RXCOUNT 8 | ||
| 201 | #define BM_USBPHY_DEBUG_TX2RXCOUNT 0xf00 | ||
| 202 | #define BF_USBPHY_DEBUG_TX2RXCOUNT(v) (((v) << 8) & 0xf00) | ||
| 203 | #define BP_USBPHY_DEBUG_ENHSTPULLDOWN 4 | ||
| 204 | #define BM_USBPHY_DEBUG_ENHSTPULLDOWN 0x30 | ||
| 205 | #define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v) (((v) << 4) & 0x30) | ||
| 206 | #define BP_USBPHY_DEBUG_HSTPULLDOWN 2 | ||
| 207 | #define BM_USBPHY_DEBUG_HSTPULLDOWN 0xc | ||
| 208 | #define BF_USBPHY_DEBUG_HSTPULLDOWN(v) (((v) << 2) & 0xc) | ||
| 209 | #define BP_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD 1 | ||
| 210 | #define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD 0x2 | ||
| 211 | #define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v) (((v) << 1) & 0x2) | ||
| 212 | #define BP_USBPHY_DEBUG_OTGIDPIOLOCK 0 | ||
| 213 | #define BM_USBPHY_DEBUG_OTGIDPIOLOCK 0x1 | ||
| 214 | #define BF_USBPHY_DEBUG_OTGIDPIOLOCK(v) (((v) << 0) & 0x1) | ||
| 215 | |||
| 216 | /** | ||
| 217 | * Register: HW_USBPHY_DEBUG0_STATUS | ||
| 218 | * Address: 0x60 | ||
| 219 | * SCT: no | ||
| 220 | */ | ||
| 221 | #define HW_USBPHY_DEBUG0_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x60)) | ||
| 222 | #define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 26 | ||
| 223 | #define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 0xfc000000 | ||
| 224 | #define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v) (((v) << 26) & 0xfc000000) | ||
| 225 | #define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 16 | ||
| 226 | #define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 0x3ff0000 | ||
| 227 | #define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
| 228 | #define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0 | ||
| 229 | #define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0xffff | ||
| 230 | #define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v) (((v) << 0) & 0xffff) | ||
| 231 | |||
| 232 | /** | ||
| 233 | * Register: HW_USBPHY_DEBUG1_STATUS | ||
| 234 | * Address: 0x70 | ||
| 235 | * SCT: no | ||
| 236 | */ | ||
| 237 | #define HW_USBPHY_DEBUG1_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70)) | ||
| 238 | #define BP_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA 16 | ||
| 239 | #define BM_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA 0xffff0000 | ||
| 240 | #define BF_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA(v) (((v) << 16) & 0xffff0000) | ||
| 241 | #define BP_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA 0 | ||
| 242 | #define BM_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA 0xffff | ||
| 243 | #define BF_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA(v) (((v) << 0) & 0xffff) | ||
| 244 | |||
| 245 | /** | ||
| 246 | * Register: HW_USBPHY_DEBUG2_STATUS | ||
| 247 | * Address: 0x80 | ||
| 248 | * SCT: no | ||
| 249 | */ | ||
| 250 | #define HW_USBPHY_DEBUG2_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x80)) | ||
| 251 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH 22 | ||
| 252 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH 0x400000 | ||
| 253 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH(v) (((v) << 22) & 0x400000) | ||
| 254 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_TXVALID 21 | ||
| 255 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_TXVALID 0x200000 | ||
| 256 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_TXVALID(v) (((v) << 21) & 0x200000) | ||
| 257 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT 20 | ||
| 258 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT 0x100000 | ||
| 259 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT(v) (((v) << 20) & 0x100000) | ||
| 260 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT 18 | ||
| 261 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT 0xc0000 | ||
| 262 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT(v) (((v) << 18) & 0xc0000) | ||
| 263 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_OPMODE 16 | ||
| 264 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_OPMODE 0x30000 | ||
| 265 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_OPMODE(v) (((v) << 16) & 0x30000) | ||
| 266 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE 6 | ||
| 267 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE 0xc0 | ||
| 268 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE(v) (((v) << 6) & 0xc0) | ||
| 269 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM 5 | ||
| 270 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM 0x20 | ||
| 271 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM(v) (((v) << 5) & 0x20) | ||
| 272 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH 4 | ||
| 273 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH 0x10 | ||
| 274 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH(v) (((v) << 4) & 0x10) | ||
| 275 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_RXVALID 3 | ||
| 276 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_RXVALID 0x8 | ||
| 277 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_RXVALID(v) (((v) << 3) & 0x8) | ||
| 278 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE 2 | ||
| 279 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE 0x4 | ||
| 280 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE(v) (((v) << 2) & 0x4) | ||
| 281 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_RXERROR 1 | ||
| 282 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_RXERROR 0x2 | ||
| 283 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_RXERROR(v) (((v) << 1) & 0x2) | ||
| 284 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_TXREADY 0 | ||
| 285 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_TXREADY 0x1 | ||
| 286 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_TXREADY(v) (((v) << 0) & 0x1) | ||
| 287 | |||
| 288 | /** | ||
| 289 | * Register: HW_USBPHY_DEBUG3_STATUS | ||
| 290 | * Address: 0x90 | ||
| 291 | * SCT: no | ||
| 292 | */ | ||
| 293 | #define HW_USBPHY_DEBUG3_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90)) | ||
| 294 | #define BP_USBPHY_DEBUG3_STATUS_B_CNT_FSM 28 | ||
| 295 | #define BM_USBPHY_DEBUG3_STATUS_B_CNT_FSM 0x70000000 | ||
| 296 | #define BF_USBPHY_DEBUG3_STATUS_B_CNT_FSM(v) (((v) << 28) & 0x70000000) | ||
| 297 | #define BP_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM 23 | ||
| 298 | #define BM_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM 0x3800000 | ||
| 299 | #define BF_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM(v) (((v) << 23) & 0x3800000) | ||
| 300 | #define BP_USBPHY_DEBUG3_STATUS_BIT_CNT 12 | ||
| 301 | #define BM_USBPHY_DEBUG3_STATUS_BIT_CNT 0x3ff000 | ||
| 302 | #define BF_USBPHY_DEBUG3_STATUS_BIT_CNT(v) (((v) << 12) & 0x3ff000) | ||
| 303 | #define BP_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM 8 | ||
| 304 | #define BM_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM 0xf00 | ||
| 305 | #define BF_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM(v) (((v) << 8) & 0xf00) | ||
| 306 | #define BP_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT 0 | ||
| 307 | #define BM_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT 0xff | ||
| 308 | #define BF_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT(v) (((v) << 0) & 0xff) | ||
| 309 | |||
| 310 | /** | ||
| 311 | * Register: HW_USBPHY_DEBUG4_STATUS | ||
| 312 | * Address: 0xa0 | ||
| 313 | * SCT: no | ||
| 314 | */ | ||
| 315 | #define HW_USBPHY_DEBUG4_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xa0)) | ||
| 316 | #define BP_USBPHY_DEBUG4_STATUS_BYTE_FSM 16 | ||
| 317 | #define BM_USBPHY_DEBUG4_STATUS_BYTE_FSM 0x1fff0000 | ||
| 318 | #define BF_USBPHY_DEBUG4_STATUS_BYTE_FSM(v) (((v) << 16) & 0x1fff0000) | ||
| 319 | #define BP_USBPHY_DEBUG4_STATUS_SND_FSM 0 | ||
| 320 | #define BM_USBPHY_DEBUG4_STATUS_SND_FSM 0x3fff | ||
| 321 | #define BF_USBPHY_DEBUG4_STATUS_SND_FSM(v) (((v) << 0) & 0x3fff) | ||
| 322 | |||
| 323 | /** | ||
| 324 | * Register: HW_USBPHY_DEBUG5_STATUS | ||
| 325 | * Address: 0xb0 | ||
| 326 | * SCT: no | ||
| 327 | */ | ||
| 328 | #define HW_USBPHY_DEBUG5_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xb0)) | ||
| 329 | #define BP_USBPHY_DEBUG5_STATUS_MAIN_FSM 24 | ||
| 330 | #define BM_USBPHY_DEBUG5_STATUS_MAIN_FSM 0xf000000 | ||
| 331 | #define BF_USBPHY_DEBUG5_STATUS_MAIN_FSM(v) (((v) << 24) & 0xf000000) | ||
| 332 | #define BP_USBPHY_DEBUG5_STATUS_SYNC_FSM 16 | ||
| 333 | #define BM_USBPHY_DEBUG5_STATUS_SYNC_FSM 0x3f0000 | ||
| 334 | #define BF_USBPHY_DEBUG5_STATUS_SYNC_FSM(v) (((v) << 16) & 0x3f0000) | ||
| 335 | #define BP_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM 12 | ||
| 336 | #define BM_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM 0x7000 | ||
| 337 | #define BF_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM(v) (((v) << 12) & 0x7000) | ||
| 338 | #define BP_USBPHY_DEBUG5_STATUS_SHIFT_FSM 8 | ||
| 339 | #define BM_USBPHY_DEBUG5_STATUS_SHIFT_FSM 0x700 | ||
| 340 | #define BF_USBPHY_DEBUG5_STATUS_SHIFT_FSM(v) (((v) << 8) & 0x700) | ||
| 341 | #define BP_USBPHY_DEBUG5_STATUS_SOF_FSM 0 | ||
| 342 | #define BM_USBPHY_DEBUG5_STATUS_SOF_FSM 0x1f | ||
| 343 | #define BF_USBPHY_DEBUG5_STATUS_SOF_FSM(v) (((v) << 0) & 0x1f) | ||
| 344 | |||
| 345 | /** | ||
| 346 | * Register: HW_USBPHY_DEBUG6_STATUS | ||
| 347 | * Address: 0xc0 | ||
| 348 | * SCT: no | ||
| 349 | */ | ||
| 350 | #define HW_USBPHY_DEBUG6_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xc0)) | ||
| 351 | #define BP_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM 8 | ||
| 352 | #define BM_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM 0x700 | ||
| 353 | #define BF_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM(v) (((v) << 8) & 0x700) | ||
| 354 | #define BP_USBPHY_DEBUG6_STATUS_EOP_FSM 0 | ||
| 355 | #define BM_USBPHY_DEBUG6_STATUS_EOP_FSM 0xff | ||
| 356 | #define BF_USBPHY_DEBUG6_STATUS_EOP_FSM(v) (((v) << 0) & 0xff) | ||
| 357 | |||
| 358 | /** | ||
| 359 | * Register: HW_USBPHY_DEBUG7_STATUS | ||
| 360 | * Address: 0xd0 | ||
| 361 | * SCT: no | ||
| 362 | */ | ||
| 363 | #define HW_USBPHY_DEBUG7_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xd0)) | ||
| 364 | #define BP_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM 28 | ||
| 365 | #define BM_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM 0x30000000 | ||
| 366 | #define BF_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM(v) (((v) << 28) & 0x30000000) | ||
| 367 | #define BP_USBPHY_DEBUG7_STATUS_BIT_CNT 24 | ||
| 368 | #define BM_USBPHY_DEBUG7_STATUS_BIT_CNT 0xf000000 | ||
| 369 | #define BF_USBPHY_DEBUG7_STATUS_BIT_CNT(v) (((v) << 24) & 0xf000000) | ||
| 370 | #define BP_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT 20 | ||
| 371 | #define BM_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT 0x700000 | ||
| 372 | #define BF_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT(v) (((v) << 20) & 0x700000) | ||
| 373 | #define BP_USBPHY_DEBUG7_STATUS_LD_FSM 16 | ||
| 374 | #define BM_USBPHY_DEBUG7_STATUS_LD_FSM 0x30000 | ||
| 375 | #define BF_USBPHY_DEBUG7_STATUS_LD_FSM(v) (((v) << 16) & 0x30000) | ||
| 376 | #define BP_USBPHY_DEBUG7_STATUS_FIFO_FSM 8 | ||
| 377 | #define BM_USBPHY_DEBUG7_STATUS_FIFO_FSM 0x3f00 | ||
| 378 | #define BF_USBPHY_DEBUG7_STATUS_FIFO_FSM(v) (((v) << 8) & 0x3f00) | ||
| 379 | #define BP_USBPHY_DEBUG7_STATUS_MAIN_FSM 4 | ||
| 380 | #define BM_USBPHY_DEBUG7_STATUS_MAIN_FSM 0xf0 | ||
| 381 | #define BF_USBPHY_DEBUG7_STATUS_MAIN_FSM(v) (((v) << 4) & 0xf0) | ||
| 382 | #define BP_USBPHY_DEBUG7_STATUS_EOP_FSM 0 | ||
| 383 | #define BM_USBPHY_DEBUG7_STATUS_EOP_FSM 0xf | ||
| 384 | #define BF_USBPHY_DEBUG7_STATUS_EOP_FSM(v) (((v) << 0) & 0xf) | ||
| 385 | |||
| 386 | /** | ||
| 387 | * Register: HW_USBPHY_DEBUG8_STATUS | ||
| 388 | * Address: 0xe0 | ||
| 389 | * SCT: no | ||
| 390 | */ | ||
| 391 | #define HW_USBPHY_DEBUG8_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xe0)) | ||
| 392 | #define BP_USBPHY_DEBUG8_STATUS_RX_SIE_FSM 28 | ||
| 393 | #define BM_USBPHY_DEBUG8_STATUS_RX_SIE_FSM 0xf0000000 | ||
| 394 | #define BF_USBPHY_DEBUG8_STATUS_RX_SIE_FSM(v) (((v) << 28) & 0xf0000000) | ||
| 395 | #define BP_USBPHY_DEBUG8_STATUS_TX_SIE_FSM 24 | ||
| 396 | #define BM_USBPHY_DEBUG8_STATUS_TX_SIE_FSM 0xf000000 | ||
| 397 | #define BF_USBPHY_DEBUG8_STATUS_TX_SIE_FSM(v) (((v) << 24) & 0xf000000) | ||
| 398 | #define BP_USBPHY_DEBUG8_STATUS_SHIFT_FSM 8 | ||
| 399 | #define BM_USBPHY_DEBUG8_STATUS_SHIFT_FSM 0x300 | ||
| 400 | #define BF_USBPHY_DEBUG8_STATUS_SHIFT_FSM(v) (((v) << 8) & 0x300) | ||
| 401 | #define BP_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM 0 | ||
| 402 | #define BM_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM 0x7f | ||
| 403 | #define BF_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM(v) (((v) << 0) & 0x7f) | ||
| 404 | |||
| 405 | #endif /* __HEADERGEN__STMP3600__USBPHY__H__ */ | ||