1 files changed, 372 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h b/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h
new file mode 100644
index 0000000000..bdf52c9308
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h
@@ -0,0 +1,372 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__GPMI__H__
+#define __HEADERGEN__STMP3600__GPMI__H__
+#define REGS_GPMI_BASE (0x8000c000)
+#define REGS_GPMI_VERSION "2.3.0"
+/**
+ * Register: HW_GPMI_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_GPMI_CTRL0                                   (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x0))
+#define HW_GPMI_CTRL0_SET                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x4))
+#define HW_GPMI_CTRL0_CLR                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x8))
+#define HW_GPMI_CTRL0_TOG                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0xc))
+#define BP_GPMI_CTRL0_SFTRST                            31
+#define BM_GPMI_CTRL0_SFTRST                            0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN                       0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET                     0x1
+#define BF_GPMI_CTRL0_SFTRST(v)                         (((v) << 31) & 0x80000000)
+#define BF_GPMI_CTRL0_SFTRST_V(v)                       ((BV_GPMI_CTRL0_SFTRST__##v << 31) & 0x80000000)
+#define BP_GPMI_CTRL0_CLKGATE                           30
+#define BM_GPMI_CTRL0_CLKGATE                           0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN                      0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS                  0x1
+#define BF_GPMI_CTRL0_CLKGATE(v)                        (((v) << 30) & 0x40000000)
+#define BF_GPMI_CTRL0_CLKGATE_V(v)                      ((BV_GPMI_CTRL0_CLKGATE__##v << 30) & 0x40000000)
+#define BP_GPMI_CTRL0_RUN                               29
+#define BM_GPMI_CTRL0_RUN                               0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE                         0x0
+#define BV_GPMI_CTRL0_RUN__BUSY                         0x1
+#define BF_GPMI_CTRL0_RUN(v)                            (((v) << 29) & 0x20000000)
+#define BF_GPMI_CTRL0_RUN_V(v)                          ((BV_GPMI_CTRL0_RUN__##v << 29) & 0x20000000)
+#define BP_GPMI_CTRL0_DEV_IRQ_EN                        28
+#define BM_GPMI_CTRL0_DEV_IRQ_EN                        0x10000000
+#define BF_GPMI_CTRL0_DEV_IRQ_EN(v)                     (((v) << 28) & 0x10000000)
+#define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN                    27
+#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN                    0x8000000
+#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v)                 (((v) << 27) & 0x8000000)
+#define BP_GPMI_CTRL0_UDMA                              26
+#define BM_GPMI_CTRL0_UDMA                              0x4000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED                    0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED                     0x1
+#define BF_GPMI_CTRL0_UDMA(v)                           (((v) << 26) & 0x4000000)
+#define BF_GPMI_CTRL0_UDMA_V(v)                         ((BV_GPMI_CTRL0_UDMA__##v << 26) & 0x4000000)
+#define BP_GPMI_CTRL0_COMMAND_MODE                      24
+#define BM_GPMI_CTRL0_COMMAND_MODE                      0x3000000
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE               0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ                0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE    0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY      0x3
+#define BF_GPMI_CTRL0_COMMAND_MODE(v)                   (((v) << 24) & 0x3000000)
+#define BF_GPMI_CTRL0_COMMAND_MODE_V(v)                 ((BV_GPMI_CTRL0_COMMAND_MODE__##v << 24) & 0x3000000)
+#define BP_GPMI_CTRL0_WORD_LENGTH                       23
+#define BM_GPMI_CTRL0_WORD_LENGTH                       0x800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT               0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT                0x1
+#define BF_GPMI_CTRL0_WORD_LENGTH(v)                    (((v) << 23) & 0x800000)
+#define BF_GPMI_CTRL0_WORD_LENGTH_V(v)                  ((BV_GPMI_CTRL0_WORD_LENGTH__##v << 23) & 0x800000)
+#define BP_GPMI_CTRL0_LOCK_CS                           22
+#define BM_GPMI_CTRL0_LOCK_CS                           0x400000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED                 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED                  0x1
+#define BF_GPMI_CTRL0_LOCK_CS(v)                        (((v) << 22) & 0x400000)
+#define BF_GPMI_CTRL0_LOCK_CS_V(v)                      ((BV_GPMI_CTRL0_LOCK_CS__##v << 22) & 0x400000)
+#define BP_GPMI_CTRL0_CS                                20
+#define BM_GPMI_CTRL0_CS                                0x300000
+#define BF_GPMI_CTRL0_CS(v)                             (((v) << 20) & 0x300000)
+#define BP_GPMI_CTRL0_ADDRESS                           17
+#define BM_GPMI_CTRL0_ADDRESS                           0xe0000
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA                0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE                 0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE                 0x2
+#define BF_GPMI_CTRL0_ADDRESS(v)                        (((v) << 17) & 0xe0000)
+#define BF_GPMI_CTRL0_ADDRESS_V(v)                      ((BV_GPMI_CTRL0_ADDRESS__##v << 17) & 0xe0000)
+#define BP_GPMI_CTRL0_ADDRESS_INCREMENT                 16
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT                 0x10000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED       0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED        0x1
+#define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v)              (((v) << 16) & 0x10000)
+#define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(v)            ((BV_GPMI_CTRL0_ADDRESS_INCREMENT__##v << 16) & 0x10000)
+#define BP_GPMI_CTRL0_XFER_COUNT                        0
+#define BM_GPMI_CTRL0_XFER_COUNT                        0xffff
+#define BF_GPMI_CTRL0_XFER_COUNT(v)                     (((v) << 0) & 0xffff)
+/**
+ * Register: HW_GPMI_COMPARE
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_GPMI_COMPARE                 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x10))
+#define BP_GPMI_COMPARE_MASK            16
+#define BM_GPMI_COMPARE_MASK            0xffff0000
+#define BF_GPMI_COMPARE_MASK(v)         (((v) << 16) & 0xffff0000)
+#define BP_GPMI_COMPARE_REFERENCE       0
+#define BM_GPMI_COMPARE_REFERENCE       0xffff
+#define BF_GPMI_COMPARE_REFERENCE(v)    (((v) << 0) & 0xffff)
+/**
+ * Register: HW_GPMI_CTRL1
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_GPMI_CTRL1                                   (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x0))
+#define HW_GPMI_CTRL1_SET                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x4))
+#define HW_GPMI_CTRL1_CLR                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x8))
+#define HW_GPMI_CTRL1_TOG                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0xc))
+#define BP_GPMI_CTRL1_DSAMPLE_TIME                      12
+#define BM_GPMI_CTRL1_DSAMPLE_TIME                      0x3000
+#define BF_GPMI_CTRL1_DSAMPLE_TIME(v)                   (((v) << 12) & 0x3000)
+#define BP_GPMI_CTRL1_DEV_IRQ                           10
+#define BM_GPMI_CTRL1_DEV_IRQ                           0x400
+#define BF_GPMI_CTRL1_DEV_IRQ(v)                        (((v) << 10) & 0x400)
+#define BP_GPMI_CTRL1_TIMEOUT_IRQ                       9
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ                       0x200
+#define BF_GPMI_CTRL1_TIMEOUT_IRQ(v)                    (((v) << 9) & 0x200)
+#define BP_GPMI_CTRL1_BURST_EN                          8
+#define BM_GPMI_CTRL1_BURST_EN                          0x100
+#define BF_GPMI_CTRL1_BURST_EN(v)                       (((v) << 8) & 0x100)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             7
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             0x80
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v)          (((v) << 7) & 0x80)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             6
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             0x40
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v)          (((v) << 6) & 0x40)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             5
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             0x20
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v)          (((v) << 5) & 0x20)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             4
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             0x10
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v)          (((v) << 4) & 0x10)
+#define BP_GPMI_CTRL1_DEV_RESET                         3
+#define BM_GPMI_CTRL1_DEV_RESET                         0x8
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED                0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED               0x1
+#define BF_GPMI_CTRL1_DEV_RESET(v)                      (((v) << 3) & 0x8)
+#define BF_GPMI_CTRL1_DEV_RESET_V(v)                    ((BV_GPMI_CTRL1_DEV_RESET__##v << 3) & 0x8)
+#define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY               2
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY               0x4
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW    0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH   0x1
+#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v)            (((v) << 2) & 0x4)
+#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v)          ((BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##v << 2) & 0x4)
+#define BP_GPMI_CTRL1_CAMERA_MODE                       1
+#define BM_GPMI_CTRL1_CAMERA_MODE                       0x2
+#define BF_GPMI_CTRL1_CAMERA_MODE(v)                    (((v) << 1) & 0x2)
+#define BP_GPMI_CTRL1_GPMI_MODE                         0
+#define BM_GPMI_CTRL1_GPMI_MODE                         0x1
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND                   0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA                    0x1
+#define BF_GPMI_CTRL1_GPMI_MODE(v)                      (((v) << 0) & 0x1)
+#define BF_GPMI_CTRL1_GPMI_MODE_V(v)                    ((BV_GPMI_CTRL1_GPMI_MODE__##v << 0) & 0x1)
+/**
+ * Register: HW_GPMI_TIMING0
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_GPMI_TIMING0                     (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x30))
+#define BP_GPMI_TIMING0_ADDRESS_SETUP       16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP       0xff0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)    (((v) << 16) & 0xff0000)
+#define BP_GPMI_TIMING0_DATA_HOLD           8
+#define BM_GPMI_TIMING0_DATA_HOLD           0xff00
+#define BF_GPMI_TIMING0_DATA_HOLD(v)        (((v) << 8) & 0xff00)
+#define BP_GPMI_TIMING0_DATA_SETUP          0
+#define BM_GPMI_TIMING0_DATA_SETUP          0xff
+#define BF_GPMI_TIMING0_DATA_SETUP(v)       (((v) << 0) & 0xff)
+/**
+ * Register: HW_GPMI_TIMING1
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_GPMI_TIMING1                         (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x40))
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     0xffff0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v)  (((v) << 16) & 0xffff0000)
+#define BP_GPMI_TIMING1_ATA_READY_TIMEOUT       0
+#define BM_GPMI_TIMING1_ATA_READY_TIMEOUT       0xffff
+#define BF_GPMI_TIMING1_ATA_READY_TIMEOUT(v)    (((v) << 0) & 0xffff)
+/**
+ * Register: HW_GPMI_TIMING2
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_GPMI_TIMING2                 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x50))
+#define BP_GPMI_TIMING2_UDMA_TRP        24
+#define BM_GPMI_TIMING2_UDMA_TRP        0xff000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v)     (((v) << 24) & 0xff000000)
+#define BP_GPMI_TIMING2_UDMA_ENV        16
+#define BM_GPMI_TIMING2_UDMA_ENV        0xff0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v)     (((v) << 16) & 0xff0000)
+#define BP_GPMI_TIMING2_UDMA_HOLD       8
+#define BM_GPMI_TIMING2_UDMA_HOLD       0xff00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v)    (((v) << 8) & 0xff00)
+#define BP_GPMI_TIMING2_UDMA_SETUP      0
+#define BM_GPMI_TIMING2_UDMA_SETUP      0xff
+#define BF_GPMI_TIMING2_UDMA_SETUP(v)   (((v) << 0) & 0xff)
+/**
+ * Register: HW_GPMI_DATA
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_GPMI_DATA            (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60))
+#define BP_GPMI_DATA_DATA       0
+#define BM_GPMI_DATA_DATA       0xffffffff
+#define BF_GPMI_DATA_DATA(v)    (((v) << 0) & 0xffffffff)
+/**
+ * Register: HW_GPMI_STAT
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_GPMI_STAT                        (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x70))
+#define BP_GPMI_STAT_PRESENT                31
+#define BM_GPMI_STAT_PRESENT                0x80000000
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE   0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE     0x1
+#define BF_GPMI_STAT_PRESENT(v)             (((v) << 31) & 0x80000000)
+#define BF_GPMI_STAT_PRESENT_V(v)           ((BV_GPMI_STAT_PRESENT__##v << 31) & 0x80000000)
+#define BP_GPMI_STAT_RDY_TIMEOUT            8
+#define BM_GPMI_STAT_RDY_TIMEOUT            0xf00
+#define BF_GPMI_STAT_RDY_TIMEOUT(v)         (((v) << 8) & 0xf00)
+#define BP_GPMI_STAT_ATA_IRQ                7
+#define BM_GPMI_STAT_ATA_IRQ                0x80
+#define BF_GPMI_STAT_ATA_IRQ(v)             (((v) << 7) & 0x80)
+#define BP_GPMI_STAT_FIFO_EMPTY             5
+#define BM_GPMI_STAT_FIFO_EMPTY             0x20
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY  0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY      0x1
+#define BF_GPMI_STAT_FIFO_EMPTY(v)          (((v) << 5) & 0x20)
+#define BF_GPMI_STAT_FIFO_EMPTY_V(v)        ((BV_GPMI_STAT_FIFO_EMPTY__##v << 5) & 0x20)
+#define BP_GPMI_STAT_FIFO_FULL              4
+#define BM_GPMI_STAT_FIFO_FULL              0x10
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL    0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL        0x1
+#define BF_GPMI_STAT_FIFO_FULL(v)           (((v) << 4) & 0x10)
+#define BF_GPMI_STAT_FIFO_FULL_V(v)         ((BV_GPMI_STAT_FIFO_FULL__##v << 4) & 0x10)
+#define BP_GPMI_STAT_DEV3_ERROR             3
+#define BM_GPMI_STAT_DEV3_ERROR             0x8
+#define BF_GPMI_STAT_DEV3_ERROR(v)          (((v) << 3) & 0x8)
+#define BP_GPMI_STAT_DEV2_ERROR             2
+#define BM_GPMI_STAT_DEV2_ERROR             0x4
+#define BF_GPMI_STAT_DEV2_ERROR(v)          (((v) << 2) & 0x4)
+#define BP_GPMI_STAT_DEV1_ERROR             1
+#define BM_GPMI_STAT_DEV1_ERROR             0x2
+#define BF_GPMI_STAT_DEV1_ERROR(v)          (((v) << 1) & 0x2)
+#define BP_GPMI_STAT_DEV0_ERROR             0
+#define BM_GPMI_STAT_DEV0_ERROR             0x1
+#define BF_GPMI_STAT_DEV0_ERROR(v)          (((v) << 0) & 0x1)
+/**
+ * Register: HW_GPMI_DEBUG
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_GPMI_DEBUG                           (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x80))
+#define BP_GPMI_DEBUG_READY3                    31
+#define BM_GPMI_DEBUG_READY3                    0x80000000
+#define BF_GPMI_DEBUG_READY3(v)                 (((v) << 31) & 0x80000000)
+#define BP_GPMI_DEBUG_READY2                    30
+#define BM_GPMI_DEBUG_READY2                    0x40000000
+#define BF_GPMI_DEBUG_READY2(v)                 (((v) << 30) & 0x40000000)
+#define BP_GPMI_DEBUG_READY1                    29
+#define BM_GPMI_DEBUG_READY1                    0x20000000
+#define BF_GPMI_DEBUG_READY1(v)                 (((v) << 29) & 0x20000000)
+#define BP_GPMI_DEBUG_READY0                    28
+#define BM_GPMI_DEBUG_READY0                    0x10000000
+#define BF_GPMI_DEBUG_READY0(v)                 (((v) << 28) & 0x10000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END3       27
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3       0x8000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v)    (((v) << 27) & 0x8000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END2       26
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2       0x4000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v)    (((v) << 26) & 0x4000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END1       25
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1       0x2000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v)    (((v) << 25) & 0x2000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END0       24
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0       0x1000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v)    (((v) << 24) & 0x1000000)
+#define BP_GPMI_DEBUG_SENSE3                    23
+#define BM_GPMI_DEBUG_SENSE3                    0x800000
+#define BF_GPMI_DEBUG_SENSE3(v)                 (((v) << 23) & 0x800000)
+#define BP_GPMI_DEBUG_SENSE2                    22
+#define BM_GPMI_DEBUG_SENSE2                    0x400000
+#define BF_GPMI_DEBUG_SENSE2(v)                 (((v) << 22) & 0x400000)
+#define BP_GPMI_DEBUG_SENSE1                    21
+#define BM_GPMI_DEBUG_SENSE1                    0x200000
+#define BF_GPMI_DEBUG_SENSE1(v)                 (((v) << 21) & 0x200000)
+#define BP_GPMI_DEBUG_SENSE0                    20
+#define BM_GPMI_DEBUG_SENSE0                    0x100000
+#define BF_GPMI_DEBUG_SENSE0(v)                 (((v) << 20) & 0x100000)
+#define BP_GPMI_DEBUG_DMAREQ3                   19
+#define BM_GPMI_DEBUG_DMAREQ3                   0x80000
+#define BF_GPMI_DEBUG_DMAREQ3(v)                (((v) << 19) & 0x80000)
+#define BP_GPMI_DEBUG_DMAREQ2                   18
+#define BM_GPMI_DEBUG_DMAREQ2                   0x40000
+#define BF_GPMI_DEBUG_DMAREQ2(v)                (((v) << 18) & 0x40000)
+#define BP_GPMI_DEBUG_DMAREQ1                   17
+#define BM_GPMI_DEBUG_DMAREQ1                   0x20000
+#define BF_GPMI_DEBUG_DMAREQ1(v)                (((v) << 17) & 0x20000)
+#define BP_GPMI_DEBUG_DMAREQ0                   16
+#define BM_GPMI_DEBUG_DMAREQ0                   0x10000
+#define BF_GPMI_DEBUG_DMAREQ0(v)                (((v) << 16) & 0x10000)
+#define BP_GPMI_DEBUG_CMD_END                   12
+#define BM_GPMI_DEBUG_CMD_END                   0xf000
+#define BF_GPMI_DEBUG_CMD_END(v)                (((v) << 12) & 0xf000)
+#define BP_GPMI_DEBUG_UDMA_STATE                8
+#define BM_GPMI_DEBUG_UDMA_STATE                0xf00
+#define BF_GPMI_DEBUG_UDMA_STATE(v)             (((v) << 8) & 0xf00)
+#define BP_GPMI_DEBUG_BUSY                      7
+#define BM_GPMI_DEBUG_BUSY                      0x80
+#define BV_GPMI_DEBUG_BUSY__DISABLED            0x0
+#define BV_GPMI_DEBUG_BUSY__ENABLED             0x1
+#define BF_GPMI_DEBUG_BUSY(v)                   (((v) << 7) & 0x80)
+#define BF_GPMI_DEBUG_BUSY_V(v)                 ((BV_GPMI_DEBUG_BUSY__##v << 7) & 0x80)
+#define BP_GPMI_DEBUG_PIN_STATE                 4
+#define BM_GPMI_DEBUG_PIN_STATE                 0x70
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE       0x0
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT     0x1
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR       0x2
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL      0x3
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE     0x4
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY     0x5
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD      0x6
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE       0x7
+#define BF_GPMI_DEBUG_PIN_STATE(v)              (((v) << 4) & 0x70)
+#define BF_GPMI_DEBUG_PIN_STATE_V(v)            ((BV_GPMI_DEBUG_PIN_STATE__##v << 4) & 0x70)
+#define BP_GPMI_DEBUG_MAIN_STATE                0
+#define BM_GPMI_DEBUG_MAIN_STATE                0xf
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE      0x0
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT    0x1
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE    0x2
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR    0x3
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ    0x4
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK    0x5
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF    0x6
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO    0x7
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR    0x8
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP     0x9
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE      0xa
+#define BF_GPMI_DEBUG_MAIN_STATE(v)             (((v) << 0) & 0xf)
+#define BF_GPMI_DEBUG_MAIN_STATE_V(v)           ((BV_GPMI_DEBUG_MAIN_STATE__##v << 0) & 0xf)
+#endif /* __HEADERGEN__STMP3600__GPMI__H__ */

diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h b/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h new file mode 100644 index 0000000000..bdf52c9308 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h
@@ -0,0 +1,372 @@
	1	/***************************************************************************
	2	* __________ __ ___.
	3	* Open \______ \ ____ ____ \| \| _\_ \|__ _______ ___
	4	* Source \| _// _ \_/ ___\\| \|/ /\| __ \ / _ \ \/ /
	5	* Jukebox \| \| ( <_> ) \___\| < \| \_\ ( <_> > < <
	6	* Firmware \|____\|_ /\____/ \___ >__\|_ \\|___ /\____/__/\_ \
	7	* \/ \/ \/ \/ \/
	8	* This file was automatically generated by headergen, DO NOT EDIT it.
	9	* headergen version: 2.1.7
	10	* XML versions: stmp3600:2.3.0
	11	*
	12	* Copyright (C) 2013 by Amaury Pouly
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License
	16	* as published by the Free Software Foundation; either version 2
	17	* of the License, or (at your option) any later version.
	18	*
	19	* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
	20	* KIND, either express or implied.
	21	*
	22	****************************************************************************/
	23	#ifndef __HEADERGEN__STMP3600__GPMI__H__
	24	#define __HEADERGEN__STMP3600__GPMI__H__
	25
	26	#define REGS_GPMI_BASE (0x8000c000)
	27
	28	#define REGS_GPMI_VERSION "2.3.0"
	29
	30	/**
	31	* Register: HW_GPMI_CTRL0
	32	* Address: 0
	33	* SCT: yes
	34	*/
	35	#define HW_GPMI_CTRL0 ((volatile unsigned long )(REGS_GPMI_BASE + 0x0 + 0x0))
	36	#define HW_GPMI_CTRL0_SET ((volatile unsigned long )(REGS_GPMI_BASE + 0x0 + 0x4))
	37	#define HW_GPMI_CTRL0_CLR ((volatile unsigned long )(REGS_GPMI_BASE + 0x0 + 0x8))
	38	#define HW_GPMI_CTRL0_TOG ((volatile unsigned long )(REGS_GPMI_BASE + 0x0 + 0xc))
	39	#define BP_GPMI_CTRL0_SFTRST 31
	40	#define BM_GPMI_CTRL0_SFTRST 0x80000000
	41	#define BV_GPMI_CTRL0_SFTRST__RUN 0x0
	42	#define BV_GPMI_CTRL0_SFTRST__RESET 0x1
	43	#define BF_GPMI_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000)
	44	#define BF_GPMI_CTRL0_SFTRST_V(v) ((BV_GPMI_CTRL0_SFTRST__##v << 31) & 0x80000000)
	45	#define BP_GPMI_CTRL0_CLKGATE 30
	46	#define BM_GPMI_CTRL0_CLKGATE 0x40000000
	47	#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0
	48	#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1
	49	#define BF_GPMI_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000)
	50	#define BF_GPMI_CTRL0_CLKGATE_V(v) ((BV_GPMI_CTRL0_CLKGATE__##v << 30) & 0x40000000)
	51	#define BP_GPMI_CTRL0_RUN 29
	52	#define BM_GPMI_CTRL0_RUN 0x20000000
	53	#define BV_GPMI_CTRL0_RUN__IDLE 0x0
	54	#define BV_GPMI_CTRL0_RUN__BUSY 0x1
	55	#define BF_GPMI_CTRL0_RUN(v) (((v) << 29) & 0x20000000)
	56	#define BF_GPMI_CTRL0_RUN_V(v) ((BV_GPMI_CTRL0_RUN__##v << 29) & 0x20000000)
	57	#define BP_GPMI_CTRL0_DEV_IRQ_EN 28
	58	#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000
	59	#define BF_GPMI_CTRL0_DEV_IRQ_EN(v) (((v) << 28) & 0x10000000)
	60	#define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN 27
	61	#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x8000000
	62	#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v) (((v) << 27) & 0x8000000)
	63	#define BP_GPMI_CTRL0_UDMA 26
	64	#define BM_GPMI_CTRL0_UDMA 0x4000000
	65	#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0
	66	#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1
	67	#define BF_GPMI_CTRL0_UDMA(v) (((v) << 26) & 0x4000000)
	68	#define BF_GPMI_CTRL0_UDMA_V(v) ((BV_GPMI_CTRL0_UDMA__##v << 26) & 0x4000000)
	69	#define BP_GPMI_CTRL0_COMMAND_MODE 24
	70	#define BM_GPMI_CTRL0_COMMAND_MODE 0x3000000
	71	#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
	72	#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
	73	#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
	74	#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
	75	#define BF_GPMI_CTRL0_COMMAND_MODE(v) (((v) << 24) & 0x3000000)
	76	#define BF_GPMI_CTRL0_COMMAND_MODE_V(v) ((BV_GPMI_CTRL0_COMMAND_MODE__##v << 24) & 0x3000000)
	77	#define BP_GPMI_CTRL0_WORD_LENGTH 23
	78	#define BM_GPMI_CTRL0_WORD_LENGTH 0x800000
	79	#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
	80	#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1
	81	#define BF_GPMI_CTRL0_WORD_LENGTH(v) (((v) << 23) & 0x800000)
	82	#define BF_GPMI_CTRL0_WORD_LENGTH_V(v) ((BV_GPMI_CTRL0_WORD_LENGTH__##v << 23) & 0x800000)
	83	#define BP_GPMI_CTRL0_LOCK_CS 22
	84	#define BM_GPMI_CTRL0_LOCK_CS 0x400000
	85	#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0
	86	#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1
	87	#define BF_GPMI_CTRL0_LOCK_CS(v) (((v) << 22) & 0x400000)
	88	#define BF_GPMI_CTRL0_LOCK_CS_V(v) ((BV_GPMI_CTRL0_LOCK_CS__##v << 22) & 0x400000)
	89	#define BP_GPMI_CTRL0_CS 20
	90	#define BM_GPMI_CTRL0_CS 0x300000
	91	#define BF_GPMI_CTRL0_CS(v) (((v) << 20) & 0x300000)
	92	#define BP_GPMI_CTRL0_ADDRESS 17
	93	#define BM_GPMI_CTRL0_ADDRESS 0xe0000
	94	#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
	95	#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
	96	#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
	97	#define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & 0xe0000)
	98	#define BF_GPMI_CTRL0_ADDRESS_V(v) ((BV_GPMI_CTRL0_ADDRESS__##v << 17) & 0xe0000)
	99	#define BP_GPMI_CTRL0_ADDRESS_INCREMENT 16
	100	#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x10000
	101	#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
	102	#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1
	103	#define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v) (((v) << 16) & 0x10000)
	104	#define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(v) ((BV_GPMI_CTRL0_ADDRESS_INCREMENT__##v << 16) & 0x10000)
	105	#define BP_GPMI_CTRL0_XFER_COUNT 0
	106	#define BM_GPMI_CTRL0_XFER_COUNT 0xffff
	107	#define BF_GPMI_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff)
	108
	109	/**
	110	* Register: HW_GPMI_COMPARE
	111	* Address: 0x10
	112	* SCT: no
	113	*/
	114	#define HW_GPMI_COMPARE ((volatile unsigned long )(REGS_GPMI_BASE + 0x10))
	115	#define BP_GPMI_COMPARE_MASK 16
	116	#define BM_GPMI_COMPARE_MASK 0xffff0000
	117	#define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & 0xffff0000)
	118	#define BP_GPMI_COMPARE_REFERENCE 0
	119	#define BM_GPMI_COMPARE_REFERENCE 0xffff
	120	#define BF_GPMI_COMPARE_REFERENCE(v) (((v) << 0) & 0xffff)
	121
	122	/**
	123	* Register: HW_GPMI_CTRL1
	124	* Address: 0x20
	125	* SCT: yes
	126	*/
	127	#define HW_GPMI_CTRL1 ((volatile unsigned long )(REGS_GPMI_BASE + 0x20 + 0x0))
	128	#define HW_GPMI_CTRL1_SET ((volatile unsigned long )(REGS_GPMI_BASE + 0x20 + 0x4))
	129	#define HW_GPMI_CTRL1_CLR ((volatile unsigned long )(REGS_GPMI_BASE + 0x20 + 0x8))
	130	#define HW_GPMI_CTRL1_TOG ((volatile unsigned long )(REGS_GPMI_BASE + 0x20 + 0xc))
	131	#define BP_GPMI_CTRL1_DSAMPLE_TIME 12
	132	#define BM_GPMI_CTRL1_DSAMPLE_TIME 0x3000
	133	#define BF_GPMI_CTRL1_DSAMPLE_TIME(v) (((v) << 12) & 0x3000)
	134	#define BP_GPMI_CTRL1_DEV_IRQ 10
	135	#define BM_GPMI_CTRL1_DEV_IRQ 0x400
	136	#define BF_GPMI_CTRL1_DEV_IRQ(v) (((v) << 10) & 0x400)
	137	#define BP_GPMI_CTRL1_TIMEOUT_IRQ 9
	138	#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x200
	139	#define BF_GPMI_CTRL1_TIMEOUT_IRQ(v) (((v) << 9) & 0x200)
	140	#define BP_GPMI_CTRL1_BURST_EN 8
	141	#define BM_GPMI_CTRL1_BURST_EN 0x100
	142	#define BF_GPMI_CTRL1_BURST_EN(v) (((v) << 8) & 0x100)
	143	#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 7
	144	#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 0x80
	145	#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v) (((v) << 7) & 0x80)
	146	#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 6
	147	#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 0x40
	148	#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v) (((v) << 6) & 0x40)
	149	#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 5
	150	#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 0x20
	151	#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v) (((v) << 5) & 0x20)
	152	#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 4
	153	#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 0x10
	154	#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v) (((v) << 4) & 0x10)
	155	#define BP_GPMI_CTRL1_DEV_RESET 3
	156	#define BM_GPMI_CTRL1_DEV_RESET 0x8
	157	#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0
	158	#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
	159	#define BF_GPMI_CTRL1_DEV_RESET(v) (((v) << 3) & 0x8)
	160	#define BF_GPMI_CTRL1_DEV_RESET_V(v) ((BV_GPMI_CTRL1_DEV_RESET__##v << 3) & 0x8)
	161	#define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY 2
	162	#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x4
	163	#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0
	164	#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
	165	#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v) (((v) << 2) & 0x4)
	166	#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v) ((BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##v << 2) & 0x4)
	167	#define BP_GPMI_CTRL1_CAMERA_MODE 1
	168	#define BM_GPMI_CTRL1_CAMERA_MODE 0x2
	169	#define BF_GPMI_CTRL1_CAMERA_MODE(v) (((v) << 1) & 0x2)
	170	#define BP_GPMI_CTRL1_GPMI_MODE 0
	171	#define BM_GPMI_CTRL1_GPMI_MODE 0x1
	172	#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
	173	#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1
	174	#define BF_GPMI_CTRL1_GPMI_MODE(v) (((v) << 0) & 0x1)
	175	#define BF_GPMI_CTRL1_GPMI_MODE_V(v) ((BV_GPMI_CTRL1_GPMI_MODE__##v << 0) & 0x1)
	176
	177	/**
	178	* Register: HW_GPMI_TIMING0
	179	* Address: 0x30
	180	* SCT: no
	181	*/
	182	#define HW_GPMI_TIMING0 ((volatile unsigned long )(REGS_GPMI_BASE + 0x30))
	183	#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
	184	#define BM_GPMI_TIMING0_ADDRESS_SETUP 0xff0000
	185	#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) (((v) << 16) & 0xff0000)
	186	#define BP_GPMI_TIMING0_DATA_HOLD 8
	187	#define BM_GPMI_TIMING0_DATA_HOLD 0xff00
	188	#define BF_GPMI_TIMING0_DATA_HOLD(v) (((v) << 8) & 0xff00)
	189	#define BP_GPMI_TIMING0_DATA_SETUP 0
	190	#define BM_GPMI_TIMING0_DATA_SETUP 0xff
	191	#define BF_GPMI_TIMING0_DATA_SETUP(v) (((v) << 0) & 0xff)
	192
	193	/**
	194	* Register: HW_GPMI_TIMING1
	195	* Address: 0x40
	196	* SCT: no
	197	*/
	198	#define HW_GPMI_TIMING1 ((volatile unsigned long )(REGS_GPMI_BASE + 0x40))
	199	#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
	200	#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xffff0000
	201	#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) (((v) << 16) & 0xffff0000)
	202	#define BP_GPMI_TIMING1_ATA_READY_TIMEOUT 0
	203	#define BM_GPMI_TIMING1_ATA_READY_TIMEOUT 0xffff
	204	#define BF_GPMI_TIMING1_ATA_READY_TIMEOUT(v) (((v) << 0) & 0xffff)
	205
	206	/**
	207	* Register: HW_GPMI_TIMING2
	208	* Address: 0x50
	209	* SCT: no
	210	*/
	211	#define HW_GPMI_TIMING2 ((volatile unsigned long )(REGS_GPMI_BASE + 0x50))
	212	#define BP_GPMI_TIMING2_UDMA_TRP 24
	213	#define BM_GPMI_TIMING2_UDMA_TRP 0xff000000
	214	#define BF_GPMI_TIMING2_UDMA_TRP(v) (((v) << 24) & 0xff000000)
	215	#define BP_GPMI_TIMING2_UDMA_ENV 16
	216	#define BM_GPMI_TIMING2_UDMA_ENV 0xff0000
	217	#define BF_GPMI_TIMING2_UDMA_ENV(v) (((v) << 16) & 0xff0000)
	218	#define BP_GPMI_TIMING2_UDMA_HOLD 8
	219	#define BM_GPMI_TIMING2_UDMA_HOLD 0xff00
	220	#define BF_GPMI_TIMING2_UDMA_HOLD(v) (((v) << 8) & 0xff00)
	221	#define BP_GPMI_TIMING2_UDMA_SETUP 0
	222	#define BM_GPMI_TIMING2_UDMA_SETUP 0xff
	223	#define BF_GPMI_TIMING2_UDMA_SETUP(v) (((v) << 0) & 0xff)
	224
	225	/**
	226	* Register: HW_GPMI_DATA
	227	* Address: 0x60
	228	* SCT: no
	229	*/
	230	#define HW_GPMI_DATA ((volatile unsigned long )(REGS_GPMI_BASE + 0x60))
	231	#define BP_GPMI_DATA_DATA 0
	232	#define BM_GPMI_DATA_DATA 0xffffffff
	233	#define BF_GPMI_DATA_DATA(v) (((v) << 0) & 0xffffffff)
	234
	235	/**
	236	* Register: HW_GPMI_STAT
	237	* Address: 0x70
	238	* SCT: no
	239	*/
	240	#define HW_GPMI_STAT ((volatile unsigned long )(REGS_GPMI_BASE + 0x70))
	241	#define BP_GPMI_STAT_PRESENT 31
	242	#define BM_GPMI_STAT_PRESENT 0x80000000
	243	#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0
	244	#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1
	245	#define BF_GPMI_STAT_PRESENT(v) (((v) << 31) & 0x80000000)
	246	#define BF_GPMI_STAT_PRESENT_V(v) ((BV_GPMI_STAT_PRESENT__##v << 31) & 0x80000000)
	247	#define BP_GPMI_STAT_RDY_TIMEOUT 8
	248	#define BM_GPMI_STAT_RDY_TIMEOUT 0xf00
	249	#define BF_GPMI_STAT_RDY_TIMEOUT(v) (((v) << 8) & 0xf00)
	250	#define BP_GPMI_STAT_ATA_IRQ 7
	251	#define BM_GPMI_STAT_ATA_IRQ 0x80
	252	#define BF_GPMI_STAT_ATA_IRQ(v) (((v) << 7) & 0x80)
	253	#define BP_GPMI_STAT_FIFO_EMPTY 5
	254	#define BM_GPMI_STAT_FIFO_EMPTY 0x20
	255	#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0
	256	#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1
	257	#define BF_GPMI_STAT_FIFO_EMPTY(v) (((v) << 5) & 0x20)
	258	#define BF_GPMI_STAT_FIFO_EMPTY_V(v) ((BV_GPMI_STAT_FIFO_EMPTY__##v << 5) & 0x20)
	259	#define BP_GPMI_STAT_FIFO_FULL 4
	260	#define BM_GPMI_STAT_FIFO_FULL 0x10
	261	#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0
	262	#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1
	263	#define BF_GPMI_STAT_FIFO_FULL(v) (((v) << 4) & 0x10)
	264	#define BF_GPMI_STAT_FIFO_FULL_V(v) ((BV_GPMI_STAT_FIFO_FULL__##v << 4) & 0x10)
	265	#define BP_GPMI_STAT_DEV3_ERROR 3
	266	#define BM_GPMI_STAT_DEV3_ERROR 0x8
	267	#define BF_GPMI_STAT_DEV3_ERROR(v) (((v) << 3) & 0x8)
	268	#define BP_GPMI_STAT_DEV2_ERROR 2
	269	#define BM_GPMI_STAT_DEV2_ERROR 0x4
	270	#define BF_GPMI_STAT_DEV2_ERROR(v) (((v) << 2) & 0x4)
	271	#define BP_GPMI_STAT_DEV1_ERROR 1
	272	#define BM_GPMI_STAT_DEV1_ERROR 0x2
	273	#define BF_GPMI_STAT_DEV1_ERROR(v) (((v) << 1) & 0x2)
	274	#define BP_GPMI_STAT_DEV0_ERROR 0
	275	#define BM_GPMI_STAT_DEV0_ERROR 0x1
	276	#define BF_GPMI_STAT_DEV0_ERROR(v) (((v) << 0) & 0x1)
	277
	278	/**
	279	* Register: HW_GPMI_DEBUG
	280	* Address: 0x80
	281	* SCT: no
	282	*/
	283	#define HW_GPMI_DEBUG ((volatile unsigned long )(REGS_GPMI_BASE + 0x80))
	284	#define BP_GPMI_DEBUG_READY3 31
	285	#define BM_GPMI_DEBUG_READY3 0x80000000
	286	#define BF_GPMI_DEBUG_READY3(v) (((v) << 31) & 0x80000000)
	287	#define BP_GPMI_DEBUG_READY2 30
	288	#define BM_GPMI_DEBUG_READY2 0x40000000
	289	#define BF_GPMI_DEBUG_READY2(v) (((v) << 30) & 0x40000000)
	290	#define BP_GPMI_DEBUG_READY1 29
	291	#define BM_GPMI_DEBUG_READY1 0x20000000
	292	#define BF_GPMI_DEBUG_READY1(v) (((v) << 29) & 0x20000000)
	293	#define BP_GPMI_DEBUG_READY0 28
	294	#define BM_GPMI_DEBUG_READY0 0x10000000
	295	#define BF_GPMI_DEBUG_READY0(v) (((v) << 28) & 0x10000000)
	296	#define BP_GPMI_DEBUG_WAIT_FOR_READY_END3 27
	297	#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 0x8000000
	298	#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v) (((v) << 27) & 0x8000000)
	299	#define BP_GPMI_DEBUG_WAIT_FOR_READY_END2 26
	300	#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 0x4000000
	301	#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v) (((v) << 26) & 0x4000000)
	302	#define BP_GPMI_DEBUG_WAIT_FOR_READY_END1 25
	303	#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 0x2000000
	304	#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v) (((v) << 25) & 0x2000000)
	305	#define BP_GPMI_DEBUG_WAIT_FOR_READY_END0 24
	306	#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 0x1000000
	307	#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v) (((v) << 24) & 0x1000000)
	308	#define BP_GPMI_DEBUG_SENSE3 23
	309	#define BM_GPMI_DEBUG_SENSE3 0x800000
	310	#define BF_GPMI_DEBUG_SENSE3(v) (((v) << 23) & 0x800000)
	311	#define BP_GPMI_DEBUG_SENSE2 22
	312	#define BM_GPMI_DEBUG_SENSE2 0x400000
	313	#define BF_GPMI_DEBUG_SENSE2(v) (((v) << 22) & 0x400000)
	314	#define BP_GPMI_DEBUG_SENSE1 21
	315	#define BM_GPMI_DEBUG_SENSE1 0x200000
	316	#define BF_GPMI_DEBUG_SENSE1(v) (((v) << 21) & 0x200000)
	317	#define BP_GPMI_DEBUG_SENSE0 20
	318	#define BM_GPMI_DEBUG_SENSE0 0x100000
	319	#define BF_GPMI_DEBUG_SENSE0(v) (((v) << 20) & 0x100000)
	320	#define BP_GPMI_DEBUG_DMAREQ3 19
	321	#define BM_GPMI_DEBUG_DMAREQ3 0x80000
	322	#define BF_GPMI_DEBUG_DMAREQ3(v) (((v) << 19) & 0x80000)
	323	#define BP_GPMI_DEBUG_DMAREQ2 18
	324	#define BM_GPMI_DEBUG_DMAREQ2 0x40000
	325	#define BF_GPMI_DEBUG_DMAREQ2(v) (((v) << 18) & 0x40000)
	326	#define BP_GPMI_DEBUG_DMAREQ1 17
	327	#define BM_GPMI_DEBUG_DMAREQ1 0x20000
	328	#define BF_GPMI_DEBUG_DMAREQ1(v) (((v) << 17) & 0x20000)
	329	#define BP_GPMI_DEBUG_DMAREQ0 16
	330	#define BM_GPMI_DEBUG_DMAREQ0 0x10000
	331	#define BF_GPMI_DEBUG_DMAREQ0(v) (((v) << 16) & 0x10000)
	332	#define BP_GPMI_DEBUG_CMD_END 12
	333	#define BM_GPMI_DEBUG_CMD_END 0xf000
	334	#define BF_GPMI_DEBUG_CMD_END(v) (((v) << 12) & 0xf000)
	335	#define BP_GPMI_DEBUG_UDMA_STATE 8
	336	#define BM_GPMI_DEBUG_UDMA_STATE 0xf00
	337	#define BF_GPMI_DEBUG_UDMA_STATE(v) (((v) << 8) & 0xf00)
	338	#define BP_GPMI_DEBUG_BUSY 7
	339	#define BM_GPMI_DEBUG_BUSY 0x80
	340	#define BV_GPMI_DEBUG_BUSY__DISABLED 0x0
	341	#define BV_GPMI_DEBUG_BUSY__ENABLED 0x1
	342	#define BF_GPMI_DEBUG_BUSY(v) (((v) << 7) & 0x80)
	343	#define BF_GPMI_DEBUG_BUSY_V(v) ((BV_GPMI_DEBUG_BUSY__##v << 7) & 0x80)
	344	#define BP_GPMI_DEBUG_PIN_STATE 4
	345	#define BM_GPMI_DEBUG_PIN_STATE 0x70
	346	#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0
	347	#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1
	348	#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2
	349	#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3
	350	#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4
	351	#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5
	352	#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6
	353	#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7
	354	#define BF_GPMI_DEBUG_PIN_STATE(v) (((v) << 4) & 0x70)
	355	#define BF_GPMI_DEBUG_PIN_STATE_V(v) ((BV_GPMI_DEBUG_PIN_STATE__##v << 4) & 0x70)
	356	#define BP_GPMI_DEBUG_MAIN_STATE 0
	357	#define BM_GPMI_DEBUG_MAIN_STATE 0xf
	358	#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0
	359	#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1
	360	#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2
	361	#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3
	362	#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4
	363	#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5
	364	#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6
	365	#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7
	366	#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8
	367	#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9
	368	#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xa
	369	#define BF_GPMI_DEBUG_MAIN_STATE(v) (((v) << 0) & 0xf)
	370	#define BF_GPMI_DEBUG_MAIN_STATE_V(v) ((BV_GPMI_DEBUG_MAIN_STATE__##v << 0) & 0xf)
	371
	372	#endif /* __HEADERGEN__STMP3600__GPMI__H__ */