diff options
Diffstat (limited to 'firmware/target/arm/imx233/regs/imx233/regs-tvenc.h')
| -rw-r--r-- | firmware/target/arm/imx233/regs/imx233/regs-tvenc.h | 776 |
1 files changed, 776 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-tvenc.h b/firmware/target/arm/imx233/regs/imx233/regs-tvenc.h new file mode 100644 index 0000000000..c587f5f7fa --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-tvenc.h | |||
| @@ -0,0 +1,776 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: imx233:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__IMX233__TVENC__H__ | ||
| 24 | #define __HEADERGEN__IMX233__TVENC__H__ | ||
| 25 | |||
| 26 | #define REGS_TVENC_BASE (0x80038000) | ||
| 27 | |||
| 28 | #define REGS_TVENC_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_TVENC_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_TVENC_CTRL (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_TVENC_CTRL_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_TVENC_CTRL_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_TVENC_CTRL_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_TVENC_CTRL_SFTRST 31 | ||
| 40 | #define BM_TVENC_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_TVENC_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_TVENC_CTRL_CLKGATE 30 | ||
| 43 | #define BM_TVENC_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_TVENC_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_TVENC_CTRL_TVENC_MACROVISION_PRESENT 29 | ||
| 46 | #define BM_TVENC_CTRL_TVENC_MACROVISION_PRESENT 0x20000000 | ||
| 47 | #define BF_TVENC_CTRL_TVENC_MACROVISION_PRESENT(v) (((v) << 29) & 0x20000000) | ||
| 48 | #define BP_TVENC_CTRL_TVENC_COMPOSITE_PRESENT 28 | ||
| 49 | #define BM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT 0x10000000 | ||
| 50 | #define BF_TVENC_CTRL_TVENC_COMPOSITE_PRESENT(v) (((v) << 28) & 0x10000000) | ||
| 51 | #define BP_TVENC_CTRL_TVENC_SVIDEO_PRESENT 27 | ||
| 52 | #define BM_TVENC_CTRL_TVENC_SVIDEO_PRESENT 0x8000000 | ||
| 53 | #define BF_TVENC_CTRL_TVENC_SVIDEO_PRESENT(v) (((v) << 27) & 0x8000000) | ||
| 54 | #define BP_TVENC_CTRL_TVENC_COMPONENT_PRESENT 26 | ||
| 55 | #define BM_TVENC_CTRL_TVENC_COMPONENT_PRESENT 0x4000000 | ||
| 56 | #define BF_TVENC_CTRL_TVENC_COMPONENT_PRESENT(v) (((v) << 26) & 0x4000000) | ||
| 57 | #define BP_TVENC_CTRL_RSRVD1 6 | ||
| 58 | #define BM_TVENC_CTRL_RSRVD1 0x3ffffc0 | ||
| 59 | #define BF_TVENC_CTRL_RSRVD1(v) (((v) << 6) & 0x3ffffc0) | ||
| 60 | #define BP_TVENC_CTRL_DAC_FIFO_NO_WRITE 5 | ||
| 61 | #define BM_TVENC_CTRL_DAC_FIFO_NO_WRITE 0x20 | ||
| 62 | #define BF_TVENC_CTRL_DAC_FIFO_NO_WRITE(v) (((v) << 5) & 0x20) | ||
| 63 | #define BP_TVENC_CTRL_DAC_FIFO_NO_READ 4 | ||
| 64 | #define BM_TVENC_CTRL_DAC_FIFO_NO_READ 0x10 | ||
| 65 | #define BF_TVENC_CTRL_DAC_FIFO_NO_READ(v) (((v) << 4) & 0x10) | ||
| 66 | #define BP_TVENC_CTRL_DAC_DATA_FIFO_RST 3 | ||
| 67 | #define BM_TVENC_CTRL_DAC_DATA_FIFO_RST 0x8 | ||
| 68 | #define BF_TVENC_CTRL_DAC_DATA_FIFO_RST(v) (((v) << 3) & 0x8) | ||
| 69 | #define BP_TVENC_CTRL_RSRVD2 1 | ||
| 70 | #define BM_TVENC_CTRL_RSRVD2 0x6 | ||
| 71 | #define BF_TVENC_CTRL_RSRVD2(v) (((v) << 1) & 0x6) | ||
| 72 | #define BP_TVENC_CTRL_DAC_MUX_MODE 0 | ||
| 73 | #define BM_TVENC_CTRL_DAC_MUX_MODE 0x1 | ||
| 74 | #define BF_TVENC_CTRL_DAC_MUX_MODE(v) (((v) << 0) & 0x1) | ||
| 75 | |||
| 76 | /** | ||
| 77 | * Register: HW_TVENC_CONFIG | ||
| 78 | * Address: 0x10 | ||
| 79 | * SCT: yes | ||
| 80 | */ | ||
| 81 | #define HW_TVENC_CONFIG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0x0)) | ||
| 82 | #define HW_TVENC_CONFIG_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0x4)) | ||
| 83 | #define HW_TVENC_CONFIG_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0x8)) | ||
| 84 | #define HW_TVENC_CONFIG_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0xc)) | ||
| 85 | #define BP_TVENC_CONFIG_RSRVD5 28 | ||
| 86 | #define BM_TVENC_CONFIG_RSRVD5 0xf0000000 | ||
| 87 | #define BF_TVENC_CONFIG_RSRVD5(v) (((v) << 28) & 0xf0000000) | ||
| 88 | #define BP_TVENC_CONFIG_DEFAULT_PICFORM 27 | ||
| 89 | #define BM_TVENC_CONFIG_DEFAULT_PICFORM 0x8000000 | ||
| 90 | #define BF_TVENC_CONFIG_DEFAULT_PICFORM(v) (((v) << 27) & 0x8000000) | ||
| 91 | #define BP_TVENC_CONFIG_YDEL_ADJ 24 | ||
| 92 | #define BM_TVENC_CONFIG_YDEL_ADJ 0x7000000 | ||
| 93 | #define BF_TVENC_CONFIG_YDEL_ADJ(v) (((v) << 24) & 0x7000000) | ||
| 94 | #define BP_TVENC_CONFIG_RSRVD4 23 | ||
| 95 | #define BM_TVENC_CONFIG_RSRVD4 0x800000 | ||
| 96 | #define BF_TVENC_CONFIG_RSRVD4(v) (((v) << 23) & 0x800000) | ||
| 97 | #define BP_TVENC_CONFIG_RSRVD3 22 | ||
| 98 | #define BM_TVENC_CONFIG_RSRVD3 0x400000 | ||
| 99 | #define BF_TVENC_CONFIG_RSRVD3(v) (((v) << 22) & 0x400000) | ||
| 100 | #define BP_TVENC_CONFIG_ADD_YPBPR_PED 21 | ||
| 101 | #define BM_TVENC_CONFIG_ADD_YPBPR_PED 0x200000 | ||
| 102 | #define BF_TVENC_CONFIG_ADD_YPBPR_PED(v) (((v) << 21) & 0x200000) | ||
| 103 | #define BP_TVENC_CONFIG_PAL_SHAPE 20 | ||
| 104 | #define BM_TVENC_CONFIG_PAL_SHAPE 0x100000 | ||
| 105 | #define BF_TVENC_CONFIG_PAL_SHAPE(v) (((v) << 20) & 0x100000) | ||
| 106 | #define BP_TVENC_CONFIG_NO_PED 19 | ||
| 107 | #define BM_TVENC_CONFIG_NO_PED 0x80000 | ||
| 108 | #define BF_TVENC_CONFIG_NO_PED(v) (((v) << 19) & 0x80000) | ||
| 109 | #define BP_TVENC_CONFIG_COLOR_BAR_EN 18 | ||
| 110 | #define BM_TVENC_CONFIG_COLOR_BAR_EN 0x40000 | ||
| 111 | #define BF_TVENC_CONFIG_COLOR_BAR_EN(v) (((v) << 18) & 0x40000) | ||
| 112 | #define BP_TVENC_CONFIG_YGAIN_SEL 16 | ||
| 113 | #define BM_TVENC_CONFIG_YGAIN_SEL 0x30000 | ||
| 114 | #define BF_TVENC_CONFIG_YGAIN_SEL(v) (((v) << 16) & 0x30000) | ||
| 115 | #define BP_TVENC_CONFIG_CGAIN 14 | ||
| 116 | #define BM_TVENC_CONFIG_CGAIN 0xc000 | ||
| 117 | #define BF_TVENC_CONFIG_CGAIN(v) (((v) << 14) & 0xc000) | ||
| 118 | #define BP_TVENC_CONFIG_CLK_PHS 12 | ||
| 119 | #define BM_TVENC_CONFIG_CLK_PHS 0x3000 | ||
| 120 | #define BF_TVENC_CONFIG_CLK_PHS(v) (((v) << 12) & 0x3000) | ||
| 121 | #define BP_TVENC_CONFIG_RSRVD2 11 | ||
| 122 | #define BM_TVENC_CONFIG_RSRVD2 0x800 | ||
| 123 | #define BF_TVENC_CONFIG_RSRVD2(v) (((v) << 11) & 0x800) | ||
| 124 | #define BP_TVENC_CONFIG_FSYNC_ENBL 10 | ||
| 125 | #define BM_TVENC_CONFIG_FSYNC_ENBL 0x400 | ||
| 126 | #define BF_TVENC_CONFIG_FSYNC_ENBL(v) (((v) << 10) & 0x400) | ||
| 127 | #define BP_TVENC_CONFIG_FSYNC_PHS 9 | ||
| 128 | #define BM_TVENC_CONFIG_FSYNC_PHS 0x200 | ||
| 129 | #define BF_TVENC_CONFIG_FSYNC_PHS(v) (((v) << 9) & 0x200) | ||
| 130 | #define BP_TVENC_CONFIG_HSYNC_PHS 8 | ||
| 131 | #define BM_TVENC_CONFIG_HSYNC_PHS 0x100 | ||
| 132 | #define BF_TVENC_CONFIG_HSYNC_PHS(v) (((v) << 8) & 0x100) | ||
| 133 | #define BP_TVENC_CONFIG_VSYNC_PHS 7 | ||
| 134 | #define BM_TVENC_CONFIG_VSYNC_PHS 0x80 | ||
| 135 | #define BF_TVENC_CONFIG_VSYNC_PHS(v) (((v) << 7) & 0x80) | ||
| 136 | #define BP_TVENC_CONFIG_SYNC_MODE 4 | ||
| 137 | #define BM_TVENC_CONFIG_SYNC_MODE 0x70 | ||
| 138 | #define BF_TVENC_CONFIG_SYNC_MODE(v) (((v) << 4) & 0x70) | ||
| 139 | #define BP_TVENC_CONFIG_RSRVD1 3 | ||
| 140 | #define BM_TVENC_CONFIG_RSRVD1 0x8 | ||
| 141 | #define BF_TVENC_CONFIG_RSRVD1(v) (((v) << 3) & 0x8) | ||
| 142 | #define BP_TVENC_CONFIG_ENCD_MODE 0 | ||
| 143 | #define BM_TVENC_CONFIG_ENCD_MODE 0x7 | ||
| 144 | #define BF_TVENC_CONFIG_ENCD_MODE(v) (((v) << 0) & 0x7) | ||
| 145 | |||
| 146 | /** | ||
| 147 | * Register: HW_TVENC_FILTCTRL | ||
| 148 | * Address: 0x20 | ||
| 149 | * SCT: yes | ||
| 150 | */ | ||
| 151 | #define HW_TVENC_FILTCTRL (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0x0)) | ||
| 152 | #define HW_TVENC_FILTCTRL_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0x4)) | ||
| 153 | #define HW_TVENC_FILTCTRL_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0x8)) | ||
| 154 | #define HW_TVENC_FILTCTRL_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0xc)) | ||
| 155 | #define BP_TVENC_FILTCTRL_RSRVD1 20 | ||
| 156 | #define BM_TVENC_FILTCTRL_RSRVD1 0xfff00000 | ||
| 157 | #define BF_TVENC_FILTCTRL_RSRVD1(v) (((v) << 20) & 0xfff00000) | ||
| 158 | #define BP_TVENC_FILTCTRL_YSHARP_BW 19 | ||
| 159 | #define BM_TVENC_FILTCTRL_YSHARP_BW 0x80000 | ||
| 160 | #define BF_TVENC_FILTCTRL_YSHARP_BW(v) (((v) << 19) & 0x80000) | ||
| 161 | #define BP_TVENC_FILTCTRL_YD_OFFSETSEL 18 | ||
| 162 | #define BM_TVENC_FILTCTRL_YD_OFFSETSEL 0x40000 | ||
| 163 | #define BF_TVENC_FILTCTRL_YD_OFFSETSEL(v) (((v) << 18) & 0x40000) | ||
| 164 | #define BP_TVENC_FILTCTRL_SEL_YLPF 17 | ||
| 165 | #define BM_TVENC_FILTCTRL_SEL_YLPF 0x20000 | ||
| 166 | #define BF_TVENC_FILTCTRL_SEL_YLPF(v) (((v) << 17) & 0x20000) | ||
| 167 | #define BP_TVENC_FILTCTRL_SEL_CLPF 16 | ||
| 168 | #define BM_TVENC_FILTCTRL_SEL_CLPF 0x10000 | ||
| 169 | #define BF_TVENC_FILTCTRL_SEL_CLPF(v) (((v) << 16) & 0x10000) | ||
| 170 | #define BP_TVENC_FILTCTRL_SEL_YSHARP 15 | ||
| 171 | #define BM_TVENC_FILTCTRL_SEL_YSHARP 0x8000 | ||
| 172 | #define BF_TVENC_FILTCTRL_SEL_YSHARP(v) (((v) << 15) & 0x8000) | ||
| 173 | #define BP_TVENC_FILTCTRL_YLPF_COEFSEL 14 | ||
| 174 | #define BM_TVENC_FILTCTRL_YLPF_COEFSEL 0x4000 | ||
| 175 | #define BF_TVENC_FILTCTRL_YLPF_COEFSEL(v) (((v) << 14) & 0x4000) | ||
| 176 | #define BP_TVENC_FILTCTRL_COEFSEL_CLPF 13 | ||
| 177 | #define BM_TVENC_FILTCTRL_COEFSEL_CLPF 0x2000 | ||
| 178 | #define BF_TVENC_FILTCTRL_COEFSEL_CLPF(v) (((v) << 13) & 0x2000) | ||
| 179 | #define BP_TVENC_FILTCTRL_YS_GAINSGN 12 | ||
| 180 | #define BM_TVENC_FILTCTRL_YS_GAINSGN 0x1000 | ||
| 181 | #define BF_TVENC_FILTCTRL_YS_GAINSGN(v) (((v) << 12) & 0x1000) | ||
| 182 | #define BP_TVENC_FILTCTRL_YS_GAINSEL 10 | ||
| 183 | #define BM_TVENC_FILTCTRL_YS_GAINSEL 0xc00 | ||
| 184 | #define BF_TVENC_FILTCTRL_YS_GAINSEL(v) (((v) << 10) & 0xc00) | ||
| 185 | #define BP_TVENC_FILTCTRL_RSRVD2 9 | ||
| 186 | #define BM_TVENC_FILTCTRL_RSRVD2 0x200 | ||
| 187 | #define BF_TVENC_FILTCTRL_RSRVD2(v) (((v) << 9) & 0x200) | ||
| 188 | #define BP_TVENC_FILTCTRL_RSRVD3 8 | ||
| 189 | #define BM_TVENC_FILTCTRL_RSRVD3 0x100 | ||
| 190 | #define BF_TVENC_FILTCTRL_RSRVD3(v) (((v) << 8) & 0x100) | ||
| 191 | #define BP_TVENC_FILTCTRL_RSRVD4 0 | ||
| 192 | #define BM_TVENC_FILTCTRL_RSRVD4 0xff | ||
| 193 | #define BF_TVENC_FILTCTRL_RSRVD4(v) (((v) << 0) & 0xff) | ||
| 194 | |||
| 195 | /** | ||
| 196 | * Register: HW_TVENC_SYNCOFFSET | ||
| 197 | * Address: 0x30 | ||
| 198 | * SCT: yes | ||
| 199 | */ | ||
| 200 | #define HW_TVENC_SYNCOFFSET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0x0)) | ||
| 201 | #define HW_TVENC_SYNCOFFSET_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0x4)) | ||
| 202 | #define HW_TVENC_SYNCOFFSET_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0x8)) | ||
| 203 | #define HW_TVENC_SYNCOFFSET_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0xc)) | ||
| 204 | #define BP_TVENC_SYNCOFFSET_RSRVD1 31 | ||
| 205 | #define BM_TVENC_SYNCOFFSET_RSRVD1 0x80000000 | ||
| 206 | #define BF_TVENC_SYNCOFFSET_RSRVD1(v) (((v) << 31) & 0x80000000) | ||
| 207 | #define BP_TVENC_SYNCOFFSET_HSO 20 | ||
| 208 | #define BM_TVENC_SYNCOFFSET_HSO 0x7ff00000 | ||
| 209 | #define BF_TVENC_SYNCOFFSET_HSO(v) (((v) << 20) & 0x7ff00000) | ||
| 210 | #define BP_TVENC_SYNCOFFSET_VSO 10 | ||
| 211 | #define BM_TVENC_SYNCOFFSET_VSO 0xffc00 | ||
| 212 | #define BF_TVENC_SYNCOFFSET_VSO(v) (((v) << 10) & 0xffc00) | ||
| 213 | #define BP_TVENC_SYNCOFFSET_HLC 0 | ||
| 214 | #define BM_TVENC_SYNCOFFSET_HLC 0x3ff | ||
| 215 | #define BF_TVENC_SYNCOFFSET_HLC(v) (((v) << 0) & 0x3ff) | ||
| 216 | |||
| 217 | /** | ||
| 218 | * Register: HW_TVENC_HTIMINGSYNC0 | ||
| 219 | * Address: 0x40 | ||
| 220 | * SCT: yes | ||
| 221 | */ | ||
| 222 | #define HW_TVENC_HTIMINGSYNC0 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0x0)) | ||
| 223 | #define HW_TVENC_HTIMINGSYNC0_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0x4)) | ||
| 224 | #define HW_TVENC_HTIMINGSYNC0_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0x8)) | ||
| 225 | #define HW_TVENC_HTIMINGSYNC0_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0xc)) | ||
| 226 | #define BP_TVENC_HTIMINGSYNC0_RSRVD2 26 | ||
| 227 | #define BM_TVENC_HTIMINGSYNC0_RSRVD2 0xfc000000 | ||
| 228 | #define BF_TVENC_HTIMINGSYNC0_RSRVD2(v) (((v) << 26) & 0xfc000000) | ||
| 229 | #define BP_TVENC_HTIMINGSYNC0_SYNC_END 16 | ||
| 230 | #define BM_TVENC_HTIMINGSYNC0_SYNC_END 0x3ff0000 | ||
| 231 | #define BF_TVENC_HTIMINGSYNC0_SYNC_END(v) (((v) << 16) & 0x3ff0000) | ||
| 232 | #define BP_TVENC_HTIMINGSYNC0_RSRVD1 10 | ||
| 233 | #define BM_TVENC_HTIMINGSYNC0_RSRVD1 0xfc00 | ||
| 234 | #define BF_TVENC_HTIMINGSYNC0_RSRVD1(v) (((v) << 10) & 0xfc00) | ||
| 235 | #define BP_TVENC_HTIMINGSYNC0_SYNC_STRT 0 | ||
| 236 | #define BM_TVENC_HTIMINGSYNC0_SYNC_STRT 0x3ff | ||
| 237 | #define BF_TVENC_HTIMINGSYNC0_SYNC_STRT(v) (((v) << 0) & 0x3ff) | ||
| 238 | |||
| 239 | /** | ||
| 240 | * Register: HW_TVENC_HTIMINGSYNC1 | ||
| 241 | * Address: 0x50 | ||
| 242 | * SCT: yes | ||
| 243 | */ | ||
| 244 | #define HW_TVENC_HTIMINGSYNC1 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0x0)) | ||
| 245 | #define HW_TVENC_HTIMINGSYNC1_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0x4)) | ||
| 246 | #define HW_TVENC_HTIMINGSYNC1_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0x8)) | ||
| 247 | #define HW_TVENC_HTIMINGSYNC1_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0xc)) | ||
| 248 | #define BP_TVENC_HTIMINGSYNC1_RSRVD2 26 | ||
| 249 | #define BM_TVENC_HTIMINGSYNC1_RSRVD2 0xfc000000 | ||
| 250 | #define BF_TVENC_HTIMINGSYNC1_RSRVD2(v) (((v) << 26) & 0xfc000000) | ||
| 251 | #define BP_TVENC_HTIMINGSYNC1_SYNC_EQEND 16 | ||
| 252 | #define BM_TVENC_HTIMINGSYNC1_SYNC_EQEND 0x3ff0000 | ||
| 253 | #define BF_TVENC_HTIMINGSYNC1_SYNC_EQEND(v) (((v) << 16) & 0x3ff0000) | ||
| 254 | #define BP_TVENC_HTIMINGSYNC1_RSRVD1 10 | ||
| 255 | #define BM_TVENC_HTIMINGSYNC1_RSRVD1 0xfc00 | ||
| 256 | #define BF_TVENC_HTIMINGSYNC1_RSRVD1(v) (((v) << 10) & 0xfc00) | ||
| 257 | #define BP_TVENC_HTIMINGSYNC1_SYNC_SREND 0 | ||
| 258 | #define BM_TVENC_HTIMINGSYNC1_SYNC_SREND 0x3ff | ||
| 259 | #define BF_TVENC_HTIMINGSYNC1_SYNC_SREND(v) (((v) << 0) & 0x3ff) | ||
| 260 | |||
| 261 | /** | ||
| 262 | * Register: HW_TVENC_HTIMINGACTIVE | ||
| 263 | * Address: 0x60 | ||
| 264 | * SCT: yes | ||
| 265 | */ | ||
| 266 | #define HW_TVENC_HTIMINGACTIVE (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0x0)) | ||
| 267 | #define HW_TVENC_HTIMINGACTIVE_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0x4)) | ||
| 268 | #define HW_TVENC_HTIMINGACTIVE_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0x8)) | ||
| 269 | #define HW_TVENC_HTIMINGACTIVE_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0xc)) | ||
| 270 | #define BP_TVENC_HTIMINGACTIVE_RSRVD2 26 | ||
| 271 | #define BM_TVENC_HTIMINGACTIVE_RSRVD2 0xfc000000 | ||
| 272 | #define BF_TVENC_HTIMINGACTIVE_RSRVD2(v) (((v) << 26) & 0xfc000000) | ||
| 273 | #define BP_TVENC_HTIMINGACTIVE_ACTV_END 16 | ||
| 274 | #define BM_TVENC_HTIMINGACTIVE_ACTV_END 0x3ff0000 | ||
| 275 | #define BF_TVENC_HTIMINGACTIVE_ACTV_END(v) (((v) << 16) & 0x3ff0000) | ||
| 276 | #define BP_TVENC_HTIMINGACTIVE_RSRVD1 10 | ||
| 277 | #define BM_TVENC_HTIMINGACTIVE_RSRVD1 0xfc00 | ||
| 278 | #define BF_TVENC_HTIMINGACTIVE_RSRVD1(v) (((v) << 10) & 0xfc00) | ||
| 279 | #define BP_TVENC_HTIMINGACTIVE_ACTV_STRT 0 | ||
| 280 | #define BM_TVENC_HTIMINGACTIVE_ACTV_STRT 0x3ff | ||
| 281 | #define BF_TVENC_HTIMINGACTIVE_ACTV_STRT(v) (((v) << 0) & 0x3ff) | ||
| 282 | |||
| 283 | /** | ||
| 284 | * Register: HW_TVENC_HTIMINGBURST0 | ||
| 285 | * Address: 0x70 | ||
| 286 | * SCT: yes | ||
| 287 | */ | ||
| 288 | #define HW_TVENC_HTIMINGBURST0 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0x0)) | ||
| 289 | #define HW_TVENC_HTIMINGBURST0_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0x4)) | ||
| 290 | #define HW_TVENC_HTIMINGBURST0_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0x8)) | ||
| 291 | #define HW_TVENC_HTIMINGBURST0_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0xc)) | ||
| 292 | #define BP_TVENC_HTIMINGBURST0_RSRVD2 26 | ||
| 293 | #define BM_TVENC_HTIMINGBURST0_RSRVD2 0xfc000000 | ||
| 294 | #define BF_TVENC_HTIMINGBURST0_RSRVD2(v) (((v) << 26) & 0xfc000000) | ||
| 295 | #define BP_TVENC_HTIMINGBURST0_WBRST_STRT 16 | ||
| 296 | #define BM_TVENC_HTIMINGBURST0_WBRST_STRT 0x3ff0000 | ||
| 297 | #define BF_TVENC_HTIMINGBURST0_WBRST_STRT(v) (((v) << 16) & 0x3ff0000) | ||
| 298 | #define BP_TVENC_HTIMINGBURST0_RSRVD1 10 | ||
| 299 | #define BM_TVENC_HTIMINGBURST0_RSRVD1 0xfc00 | ||
| 300 | #define BF_TVENC_HTIMINGBURST0_RSRVD1(v) (((v) << 10) & 0xfc00) | ||
| 301 | #define BP_TVENC_HTIMINGBURST0_NBRST_STRT 0 | ||
| 302 | #define BM_TVENC_HTIMINGBURST0_NBRST_STRT 0x3ff | ||
| 303 | #define BF_TVENC_HTIMINGBURST0_NBRST_STRT(v) (((v) << 0) & 0x3ff) | ||
| 304 | |||
| 305 | /** | ||
| 306 | * Register: HW_TVENC_HTIMINGBURST1 | ||
| 307 | * Address: 0x80 | ||
| 308 | * SCT: yes | ||
| 309 | */ | ||
| 310 | #define HW_TVENC_HTIMINGBURST1 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0x0)) | ||
| 311 | #define HW_TVENC_HTIMINGBURST1_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0x4)) | ||
| 312 | #define HW_TVENC_HTIMINGBURST1_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0x8)) | ||
| 313 | #define HW_TVENC_HTIMINGBURST1_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0xc)) | ||
| 314 | #define BP_TVENC_HTIMINGBURST1_RSRVD1 10 | ||
| 315 | #define BM_TVENC_HTIMINGBURST1_RSRVD1 0xfffffc00 | ||
| 316 | #define BF_TVENC_HTIMINGBURST1_RSRVD1(v) (((v) << 10) & 0xfffffc00) | ||
| 317 | #define BP_TVENC_HTIMINGBURST1_BRST_END 0 | ||
| 318 | #define BM_TVENC_HTIMINGBURST1_BRST_END 0x3ff | ||
| 319 | #define BF_TVENC_HTIMINGBURST1_BRST_END(v) (((v) << 0) & 0x3ff) | ||
| 320 | |||
| 321 | /** | ||
| 322 | * Register: HW_TVENC_VTIMING0 | ||
| 323 | * Address: 0x90 | ||
| 324 | * SCT: yes | ||
| 325 | */ | ||
| 326 | #define HW_TVENC_VTIMING0 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0x0)) | ||
| 327 | #define HW_TVENC_VTIMING0_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0x4)) | ||
| 328 | #define HW_TVENC_VTIMING0_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0x8)) | ||
| 329 | #define HW_TVENC_VTIMING0_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0xc)) | ||
| 330 | #define BP_TVENC_VTIMING0_RSRVD3 26 | ||
| 331 | #define BM_TVENC_VTIMING0_RSRVD3 0xfc000000 | ||
| 332 | #define BF_TVENC_VTIMING0_RSRVD3(v) (((v) << 26) & 0xfc000000) | ||
| 333 | #define BP_TVENC_VTIMING0_VSTRT_PREEQ 16 | ||
| 334 | #define BM_TVENC_VTIMING0_VSTRT_PREEQ 0x3ff0000 | ||
| 335 | #define BF_TVENC_VTIMING0_VSTRT_PREEQ(v) (((v) << 16) & 0x3ff0000) | ||
| 336 | #define BP_TVENC_VTIMING0_RSRVD2 14 | ||
| 337 | #define BM_TVENC_VTIMING0_RSRVD2 0xc000 | ||
| 338 | #define BF_TVENC_VTIMING0_RSRVD2(v) (((v) << 14) & 0xc000) | ||
| 339 | #define BP_TVENC_VTIMING0_VSTRT_ACTV 8 | ||
| 340 | #define BM_TVENC_VTIMING0_VSTRT_ACTV 0x3f00 | ||
| 341 | #define BF_TVENC_VTIMING0_VSTRT_ACTV(v) (((v) << 8) & 0x3f00) | ||
| 342 | #define BP_TVENC_VTIMING0_RSRVD1 6 | ||
| 343 | #define BM_TVENC_VTIMING0_RSRVD1 0xc0 | ||
| 344 | #define BF_TVENC_VTIMING0_RSRVD1(v) (((v) << 6) & 0xc0) | ||
| 345 | #define BP_TVENC_VTIMING0_VSTRT_SUBPH 0 | ||
| 346 | #define BM_TVENC_VTIMING0_VSTRT_SUBPH 0x3f | ||
| 347 | #define BF_TVENC_VTIMING0_VSTRT_SUBPH(v) (((v) << 0) & 0x3f) | ||
| 348 | |||
| 349 | /** | ||
| 350 | * Register: HW_TVENC_VTIMING1 | ||
| 351 | * Address: 0xa0 | ||
| 352 | * SCT: yes | ||
| 353 | */ | ||
| 354 | #define HW_TVENC_VTIMING1 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0x0)) | ||
| 355 | #define HW_TVENC_VTIMING1_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0x4)) | ||
| 356 | #define HW_TVENC_VTIMING1_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0x8)) | ||
| 357 | #define HW_TVENC_VTIMING1_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0xc)) | ||
| 358 | #define BP_TVENC_VTIMING1_RSRVD3 30 | ||
| 359 | #define BM_TVENC_VTIMING1_RSRVD3 0xc0000000 | ||
| 360 | #define BF_TVENC_VTIMING1_RSRVD3(v) (((v) << 30) & 0xc0000000) | ||
| 361 | #define BP_TVENC_VTIMING1_VSTRT_POSTEQ 24 | ||
| 362 | #define BM_TVENC_VTIMING1_VSTRT_POSTEQ 0x3f000000 | ||
| 363 | #define BF_TVENC_VTIMING1_VSTRT_POSTEQ(v) (((v) << 24) & 0x3f000000) | ||
| 364 | #define BP_TVENC_VTIMING1_RSRVD2 22 | ||
| 365 | #define BM_TVENC_VTIMING1_RSRVD2 0xc00000 | ||
| 366 | #define BF_TVENC_VTIMING1_RSRVD2(v) (((v) << 22) & 0xc00000) | ||
| 367 | #define BP_TVENC_VTIMING1_VSTRT_SERRA 16 | ||
| 368 | #define BM_TVENC_VTIMING1_VSTRT_SERRA 0x3f0000 | ||
| 369 | #define BF_TVENC_VTIMING1_VSTRT_SERRA(v) (((v) << 16) & 0x3f0000) | ||
| 370 | #define BP_TVENC_VTIMING1_RSRVD1 10 | ||
| 371 | #define BM_TVENC_VTIMING1_RSRVD1 0xfc00 | ||
| 372 | #define BF_TVENC_VTIMING1_RSRVD1(v) (((v) << 10) & 0xfc00) | ||
| 373 | #define BP_TVENC_VTIMING1_LAST_FLD_LN 0 | ||
| 374 | #define BM_TVENC_VTIMING1_LAST_FLD_LN 0x3ff | ||
| 375 | #define BF_TVENC_VTIMING1_LAST_FLD_LN(v) (((v) << 0) & 0x3ff) | ||
| 376 | |||
| 377 | /** | ||
| 378 | * Register: HW_TVENC_MISC | ||
| 379 | * Address: 0xb0 | ||
| 380 | * SCT: yes | ||
| 381 | */ | ||
| 382 | #define HW_TVENC_MISC (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0x0)) | ||
| 383 | #define HW_TVENC_MISC_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0x4)) | ||
| 384 | #define HW_TVENC_MISC_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0x8)) | ||
| 385 | #define HW_TVENC_MISC_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0xc)) | ||
| 386 | #define BP_TVENC_MISC_RSRVD3 25 | ||
| 387 | #define BM_TVENC_MISC_RSRVD3 0xfe000000 | ||
| 388 | #define BF_TVENC_MISC_RSRVD3(v) (((v) << 25) & 0xfe000000) | ||
| 389 | #define BP_TVENC_MISC_LPF_RST_OFF 16 | ||
| 390 | #define BM_TVENC_MISC_LPF_RST_OFF 0x1ff0000 | ||
| 391 | #define BF_TVENC_MISC_LPF_RST_OFF(v) (((v) << 16) & 0x1ff0000) | ||
| 392 | #define BP_TVENC_MISC_RSRVD2 12 | ||
| 393 | #define BM_TVENC_MISC_RSRVD2 0xf000 | ||
| 394 | #define BF_TVENC_MISC_RSRVD2(v) (((v) << 12) & 0xf000) | ||
| 395 | #define BP_TVENC_MISC_NTSC_LN_CNT 11 | ||
| 396 | #define BM_TVENC_MISC_NTSC_LN_CNT 0x800 | ||
| 397 | #define BF_TVENC_MISC_NTSC_LN_CNT(v) (((v) << 11) & 0x800) | ||
| 398 | #define BP_TVENC_MISC_PAL_FSC_PHASE_ALT 10 | ||
| 399 | #define BM_TVENC_MISC_PAL_FSC_PHASE_ALT 0x400 | ||
| 400 | #define BF_TVENC_MISC_PAL_FSC_PHASE_ALT(v) (((v) << 10) & 0x400) | ||
| 401 | #define BP_TVENC_MISC_FSC_PHASE_RST 8 | ||
| 402 | #define BM_TVENC_MISC_FSC_PHASE_RST 0x300 | ||
| 403 | #define BF_TVENC_MISC_FSC_PHASE_RST(v) (((v) << 8) & 0x300) | ||
| 404 | #define BP_TVENC_MISC_BRUCHB 6 | ||
| 405 | #define BM_TVENC_MISC_BRUCHB 0xc0 | ||
| 406 | #define BF_TVENC_MISC_BRUCHB(v) (((v) << 6) & 0xc0) | ||
| 407 | #define BP_TVENC_MISC_AGC_LVL_CTRL 4 | ||
| 408 | #define BM_TVENC_MISC_AGC_LVL_CTRL 0x30 | ||
| 409 | #define BF_TVENC_MISC_AGC_LVL_CTRL(v) (((v) << 4) & 0x30) | ||
| 410 | #define BP_TVENC_MISC_RSRVD1 3 | ||
| 411 | #define BM_TVENC_MISC_RSRVD1 0x8 | ||
| 412 | #define BF_TVENC_MISC_RSRVD1(v) (((v) << 3) & 0x8) | ||
| 413 | #define BP_TVENC_MISC_CS_INVERT_CTRL 2 | ||
| 414 | #define BM_TVENC_MISC_CS_INVERT_CTRL 0x4 | ||
| 415 | #define BF_TVENC_MISC_CS_INVERT_CTRL(v) (((v) << 2) & 0x4) | ||
| 416 | #define BP_TVENC_MISC_Y_BLANK_CTRL 0 | ||
| 417 | #define BM_TVENC_MISC_Y_BLANK_CTRL 0x3 | ||
| 418 | #define BF_TVENC_MISC_Y_BLANK_CTRL(v) (((v) << 0) & 0x3) | ||
| 419 | |||
| 420 | /** | ||
| 421 | * Register: HW_TVENC_COLORSUB0 | ||
| 422 | * Address: 0xc0 | ||
| 423 | * SCT: yes | ||
| 424 | */ | ||
| 425 | #define HW_TVENC_COLORSUB0 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0x0)) | ||
| 426 | #define HW_TVENC_COLORSUB0_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0x4)) | ||
| 427 | #define HW_TVENC_COLORSUB0_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0x8)) | ||
| 428 | #define HW_TVENC_COLORSUB0_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0xc)) | ||
| 429 | #define BP_TVENC_COLORSUB0_PHASE_INC 0 | ||
| 430 | #define BM_TVENC_COLORSUB0_PHASE_INC 0xffffffff | ||
| 431 | #define BF_TVENC_COLORSUB0_PHASE_INC(v) (((v) << 0) & 0xffffffff) | ||
| 432 | |||
| 433 | /** | ||
| 434 | * Register: HW_TVENC_COLORSUB1 | ||
| 435 | * Address: 0xd0 | ||
| 436 | * SCT: yes | ||
| 437 | */ | ||
| 438 | #define HW_TVENC_COLORSUB1 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0x0)) | ||
| 439 | #define HW_TVENC_COLORSUB1_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0x4)) | ||
| 440 | #define HW_TVENC_COLORSUB1_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0x8)) | ||
| 441 | #define HW_TVENC_COLORSUB1_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0xc)) | ||
| 442 | #define BP_TVENC_COLORSUB1_PHASE_OFFSET 0 | ||
| 443 | #define BM_TVENC_COLORSUB1_PHASE_OFFSET 0xffffffff | ||
| 444 | #define BF_TVENC_COLORSUB1_PHASE_OFFSET(v) (((v) << 0) & 0xffffffff) | ||
| 445 | |||
| 446 | /** | ||
| 447 | * Register: HW_TVENC_COPYPROTECT | ||
| 448 | * Address: 0xe0 | ||
| 449 | * SCT: yes | ||
| 450 | */ | ||
| 451 | #define HW_TVENC_COPYPROTECT (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0x0)) | ||
| 452 | #define HW_TVENC_COPYPROTECT_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0x4)) | ||
| 453 | #define HW_TVENC_COPYPROTECT_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0x8)) | ||
| 454 | #define HW_TVENC_COPYPROTECT_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0xc)) | ||
| 455 | #define BP_TVENC_COPYPROTECT_RSRVD1 16 | ||
| 456 | #define BM_TVENC_COPYPROTECT_RSRVD1 0xffff0000 | ||
| 457 | #define BF_TVENC_COPYPROTECT_RSRVD1(v) (((v) << 16) & 0xffff0000) | ||
| 458 | #define BP_TVENC_COPYPROTECT_WSS_ENBL 15 | ||
| 459 | #define BM_TVENC_COPYPROTECT_WSS_ENBL 0x8000 | ||
| 460 | #define BF_TVENC_COPYPROTECT_WSS_ENBL(v) (((v) << 15) & 0x8000) | ||
| 461 | #define BP_TVENC_COPYPROTECT_CGMS_ENBL 14 | ||
| 462 | #define BM_TVENC_COPYPROTECT_CGMS_ENBL 0x4000 | ||
| 463 | #define BF_TVENC_COPYPROTECT_CGMS_ENBL(v) (((v) << 14) & 0x4000) | ||
| 464 | #define BP_TVENC_COPYPROTECT_WSS_CGMS_DATA 0 | ||
| 465 | #define BM_TVENC_COPYPROTECT_WSS_CGMS_DATA 0x3fff | ||
| 466 | #define BF_TVENC_COPYPROTECT_WSS_CGMS_DATA(v) (((v) << 0) & 0x3fff) | ||
| 467 | |||
| 468 | /** | ||
| 469 | * Register: HW_TVENC_CLOSEDCAPTION | ||
| 470 | * Address: 0xf0 | ||
| 471 | * SCT: yes | ||
| 472 | */ | ||
| 473 | #define HW_TVENC_CLOSEDCAPTION (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0x0)) | ||
| 474 | #define HW_TVENC_CLOSEDCAPTION_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0x4)) | ||
| 475 | #define HW_TVENC_CLOSEDCAPTION_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0x8)) | ||
| 476 | #define HW_TVENC_CLOSEDCAPTION_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0xc)) | ||
| 477 | #define BP_TVENC_CLOSEDCAPTION_RSRVD1 20 | ||
| 478 | #define BM_TVENC_CLOSEDCAPTION_RSRVD1 0xfff00000 | ||
| 479 | #define BF_TVENC_CLOSEDCAPTION_RSRVD1(v) (((v) << 20) & 0xfff00000) | ||
| 480 | #define BP_TVENC_CLOSEDCAPTION_CC_ENBL 18 | ||
| 481 | #define BM_TVENC_CLOSEDCAPTION_CC_ENBL 0xc0000 | ||
| 482 | #define BF_TVENC_CLOSEDCAPTION_CC_ENBL(v) (((v) << 18) & 0xc0000) | ||
| 483 | #define BP_TVENC_CLOSEDCAPTION_CC_FILL 16 | ||
| 484 | #define BM_TVENC_CLOSEDCAPTION_CC_FILL 0x30000 | ||
| 485 | #define BF_TVENC_CLOSEDCAPTION_CC_FILL(v) (((v) << 16) & 0x30000) | ||
| 486 | #define BP_TVENC_CLOSEDCAPTION_CC_DATA 0 | ||
| 487 | #define BM_TVENC_CLOSEDCAPTION_CC_DATA 0xffff | ||
| 488 | #define BF_TVENC_CLOSEDCAPTION_CC_DATA(v) (((v) << 0) & 0xffff) | ||
| 489 | |||
| 490 | /** | ||
| 491 | * Register: HW_TVENC_COLORBURST | ||
| 492 | * Address: 0x140 | ||
| 493 | * SCT: yes | ||
| 494 | */ | ||
| 495 | #define HW_TVENC_COLORBURST (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0x0)) | ||
| 496 | #define HW_TVENC_COLORBURST_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0x4)) | ||
| 497 | #define HW_TVENC_COLORBURST_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0x8)) | ||
| 498 | #define HW_TVENC_COLORBURST_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0xc)) | ||
| 499 | #define BP_TVENC_COLORBURST_NBA 24 | ||
| 500 | #define BM_TVENC_COLORBURST_NBA 0xff000000 | ||
| 501 | #define BF_TVENC_COLORBURST_NBA(v) (((v) << 24) & 0xff000000) | ||
| 502 | #define BP_TVENC_COLORBURST_PBA 16 | ||
| 503 | #define BM_TVENC_COLORBURST_PBA 0xff0000 | ||
| 504 | #define BF_TVENC_COLORBURST_PBA(v) (((v) << 16) & 0xff0000) | ||
| 505 | #define BP_TVENC_COLORBURST_RSRVD1 12 | ||
| 506 | #define BM_TVENC_COLORBURST_RSRVD1 0xf000 | ||
| 507 | #define BF_TVENC_COLORBURST_RSRVD1(v) (((v) << 12) & 0xf000) | ||
| 508 | #define BP_TVENC_COLORBURST_RSRVD2 0 | ||
| 509 | #define BM_TVENC_COLORBURST_RSRVD2 0xfff | ||
| 510 | #define BF_TVENC_COLORBURST_RSRVD2(v) (((v) << 0) & 0xfff) | ||
| 511 | |||
| 512 | /** | ||
| 513 | * Register: HW_TVENC_MACROVISION0 | ||
| 514 | * Address: 0x150 | ||
| 515 | * SCT: yes | ||
| 516 | */ | ||
| 517 | #define HW_TVENC_MACROVISION0 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0x0)) | ||
| 518 | #define HW_TVENC_MACROVISION0_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0x4)) | ||
| 519 | #define HW_TVENC_MACROVISION0_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0x8)) | ||
| 520 | #define HW_TVENC_MACROVISION0_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0xc)) | ||
| 521 | #define BP_TVENC_MACROVISION0_DATA 0 | ||
| 522 | #define BM_TVENC_MACROVISION0_DATA 0xffffffff | ||
| 523 | #define BF_TVENC_MACROVISION0_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 524 | |||
| 525 | /** | ||
| 526 | * Register: HW_TVENC_MACROVISION1 | ||
| 527 | * Address: 0x160 | ||
| 528 | * SCT: yes | ||
| 529 | */ | ||
| 530 | #define HW_TVENC_MACROVISION1 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0x0)) | ||
| 531 | #define HW_TVENC_MACROVISION1_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0x4)) | ||
| 532 | #define HW_TVENC_MACROVISION1_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0x8)) | ||
| 533 | #define HW_TVENC_MACROVISION1_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0xc)) | ||
| 534 | #define BP_TVENC_MACROVISION1_DATA 0 | ||
| 535 | #define BM_TVENC_MACROVISION1_DATA 0xffffffff | ||
| 536 | #define BF_TVENC_MACROVISION1_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 537 | |||
| 538 | /** | ||
| 539 | * Register: HW_TVENC_MACROVISION2 | ||
| 540 | * Address: 0x170 | ||
| 541 | * SCT: yes | ||
| 542 | */ | ||
| 543 | #define HW_TVENC_MACROVISION2 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0x0)) | ||
| 544 | #define HW_TVENC_MACROVISION2_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0x4)) | ||
| 545 | #define HW_TVENC_MACROVISION2_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0x8)) | ||
| 546 | #define HW_TVENC_MACROVISION2_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0xc)) | ||
| 547 | #define BP_TVENC_MACROVISION2_DATA 0 | ||
| 548 | #define BM_TVENC_MACROVISION2_DATA 0xffffffff | ||
| 549 | #define BF_TVENC_MACROVISION2_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 550 | |||
| 551 | /** | ||
| 552 | * Register: HW_TVENC_MACROVISION3 | ||
| 553 | * Address: 0x180 | ||
| 554 | * SCT: yes | ||
| 555 | */ | ||
| 556 | #define HW_TVENC_MACROVISION3 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0x0)) | ||
| 557 | #define HW_TVENC_MACROVISION3_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0x4)) | ||
| 558 | #define HW_TVENC_MACROVISION3_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0x8)) | ||
| 559 | #define HW_TVENC_MACROVISION3_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0xc)) | ||
| 560 | #define BP_TVENC_MACROVISION3_DATA 0 | ||
| 561 | #define BM_TVENC_MACROVISION3_DATA 0xffffffff | ||
| 562 | #define BF_TVENC_MACROVISION3_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 563 | |||
| 564 | /** | ||
| 565 | * Register: HW_TVENC_MACROVISION4 | ||
| 566 | * Address: 0x190 | ||
| 567 | * SCT: yes | ||
| 568 | */ | ||
| 569 | #define HW_TVENC_MACROVISION4 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0x0)) | ||
| 570 | #define HW_TVENC_MACROVISION4_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0x4)) | ||
| 571 | #define HW_TVENC_MACROVISION4_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0x8)) | ||
| 572 | #define HW_TVENC_MACROVISION4_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0xc)) | ||
| 573 | #define BP_TVENC_MACROVISION4_RSRVD2 24 | ||
| 574 | #define BM_TVENC_MACROVISION4_RSRVD2 0xff000000 | ||
| 575 | #define BF_TVENC_MACROVISION4_RSRVD2(v) (((v) << 24) & 0xff000000) | ||
| 576 | #define BP_TVENC_MACROVISION4_MACV_TST 16 | ||
| 577 | #define BM_TVENC_MACROVISION4_MACV_TST 0xff0000 | ||
| 578 | #define BF_TVENC_MACROVISION4_MACV_TST(v) (((v) << 16) & 0xff0000) | ||
| 579 | #define BP_TVENC_MACROVISION4_RSRVD1 11 | ||
| 580 | #define BM_TVENC_MACROVISION4_RSRVD1 0xf800 | ||
| 581 | #define BF_TVENC_MACROVISION4_RSRVD1(v) (((v) << 11) & 0xf800) | ||
| 582 | #define BP_TVENC_MACROVISION4_DATA 0 | ||
| 583 | #define BM_TVENC_MACROVISION4_DATA 0x7ff | ||
| 584 | #define BF_TVENC_MACROVISION4_DATA(v) (((v) << 0) & 0x7ff) | ||
| 585 | |||
| 586 | /** | ||
| 587 | * Register: HW_TVENC_DACCTRL | ||
| 588 | * Address: 0x1a0 | ||
| 589 | * SCT: yes | ||
| 590 | */ | ||
| 591 | #define HW_TVENC_DACCTRL (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0x0)) | ||
| 592 | #define HW_TVENC_DACCTRL_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0x4)) | ||
| 593 | #define HW_TVENC_DACCTRL_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0x8)) | ||
| 594 | #define HW_TVENC_DACCTRL_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0xc)) | ||
| 595 | #define BP_TVENC_DACCTRL_TEST3 31 | ||
| 596 | #define BM_TVENC_DACCTRL_TEST3 0x80000000 | ||
| 597 | #define BF_TVENC_DACCTRL_TEST3(v) (((v) << 31) & 0x80000000) | ||
| 598 | #define BP_TVENC_DACCTRL_RSRVD1 30 | ||
| 599 | #define BM_TVENC_DACCTRL_RSRVD1 0x40000000 | ||
| 600 | #define BF_TVENC_DACCTRL_RSRVD1(v) (((v) << 30) & 0x40000000) | ||
| 601 | #define BP_TVENC_DACCTRL_RSRVD2 29 | ||
| 602 | #define BM_TVENC_DACCTRL_RSRVD2 0x20000000 | ||
| 603 | #define BF_TVENC_DACCTRL_RSRVD2(v) (((v) << 29) & 0x20000000) | ||
| 604 | #define BP_TVENC_DACCTRL_JACK1_DIS_DET_EN 28 | ||
| 605 | #define BM_TVENC_DACCTRL_JACK1_DIS_DET_EN 0x10000000 | ||
| 606 | #define BF_TVENC_DACCTRL_JACK1_DIS_DET_EN(v) (((v) << 28) & 0x10000000) | ||
| 607 | #define BP_TVENC_DACCTRL_TEST2 27 | ||
| 608 | #define BM_TVENC_DACCTRL_TEST2 0x8000000 | ||
| 609 | #define BF_TVENC_DACCTRL_TEST2(v) (((v) << 27) & 0x8000000) | ||
| 610 | #define BP_TVENC_DACCTRL_RSRVD3 26 | ||
| 611 | #define BM_TVENC_DACCTRL_RSRVD3 0x4000000 | ||
| 612 | #define BF_TVENC_DACCTRL_RSRVD3(v) (((v) << 26) & 0x4000000) | ||
| 613 | #define BP_TVENC_DACCTRL_RSRVD4 25 | ||
| 614 | #define BM_TVENC_DACCTRL_RSRVD4 0x2000000 | ||
| 615 | #define BF_TVENC_DACCTRL_RSRVD4(v) (((v) << 25) & 0x2000000) | ||
| 616 | #define BP_TVENC_DACCTRL_JACK1_DET_EN 24 | ||
| 617 | #define BM_TVENC_DACCTRL_JACK1_DET_EN 0x1000000 | ||
| 618 | #define BF_TVENC_DACCTRL_JACK1_DET_EN(v) (((v) << 24) & 0x1000000) | ||
| 619 | #define BP_TVENC_DACCTRL_TEST1 23 | ||
| 620 | #define BM_TVENC_DACCTRL_TEST1 0x800000 | ||
| 621 | #define BF_TVENC_DACCTRL_TEST1(v) (((v) << 23) & 0x800000) | ||
| 622 | #define BP_TVENC_DACCTRL_DISABLE_GND_DETECT 22 | ||
| 623 | #define BM_TVENC_DACCTRL_DISABLE_GND_DETECT 0x400000 | ||
| 624 | #define BF_TVENC_DACCTRL_DISABLE_GND_DETECT(v) (((v) << 22) & 0x400000) | ||
| 625 | #define BP_TVENC_DACCTRL_JACK_DIS_ADJ 20 | ||
| 626 | #define BM_TVENC_DACCTRL_JACK_DIS_ADJ 0x300000 | ||
| 627 | #define BF_TVENC_DACCTRL_JACK_DIS_ADJ(v) (((v) << 20) & 0x300000) | ||
| 628 | #define BP_TVENC_DACCTRL_GAINDN 19 | ||
| 629 | #define BM_TVENC_DACCTRL_GAINDN 0x80000 | ||
| 630 | #define BF_TVENC_DACCTRL_GAINDN(v) (((v) << 19) & 0x80000) | ||
| 631 | #define BP_TVENC_DACCTRL_GAINUP 18 | ||
| 632 | #define BM_TVENC_DACCTRL_GAINUP 0x40000 | ||
| 633 | #define BF_TVENC_DACCTRL_GAINUP(v) (((v) << 18) & 0x40000) | ||
| 634 | #define BP_TVENC_DACCTRL_INVERT_CLK 17 | ||
| 635 | #define BM_TVENC_DACCTRL_INVERT_CLK 0x20000 | ||
| 636 | #define BF_TVENC_DACCTRL_INVERT_CLK(v) (((v) << 17) & 0x20000) | ||
| 637 | #define BP_TVENC_DACCTRL_SELECT_CLK 16 | ||
| 638 | #define BM_TVENC_DACCTRL_SELECT_CLK 0x10000 | ||
| 639 | #define BF_TVENC_DACCTRL_SELECT_CLK(v) (((v) << 16) & 0x10000) | ||
| 640 | #define BP_TVENC_DACCTRL_BYPASS_ACT_CASCODE 15 | ||
| 641 | #define BM_TVENC_DACCTRL_BYPASS_ACT_CASCODE 0x8000 | ||
| 642 | #define BF_TVENC_DACCTRL_BYPASS_ACT_CASCODE(v) (((v) << 15) & 0x8000) | ||
| 643 | #define BP_TVENC_DACCTRL_RSRVD5 14 | ||
| 644 | #define BM_TVENC_DACCTRL_RSRVD5 0x4000 | ||
| 645 | #define BF_TVENC_DACCTRL_RSRVD5(v) (((v) << 14) & 0x4000) | ||
| 646 | #define BP_TVENC_DACCTRL_RSRVD6 13 | ||
| 647 | #define BM_TVENC_DACCTRL_RSRVD6 0x2000 | ||
| 648 | #define BF_TVENC_DACCTRL_RSRVD6(v) (((v) << 13) & 0x2000) | ||
| 649 | #define BP_TVENC_DACCTRL_PWRUP1 12 | ||
| 650 | #define BM_TVENC_DACCTRL_PWRUP1 0x1000 | ||
| 651 | #define BF_TVENC_DACCTRL_PWRUP1(v) (((v) << 12) & 0x1000) | ||
| 652 | #define BP_TVENC_DACCTRL_WELL_TOVDD 11 | ||
| 653 | #define BM_TVENC_DACCTRL_WELL_TOVDD 0x800 | ||
| 654 | #define BF_TVENC_DACCTRL_WELL_TOVDD(v) (((v) << 11) & 0x800) | ||
| 655 | #define BP_TVENC_DACCTRL_RSRVD7 10 | ||
| 656 | #define BM_TVENC_DACCTRL_RSRVD7 0x400 | ||
| 657 | #define BF_TVENC_DACCTRL_RSRVD7(v) (((v) << 10) & 0x400) | ||
| 658 | #define BP_TVENC_DACCTRL_RSRVD8 9 | ||
| 659 | #define BM_TVENC_DACCTRL_RSRVD8 0x200 | ||
| 660 | #define BF_TVENC_DACCTRL_RSRVD8(v) (((v) << 9) & 0x200) | ||
| 661 | #define BP_TVENC_DACCTRL_DUMP_TOVDD1 8 | ||
| 662 | #define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x100 | ||
| 663 | #define BF_TVENC_DACCTRL_DUMP_TOVDD1(v) (((v) << 8) & 0x100) | ||
| 664 | #define BP_TVENC_DACCTRL_LOWER_SIGNAL 7 | ||
| 665 | #define BM_TVENC_DACCTRL_LOWER_SIGNAL 0x80 | ||
| 666 | #define BF_TVENC_DACCTRL_LOWER_SIGNAL(v) (((v) << 7) & 0x80) | ||
| 667 | #define BP_TVENC_DACCTRL_RVAL 4 | ||
| 668 | #define BM_TVENC_DACCTRL_RVAL 0x70 | ||
| 669 | #define BF_TVENC_DACCTRL_RVAL(v) (((v) << 4) & 0x70) | ||
| 670 | #define BP_TVENC_DACCTRL_NO_INTERNAL_TERM 3 | ||
| 671 | #define BM_TVENC_DACCTRL_NO_INTERNAL_TERM 0x8 | ||
| 672 | #define BF_TVENC_DACCTRL_NO_INTERNAL_TERM(v) (((v) << 3) & 0x8) | ||
| 673 | #define BP_TVENC_DACCTRL_HALF_CURRENT 2 | ||
| 674 | #define BM_TVENC_DACCTRL_HALF_CURRENT 0x4 | ||
| 675 | #define BF_TVENC_DACCTRL_HALF_CURRENT(v) (((v) << 2) & 0x4) | ||
| 676 | #define BP_TVENC_DACCTRL_CASC_ADJ 0 | ||
| 677 | #define BM_TVENC_DACCTRL_CASC_ADJ 0x3 | ||
| 678 | #define BF_TVENC_DACCTRL_CASC_ADJ(v) (((v) << 0) & 0x3) | ||
| 679 | |||
| 680 | /** | ||
| 681 | * Register: HW_TVENC_DACSTATUS | ||
| 682 | * Address: 0x1b0 | ||
| 683 | * SCT: yes | ||
| 684 | */ | ||
| 685 | #define HW_TVENC_DACSTATUS (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0x0)) | ||
| 686 | #define HW_TVENC_DACSTATUS_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0x4)) | ||
| 687 | #define HW_TVENC_DACSTATUS_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0x8)) | ||
| 688 | #define HW_TVENC_DACSTATUS_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0xc)) | ||
| 689 | #define BP_TVENC_DACSTATUS_RSRVD1 13 | ||
| 690 | #define BM_TVENC_DACSTATUS_RSRVD1 0xffffe000 | ||
| 691 | #define BF_TVENC_DACSTATUS_RSRVD1(v) (((v) << 13) & 0xffffe000) | ||
| 692 | #define BP_TVENC_DACSTATUS_RSRVD2 12 | ||
| 693 | #define BM_TVENC_DACSTATUS_RSRVD2 0x1000 | ||
| 694 | #define BF_TVENC_DACSTATUS_RSRVD2(v) (((v) << 12) & 0x1000) | ||
| 695 | #define BP_TVENC_DACSTATUS_RSRVD3 11 | ||
| 696 | #define BM_TVENC_DACSTATUS_RSRVD3 0x800 | ||
| 697 | #define BF_TVENC_DACSTATUS_RSRVD3(v) (((v) << 11) & 0x800) | ||
| 698 | #define BP_TVENC_DACSTATUS_JACK1_DET_STATUS 10 | ||
| 699 | #define BM_TVENC_DACSTATUS_JACK1_DET_STATUS 0x400 | ||
| 700 | #define BF_TVENC_DACSTATUS_JACK1_DET_STATUS(v) (((v) << 10) & 0x400) | ||
| 701 | #define BP_TVENC_DACSTATUS_RSRVD4 9 | ||
| 702 | #define BM_TVENC_DACSTATUS_RSRVD4 0x200 | ||
| 703 | #define BF_TVENC_DACSTATUS_RSRVD4(v) (((v) << 9) & 0x200) | ||
| 704 | #define BP_TVENC_DACSTATUS_RSRVD5 8 | ||
| 705 | #define BM_TVENC_DACSTATUS_RSRVD5 0x100 | ||
| 706 | #define BF_TVENC_DACSTATUS_RSRVD5(v) (((v) << 8) & 0x100) | ||
| 707 | #define BP_TVENC_DACSTATUS_JACK1_GROUNDED 7 | ||
| 708 | #define BM_TVENC_DACSTATUS_JACK1_GROUNDED 0x80 | ||
| 709 | #define BF_TVENC_DACSTATUS_JACK1_GROUNDED(v) (((v) << 7) & 0x80) | ||
| 710 | #define BP_TVENC_DACSTATUS_RSRVD6 6 | ||
| 711 | #define BM_TVENC_DACSTATUS_RSRVD6 0x40 | ||
| 712 | #define BF_TVENC_DACSTATUS_RSRVD6(v) (((v) << 6) & 0x40) | ||
| 713 | #define BP_TVENC_DACSTATUS_RSRVD7 5 | ||
| 714 | #define BM_TVENC_DACSTATUS_RSRVD7 0x20 | ||
| 715 | #define BF_TVENC_DACSTATUS_RSRVD7(v) (((v) << 5) & 0x20) | ||
| 716 | #define BP_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ 4 | ||
| 717 | #define BM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ 0x10 | ||
| 718 | #define BF_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ(v) (((v) << 4) & 0x10) | ||
| 719 | #define BP_TVENC_DACSTATUS_RSRVD8 3 | ||
| 720 | #define BM_TVENC_DACSTATUS_RSRVD8 0x8 | ||
| 721 | #define BF_TVENC_DACSTATUS_RSRVD8(v) (((v) << 3) & 0x8) | ||
| 722 | #define BP_TVENC_DACSTATUS_RSRVD9 2 | ||
| 723 | #define BM_TVENC_DACSTATUS_RSRVD9 0x4 | ||
| 724 | #define BF_TVENC_DACSTATUS_RSRVD9(v) (((v) << 2) & 0x4) | ||
| 725 | #define BP_TVENC_DACSTATUS_JACK1_DET_IRQ 1 | ||
| 726 | #define BM_TVENC_DACSTATUS_JACK1_DET_IRQ 0x2 | ||
| 727 | #define BF_TVENC_DACSTATUS_JACK1_DET_IRQ(v) (((v) << 1) & 0x2) | ||
| 728 | #define BP_TVENC_DACSTATUS_ENIRQ_JACK 0 | ||
| 729 | #define BM_TVENC_DACSTATUS_ENIRQ_JACK 0x1 | ||
| 730 | #define BF_TVENC_DACSTATUS_ENIRQ_JACK(v) (((v) << 0) & 0x1) | ||
| 731 | |||
| 732 | /** | ||
| 733 | * Register: HW_TVENC_VDACTEST | ||
| 734 | * Address: 0x1c0 | ||
| 735 | * SCT: yes | ||
| 736 | */ | ||
| 737 | #define HW_TVENC_VDACTEST (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0x0)) | ||
| 738 | #define HW_TVENC_VDACTEST_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0x4)) | ||
| 739 | #define HW_TVENC_VDACTEST_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0x8)) | ||
| 740 | #define HW_TVENC_VDACTEST_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0xc)) | ||
| 741 | #define BP_TVENC_VDACTEST_RSRVD1 14 | ||
| 742 | #define BM_TVENC_VDACTEST_RSRVD1 0xffffc000 | ||
| 743 | #define BF_TVENC_VDACTEST_RSRVD1(v) (((v) << 14) & 0xffffc000) | ||
| 744 | #define BP_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN 13 | ||
| 745 | #define BM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN 0x2000 | ||
| 746 | #define BF_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN(v) (((v) << 13) & 0x2000) | ||
| 747 | #define BP_TVENC_VDACTEST_BYPASS_PIX_INT 12 | ||
| 748 | #define BM_TVENC_VDACTEST_BYPASS_PIX_INT 0x1000 | ||
| 749 | #define BF_TVENC_VDACTEST_BYPASS_PIX_INT(v) (((v) << 12) & 0x1000) | ||
| 750 | #define BP_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP 11 | ||
| 751 | #define BM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP 0x800 | ||
| 752 | #define BF_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP(v) (((v) << 11) & 0x800) | ||
| 753 | #define BP_TVENC_VDACTEST_TEST_FIFO_FULL 10 | ||
| 754 | #define BM_TVENC_VDACTEST_TEST_FIFO_FULL 0x400 | ||
| 755 | #define BF_TVENC_VDACTEST_TEST_FIFO_FULL(v) (((v) << 10) & 0x400) | ||
| 756 | #define BP_TVENC_VDACTEST_DATA 0 | ||
| 757 | #define BM_TVENC_VDACTEST_DATA 0x3ff | ||
| 758 | #define BF_TVENC_VDACTEST_DATA(v) (((v) << 0) & 0x3ff) | ||
| 759 | |||
| 760 | /** | ||
| 761 | * Register: HW_TVENC_VERSION | ||
| 762 | * Address: 0x1d0 | ||
| 763 | * SCT: no | ||
| 764 | */ | ||
| 765 | #define HW_TVENC_VERSION (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1d0)) | ||
| 766 | #define BP_TVENC_VERSION_MAJOR 24 | ||
| 767 | #define BM_TVENC_VERSION_MAJOR 0xff000000 | ||
| 768 | #define BF_TVENC_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 769 | #define BP_TVENC_VERSION_MINOR 16 | ||
| 770 | #define BM_TVENC_VERSION_MINOR 0xff0000 | ||
| 771 | #define BF_TVENC_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 772 | #define BP_TVENC_VERSION_STEP 0 | ||
| 773 | #define BM_TVENC_VERSION_STEP 0xffff | ||
| 774 | #define BF_TVENC_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 775 | |||
| 776 | #endif /* __HEADERGEN__IMX233__TVENC__H__ */ | ||