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Diffstat (limited to 'firmware/target/arm/imx233/regs/imx233/regs-pinctrl.h')
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1 files changed, 216 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-pinctrl.h b/firmware/target/arm/imx233/regs/imx233/regs-pinctrl.h
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index 0000000000..a8faa358c5
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+++ b/firmware/target/arm/imx233/regs/imx233/regs-pinctrl.h
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1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * This file was automatically generated by headergen, DO NOT EDIT it.
9 * headergen version: 2.1.7
10 * XML versions: imx233:3.2.0
11 *
12 * Copyright (C) 2013 by Amaury Pouly
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version 2
17 * of the License, or (at your option) any later version.
18 *
19 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
20 * KIND, either express or implied.
21 *
22 ****************************************************************************/
23#ifndef __HEADERGEN__IMX233__PINCTRL__H__
24#define __HEADERGEN__IMX233__PINCTRL__H__
25
26#define REGS_PINCTRL_BASE (0x80018000)
27
28#define REGS_PINCTRL_VERSION "3.2.0"
29
30/**
31 * Register: HW_PINCTRL_CTRL
32 * Address: 0
33 * SCT: yes
34*/
35#define HW_PINCTRL_CTRL (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x0))
36#define HW_PINCTRL_CTRL_SET (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x4))
37#define HW_PINCTRL_CTRL_CLR (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x8))
38#define HW_PINCTRL_CTRL_TOG (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0xc))
39#define BP_PINCTRL_CTRL_SFTRST 31
40#define BM_PINCTRL_CTRL_SFTRST 0x80000000
41#define BF_PINCTRL_CTRL_SFTRST(v) (((v) << 31) & 0x80000000)
42#define BP_PINCTRL_CTRL_CLKGATE 30
43#define BM_PINCTRL_CTRL_CLKGATE 0x40000000
44#define BF_PINCTRL_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000)
45#define BP_PINCTRL_CTRL_RSRVD2 28
46#define BM_PINCTRL_CTRL_RSRVD2 0x30000000
47#define BF_PINCTRL_CTRL_RSRVD2(v) (((v) << 28) & 0x30000000)
48#define BP_PINCTRL_CTRL_PRESENT3 27
49#define BM_PINCTRL_CTRL_PRESENT3 0x8000000
50#define BF_PINCTRL_CTRL_PRESENT3(v) (((v) << 27) & 0x8000000)
51#define BP_PINCTRL_CTRL_PRESENT2 26
52#define BM_PINCTRL_CTRL_PRESENT2 0x4000000
53#define BF_PINCTRL_CTRL_PRESENT2(v) (((v) << 26) & 0x4000000)
54#define BP_PINCTRL_CTRL_PRESENT1 25
55#define BM_PINCTRL_CTRL_PRESENT1 0x2000000
56#define BF_PINCTRL_CTRL_PRESENT1(v) (((v) << 25) & 0x2000000)
57#define BP_PINCTRL_CTRL_PRESENT0 24
58#define BM_PINCTRL_CTRL_PRESENT0 0x1000000
59#define BF_PINCTRL_CTRL_PRESENT0(v) (((v) << 24) & 0x1000000)
60#define BP_PINCTRL_CTRL_RSRVD1 3
61#define BM_PINCTRL_CTRL_RSRVD1 0xfffff8
62#define BF_PINCTRL_CTRL_RSRVD1(v) (((v) << 3) & 0xfffff8)
63#define BP_PINCTRL_CTRL_IRQOUT2 2
64#define BM_PINCTRL_CTRL_IRQOUT2 0x4
65#define BF_PINCTRL_CTRL_IRQOUT2(v) (((v) << 2) & 0x4)
66#define BP_PINCTRL_CTRL_IRQOUT1 1
67#define BM_PINCTRL_CTRL_IRQOUT1 0x2
68#define BF_PINCTRL_CTRL_IRQOUT1(v) (((v) << 1) & 0x2)
69#define BP_PINCTRL_CTRL_IRQOUT0 0
70#define BM_PINCTRL_CTRL_IRQOUT0 0x1
71#define BF_PINCTRL_CTRL_IRQOUT0(v) (((v) << 0) & 0x1)
72
73/**
74 * Register: HW_PINCTRL_MUXSELn
75 * Address: 0x100+n*0x10
76 * SCT: yes
77*/
78#define HW_PINCTRL_MUXSELn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x0))
79#define HW_PINCTRL_MUXSELn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x4))
80#define HW_PINCTRL_MUXSELn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x8))
81#define HW_PINCTRL_MUXSELn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0xc))
82#define BP_PINCTRL_MUXSELn_BITS 0
83#define BM_PINCTRL_MUXSELn_BITS 0xffffffff
84#define BF_PINCTRL_MUXSELn_BITS(v) (((v) << 0) & 0xffffffff)
85
86/**
87 * Register: HW_PINCTRL_DRIVEn
88 * Address: 0x200+n*0x10
89 * SCT: yes
90*/
91#define HW_PINCTRL_DRIVEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x0))
92#define HW_PINCTRL_DRIVEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x4))
93#define HW_PINCTRL_DRIVEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x8))
94#define HW_PINCTRL_DRIVEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0xc))
95#define BP_PINCTRL_DRIVEn_BITS 0
96#define BM_PINCTRL_DRIVEn_BITS 0xffffffff
97#define BF_PINCTRL_DRIVEn_BITS(v) (((v) << 0) & 0xffffffff)
98
99/**
100 * Register: HW_PINCTRL_PULLn
101 * Address: 0x400+n*0x10
102 * SCT: yes
103*/
104#define HW_PINCTRL_PULLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x0))
105#define HW_PINCTRL_PULLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x4))
106#define HW_PINCTRL_PULLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x8))
107#define HW_PINCTRL_PULLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0xc))
108#define BP_PINCTRL_PULLn_BITS 0
109#define BM_PINCTRL_PULLn_BITS 0xffffffff
110#define BF_PINCTRL_PULLn_BITS(v) (((v) << 0) & 0xffffffff)
111
112/**
113 * Register: HW_PINCTRL_DOUTn
114 * Address: 0x500+n*0x10
115 * SCT: yes
116*/
117#define HW_PINCTRL_DOUTn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x0))
118#define HW_PINCTRL_DOUTn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x4))
119#define HW_PINCTRL_DOUTn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x8))
120#define HW_PINCTRL_DOUTn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0xc))
121#define BP_PINCTRL_DOUTn_BITS 0
122#define BM_PINCTRL_DOUTn_BITS 0xffffffff
123#define BF_PINCTRL_DOUTn_BITS(v) (((v) << 0) & 0xffffffff)
124
125/**
126 * Register: HW_PINCTRL_DINn
127 * Address: 0x600+n*0x10
128 * SCT: yes
129*/
130#define HW_PINCTRL_DINn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x0))
131#define HW_PINCTRL_DINn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x4))
132#define HW_PINCTRL_DINn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x8))
133#define HW_PINCTRL_DINn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0xc))
134#define BP_PINCTRL_DINn_BITS 0
135#define BM_PINCTRL_DINn_BITS 0xffffffff
136#define BF_PINCTRL_DINn_BITS(v) (((v) << 0) & 0xffffffff)
137
138/**
139 * Register: HW_PINCTRL_DOEn
140 * Address: 0x700+n*0x10
141 * SCT: yes
142*/
143#define HW_PINCTRL_DOEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x0))
144#define HW_PINCTRL_DOEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x4))
145#define HW_PINCTRL_DOEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x8))
146#define HW_PINCTRL_DOEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0xc))
147#define BP_PINCTRL_DOEn_BITS 0
148#define BM_PINCTRL_DOEn_BITS 0xffffffff
149#define BF_PINCTRL_DOEn_BITS(v) (((v) << 0) & 0xffffffff)
150
151/**
152 * Register: HW_PINCTRL_PIN2IRQn
153 * Address: 0x800+n*0x10
154 * SCT: yes
155*/
156#define HW_PINCTRL_PIN2IRQn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x0))
157#define HW_PINCTRL_PIN2IRQn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x4))
158#define HW_PINCTRL_PIN2IRQn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x8))
159#define HW_PINCTRL_PIN2IRQn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0xc))
160#define BP_PINCTRL_PIN2IRQn_BITS 0
161#define BM_PINCTRL_PIN2IRQn_BITS 0xffffffff
162#define BF_PINCTRL_PIN2IRQn_BITS(v) (((v) << 0) & 0xffffffff)
163
164/**
165 * Register: HW_PINCTRL_IRQENn
166 * Address: 0x900+n*0x10
167 * SCT: yes
168*/
169#define HW_PINCTRL_IRQENn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x0))
170#define HW_PINCTRL_IRQENn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x4))
171#define HW_PINCTRL_IRQENn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x8))
172#define HW_PINCTRL_IRQENn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0xc))
173#define BP_PINCTRL_IRQENn_BITS 0
174#define BM_PINCTRL_IRQENn_BITS 0xffffffff
175#define BF_PINCTRL_IRQENn_BITS(v) (((v) << 0) & 0xffffffff)
176
177/**
178 * Register: HW_PINCTRL_IRQLEVELn
179 * Address: 0xa00+n*0x10
180 * SCT: yes
181*/
182#define HW_PINCTRL_IRQLEVELn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x0))
183#define HW_PINCTRL_IRQLEVELn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x4))
184#define HW_PINCTRL_IRQLEVELn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x8))
185#define HW_PINCTRL_IRQLEVELn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0xc))
186#define BP_PINCTRL_IRQLEVELn_BITS 0
187#define BM_PINCTRL_IRQLEVELn_BITS 0xffffffff
188#define BF_PINCTRL_IRQLEVELn_BITS(v) (((v) << 0) & 0xffffffff)
189
190/**
191 * Register: HW_PINCTRL_IRQPOLn
192 * Address: 0xb00+n*0x10
193 * SCT: yes
194*/
195#define HW_PINCTRL_IRQPOLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x0))
196#define HW_PINCTRL_IRQPOLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x4))
197#define HW_PINCTRL_IRQPOLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x8))
198#define HW_PINCTRL_IRQPOLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0xc))
199#define BP_PINCTRL_IRQPOLn_BITS 0
200#define BM_PINCTRL_IRQPOLn_BITS 0xffffffff
201#define BF_PINCTRL_IRQPOLn_BITS(v) (((v) << 0) & 0xffffffff)
202
203/**
204 * Register: HW_PINCTRL_IRQSTATn
205 * Address: 0xc00+n*0x10
206 * SCT: yes
207*/
208#define HW_PINCTRL_IRQSTATn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0x0))
209#define HW_PINCTRL_IRQSTATn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0x4))
210#define HW_PINCTRL_IRQSTATn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0x8))
211#define HW_PINCTRL_IRQSTATn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0xc))
212#define BP_PINCTRL_IRQSTATn_BITS 0
213#define BM_PINCTRL_IRQSTATn_BITS 0xffffffff
214#define BF_PINCTRL_IRQSTATn_BITS(v) (((v) << 0) & 0xffffffff)
215
216#endif /* __HEADERGEN__IMX233__PINCTRL__H__ */
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-21 14:08:03 +0000