diff options
Diffstat (limited to 'firmware/target/arm/imx233/power-imx233.h')
-rw-r--r-- | firmware/target/arm/imx233/power-imx233.h | 182 |
1 files changed, 34 insertions, 148 deletions
diff --git a/firmware/target/arm/imx233/power-imx233.h b/firmware/target/arm/imx233/power-imx233.h index 5379326969..e6bd02525b 100644 --- a/firmware/target/arm/imx233/power-imx233.h +++ b/firmware/target/arm/imx233/power-imx233.h | |||
@@ -25,157 +25,47 @@ | |||
25 | #include "system-target.h" | 25 | #include "system-target.h" |
26 | #include "cpu.h" | 26 | #include "cpu.h" |
27 | 27 | ||
28 | #define HW_POWER_BASE 0x80044000 | 28 | #include "regs/regs-power.h" |
29 | 29 | ||
30 | #define HW_POWER_CTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x0)) | 30 | #define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__10mA (1 << 0) |
31 | #define HW_POWER_CTRL__ENIRQ_VBUS_VALID (1 << 3) | 31 | #define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__20mA (1 << 1) |
32 | #define HW_POWER_CTRL__VBUSVALID_IRQ (1 << 4) | 32 | #define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__50mA (1 << 2) |
33 | #define HW_POWER_CTRL__POLARITY_VBUSVALID (1 << 5) | 33 | #define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__100mA (1 << 3) |
34 | #define HW_POWER_CTRL__ENIRQ_DC_OK (1 << 14) | 34 | #define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__200mA (1 << 4) |
35 | #define HW_POWER_CTRL__DC_OK_IRQ (1 << 15) | 35 | #define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__400mA (1 << 5) |
36 | 36 | ||
37 | #define HW_POWER_5VCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x10)) | 37 | #define BV_POWER_CHARGE_BATTCHRG_I__10mA (1 << 0) |
38 | #define HW_POWER_5VCTRL__ENABLE_DCDC (1 << 0) | 38 | #define BV_POWER_CHARGE_BATTCHRG_I__20mA (1 << 1) |
39 | #define HW_POWER_5VCTRL__PWRUP_VBUS_CMPS (1 << 1) | 39 | #define BV_POWER_CHARGE_BATTCHRG_I__50mA (1 << 2) |
40 | #define HW_POWER_5VCTRL__VBUSVALID_5VDETECT (1 << 4) | 40 | #define BV_POWER_CHARGE_BATTCHRG_I__100mA (1 << 3) |
41 | #define HW_POWER_5VCTRL__DCDC_XFER (1 << 5) | 41 | #define BV_POWER_CHARGE_BATTCHRG_I__200mA (1 << 4) |
42 | #define HW_POWER_5VCTRL__VBUSVALID_TRSH_BP 8 | 42 | #define BV_POWER_CHARGE_BATTCHRG_I__400mA (1 << 5) |
43 | #define HW_POWER_5VCTRL__VBUSVALID_TRSH_BM (0x7 << 8) | 43 | |
44 | #define HW_POWER_5VCTRL__VBUSVALID_TRSH_2p9 (0 << 8) | 44 | #define BV_POWER_CHARGE_STOP_ILIMIT__10mA (1 << 0) |
45 | #define HW_POWER_5VCTRL__VBUSVALID_TRSH_4V (1 << 8) | 45 | #define BV_POWER_CHARGE_STOP_ILIMIT__20mA (1 << 1) |
46 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT_BP 12 | 46 | #define BV_POWER_CHARGE_STOP_ILIMIT__50mA (1 << 2) |
47 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT_BM (0x3f << 12) | 47 | #define BV_POWER_CHARGE_STOP_ILIMIT__100mA (1 << 3) |
48 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__10mA (1 << 12) | 48 | |
49 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__20mA (1 << 13) | ||
50 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__50mA (1 << 14) | ||
51 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__100mA (1 << 15) | ||
52 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__200mA (1 << 16) | ||
53 | #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__400mA (1 << 17) | ||
54 | #define HW_POWER_5VCTRL__PWD_CHARGE_4P2 (1 << 20) | ||
55 | |||
56 | #define HW_POWER_MINPWR (*(volatile uint32_t *)(HW_POWER_BASE + 0x20)) | ||
57 | #define HW_POWER_MINPWR__HALF_FETS (1 << 5) | ||
58 | #define HW_POWER_MINPWR__DOUBLE_FETS (1 << 6) | ||
59 | |||
60 | #define HW_POWER_CHARGE (*(volatile uint32_t *)(HW_POWER_BASE + 0x30)) | ||
61 | #define HW_POWER_CHARGE__BATTCHRG_I_BP 0 | ||
62 | #define HW_POWER_CHARGE__BATTCHRG_I_BM 0x3f | ||
63 | #define HW_POWER_CHARGE__BATTCHRG_I__10mA (1 << 0) | ||
64 | #define HW_POWER_CHARGE__BATTCHRG_I__20mA (1 << 1) | ||
65 | #define HW_POWER_CHARGE__BATTCHRG_I__50mA (1 << 2) | ||
66 | #define HW_POWER_CHARGE__BATTCHRG_I__100mA (1 << 3) | ||
67 | #define HW_POWER_CHARGE__BATTCHRG_I__200mA (1 << 4) | ||
68 | #define HW_POWER_CHARGE__BATTCHRG_I__400mA (1 << 5) | ||
69 | #define HW_POWER_CHARGE__STOP_ILIMIT_BP 8 | ||
70 | #define HW_POWER_CHARGE__STOP_ILIMIT_BM 0xf00 | ||
71 | #define HW_POWER_CHARGE__STOP_ILIMIT__10mA (1 << 8) | ||
72 | #define HW_POWER_CHARGE__STOP_ILIMIT__20mA (1 << 9) | ||
73 | #define HW_POWER_CHARGE__STOP_ILIMIT__50mA (1 << 10) | ||
74 | #define HW_POWER_CHARGE__STOP_ILIMIT__100mA (1 << 11) | ||
75 | #define HW_POWER_CHARGE__PWD_BATTCHRG (1 << 16) | ||
76 | #define HW_POWER_CHARGE__CHRG_STS_OFF (1 << 19) | ||
77 | #define HW_POWER_CHARGE__ENABLE_LOAD (1 << 22) | ||
78 | |||
79 | #define HW_POWER_VDDDCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x40)) | ||
80 | #define HW_POWER_VDDDCTRL__TRG_BP 0 | ||
81 | #define HW_POWER_VDDDCTRL__TRG_BM 0x1f | ||
82 | #define HW_POWER_VDDDCTRL__BO_OFFSET_BP 8 | ||
83 | #define HW_POWER_VDDDCTRL__BO_OFFSET_BM (0x7 << 8) | ||
84 | #define HW_POWER_VDDDCTRL__TRG_STEP 25 /* mV */ | 49 | #define HW_POWER_VDDDCTRL__TRG_STEP 25 /* mV */ |
85 | #define HW_POWER_VDDDCTRL__TRG_MIN 800 /* mV */ | 50 | #define HW_POWER_VDDDCTRL__TRG_MIN 800 /* mV */ |
86 | #define HW_POWER_VDDDCTRL__LINREG_OFFSET_BP 16 | 51 | |
87 | #define HW_POWER_VDDDCTRL__LINREG_OFFSET_BM (0x3 << 16) | ||
88 | #define HW_POWER_VDDDCTRL__ENABLE_LINREG (1 << 21) | ||
89 | |||
90 | #define HW_POWER_VDDACTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x50)) | ||
91 | #define HW_POWER_VDDACTRL__TRG_BP 0 | ||
92 | #define HW_POWER_VDDACTRL__TRG_BM 0x1f | ||
93 | #define HW_POWER_VDDACTRL__BO_OFFSET_BP 8 | ||
94 | #define HW_POWER_VDDACTRL__BO_OFFSET_BM (0x7 << 8) | ||
95 | #define HW_POWER_VDDACTRL__TRG_STEP 25 /* mV */ | 52 | #define HW_POWER_VDDACTRL__TRG_STEP 25 /* mV */ |
96 | #define HW_POWER_VDDACTRL__TRG_MIN 1500 /* mV */ | 53 | #define HW_POWER_VDDACTRL__TRG_MIN 1500 /* mV */ |
97 | #define HW_POWER_VDDACTRL__LINREG_OFFSET_BP 12 | 54 | |
98 | #define HW_POWER_VDDACTRL__LINREG_OFFSET_BM (0x3 << 12) | ||
99 | #define HW_POWER_VDDACTRL__ENABLE_LINREG (1 << 17) | ||
100 | |||
101 | #define HW_POWER_VDDIOCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x60)) | ||
102 | #define HW_POWER_VDDIOCTRL__TRG_BP 0 | ||
103 | #define HW_POWER_VDDIOCTRL__TRG_BM 0x1f | ||
104 | #define HW_POWER_VDDIOCTRL__BO_OFFSET_BP 8 | ||
105 | #define HW_POWER_VDDIOCTRL__BO_OFFSET_BM (0x7 << 8) | ||
106 | #define HW_POWER_VDDIOCTRL__TRG_STEP 25 /* mV */ | 55 | #define HW_POWER_VDDIOCTRL__TRG_STEP 25 /* mV */ |
107 | #define HW_POWER_VDDIOCTRL__TRG_MIN 2800 /* mV */ | 56 | #define HW_POWER_VDDIOCTRL__TRG_MIN 2800 /* mV */ |
108 | #define HW_POWER_VDDIOCTRL__LINREG_OFFSET_BP 12 | ||
109 | #define HW_POWER_VDDIOCTRL__LINREG_OFFSET_BM (0x3 << 12) | ||
110 | 57 | ||
111 | #define HW_POWER_VDDMEMCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x70)) | ||
112 | #define HW_POWER_VDDMEMCTRL__TRG_BP 0 | ||
113 | #define HW_POWER_VDDMEMCTRL__TRG_BM 0x1f | ||
114 | #define HW_POWER_VDDMEMCTRL__TRG_STEP 50 /* mV */ | 58 | #define HW_POWER_VDDMEMCTRL__TRG_STEP 50 /* mV */ |
115 | #define HW_POWER_VDDMEMCTRL__TRG_MIN 1700 /* mV */ | 59 | #define HW_POWER_VDDMEMCTRL__TRG_MIN 1700 /* mV */ |
116 | #define HW_POWER_VDDMEMCTRL__ENABLE_LINREG (1 << 8) | 60 | |
117 | 61 | #define BV_POWER_MISC_FREQSEL__RES 0 | |
118 | #define HW_POWER_DCDC4P2 (*(volatile uint32_t *)(HW_POWER_BASE + 0x80)) | 62 | #define BV_POWER_MISC_FREQSEL__20MHz 1 |
119 | #define HW_POWER_DCDC4P2__CMPTRIP_BP 0 | 63 | #define BV_POWER_MISC_FREQSEL__24MHz 2 |
120 | #define HW_POWER_DCDC4P2__CMPTRIP_BM 0x1f | 64 | #define BV_POWER_MISC_FREQSEL__19p2MHz 3 |
121 | #define HW_POWER_DCDC4P2__CMPTRIP__0p85 0 | 65 | #define BV_POWER_MISC_FREQSEL__14p4MHz 4 |
122 | #define HW_POWER_DCDC4P2__ENABLE_DCDC (1 << 22) | 66 | #define BV_POWER_MISC_FREQSEL__18MHz 5 |
123 | #define HW_POWER_DCDC4P2__ENABLE_4P2 (1 << 23) | 67 | #define BV_POWER_MISC_FREQSEL__21p6MHz 6 |
124 | #define HW_POWER_DCDC4P2__DROPOUT_CTRL_BP 28 | 68 | #define BV_POWER_MISC_FREQSEL__17p28MHz 7 |
125 | #define HW_POWER_DCDC4P2__DROPOUT_CTRL_BM (0xf << 28) | ||
126 | #define HW_POWER_DCDC4P2__DROPOUT_CTRL__200mV (3 << 30) | ||
127 | #define HW_POWER_DCDC4P2__DROPOUT_CTRL__HIGHER (2 << 28) | ||
128 | |||
129 | #define HW_POWER_MISC (*(volatile uint32_t *)(HW_POWER_BASE + 0x90)) | ||
130 | #define HW_POWER_MISC__SEL_PLLCLK 1 | ||
131 | #define HW_POWER_MISC__FREQSEL_BP 4 | ||
132 | #define HW_POWER_MISC__FREQSEL_BM (0x7 << 4) | ||
133 | #define HW_POWER_MISC__FREQSEL__RES 0 | ||
134 | #define HW_POWER_MISC__FREQSEL__20MHz 1 | ||
135 | #define HW_POWER_MISC__FREQSEL__24MHz 2 | ||
136 | #define HW_POWER_MISC__FREQSEL__19p2MHz 3 | ||
137 | #define HW_POWER_MISC__FREQSEL__14p4MHz 4 | ||
138 | #define HW_POWER_MISC__FREQSEL__18MHz 5 | ||
139 | #define HW_POWER_MISC__FREQSEL__21p6MHz 6 | ||
140 | #define HW_POWER_MISC__FREQSEL__17p28MHz 7 | ||
141 | |||
142 | #define HW_POWER_LOOPCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0xb0)) | ||
143 | #define HW_POWER_LOOPCTRL__DC_C_BP 0 | ||
144 | #define HW_POWER_LOOPCTRL__DC_C_BM 0x3 | ||
145 | #define HW_POWER_LOOPCTRL__DC_R_BP 4 | ||
146 | #define HW_POWER_LOOPCTRL__DC_R_BM 0xf0 | ||
147 | #define HW_POWER_LOOPCTRL__DC_FF_BP 8 | ||
148 | #define HW_POWER_LOOPCTRL__DC_FF_BM (0x7 << 8) | ||
149 | #define HW_POWER_LOOPCTRL__EN_RCSCALE_BP 12 | ||
150 | #define HW_POWER_LOOPCTRL__EN_RCSCALE_BM (0x3 << 12) | ||
151 | #define HW_POWER_LOOPCTRL__EN_RCSCALE__DISABLED 0 | ||
152 | #define HW_POWER_LOOPCTRL__EN_RCSCALE__2X 1 | ||
153 | #define HW_POWER_LOOPCTRL__EN_RCSCALE__4X 2 | ||
154 | #define HW_POWER_LOOPCTRL__EN_RCSCALE__8X 3 | ||
155 | #define HW_POWER_LOOPCTRL__RCSCALE_THRESH (1 << 14) | ||
156 | #define HW_POWER_LOOPCTRL__DF_HYST_THRESH (1 << 15) | ||
157 | #define HW_POWER_LOOPCTRL__CM_HYST_THRESH (1 << 16) | ||
158 | #define HW_POWER_LOOPCTRL__EN_DF_HYST (1 << 17) | ||
159 | #define HW_POWER_LOOPCTRL__EN_CM_HYST (1 << 18) | ||
160 | #define HW_POWER_LOOPCTRL__HYST_SIGN (1 << 19) | ||
161 | #define HW_POWER_LOOPCTRL__TOGGLE_DIF (1 << 20) | ||
162 | |||
163 | #define HW_POWER_STS (*(volatile uint32_t *)(HW_POWER_BASE + 0xc0)) | ||
164 | #define HW_POWER_STS__VBUSVALID (1 << 1) | ||
165 | #define HW_POWER_STS__CHRGSTS (1 << 11) | ||
166 | #define HW_POWER_STS__PSWITCH_BP 20 | ||
167 | #define HW_POWER_STS__PSWITCH_BM (3 << 20) | ||
168 | #define HW_POWER_STS__PWRUP_SOURCE_BP 24 | ||
169 | #define HW_POWER_STS__PWRUP_SOURCE_BM (0x3f << 24) | ||
170 | |||
171 | #define HW_POWER_BATTMONITOR (*(volatile uint32_t *)(HW_POWER_BASE + 0xe0)) | ||
172 | #define HW_POWER_BATTMONITOR__ENBATADJ (1 << 10) | ||
173 | #define HW_POWER_BATTMONITOR__BATT_VAL_BP 16 | ||
174 | #define HW_POWER_BATTMONITOR__BATT_VAL_BM (0x3ff << 16) | ||
175 | |||
176 | #define HW_POWER_RESET (*(volatile uint32_t *)(HW_POWER_BASE + 0x100)) | ||
177 | #define HW_POWER_RESET__UNLOCK 0x3E770000 | ||
178 | #define HW_POWER_RESET__PWD 0x1 | ||
179 | 69 | ||
180 | void imx233_power_init(void); | 70 | void imx233_power_init(void); |
181 | 71 | ||
@@ -209,13 +99,9 @@ void imx233_power_set_regulator_linreg(enum imx233_regulator_t reg, | |||
209 | 99 | ||
210 | static inline void imx233_power_set_dcdc_freq(bool pll, unsigned freq) | 100 | static inline void imx233_power_set_dcdc_freq(bool pll, unsigned freq) |
211 | { | 101 | { |
212 | HW_POWER_MISC &= ~(HW_POWER_MISC__SEL_PLLCLK | HW_POWER_MISC__FREQSEL_BM); | ||
213 | /* WARNING: HW_POWER_MISC does not have a SET/CLR variant ! */ | ||
214 | if(pll) | 102 | if(pll) |
215 | { | 103 | BF_WR(POWER_MISC, FREQSEL, freq); |
216 | HW_POWER_MISC |= freq << HW_POWER_MISC__FREQSEL_BP; | 104 | BF_WR(POWER_MISC, SEL_PLLCLK, pll); |
217 | HW_POWER_MISC |= HW_POWER_MISC__SEL_PLLCLK; | ||
218 | } | ||
219 | } | 105 | } |
220 | 106 | ||
221 | struct imx233_power_info_t | 107 | struct imx233_power_info_t |