diff options
Diffstat (limited to 'firmware/target/arm/imx233/dma-imx233.h')
-rw-r--r-- | firmware/target/arm/imx233/dma-imx233.h | 161 |
1 files changed, 161 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/dma-imx233.h b/firmware/target/arm/imx233/dma-imx233.h new file mode 100644 index 0000000000..ce13aba89f --- /dev/null +++ b/firmware/target/arm/imx233/dma-imx233.h | |||
@@ -0,0 +1,161 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2011 by amaury Pouly | ||
11 | * | ||
12 | * Based on Rockbox iriver bootloader by Linus Nielsen Feltzing | ||
13 | * and the ipodlinux bootloader by Daniel Palffy and Bernard Leach | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __DMA_IMX233_H__ | ||
25 | #define __DMA_IMX233_H__ | ||
26 | |||
27 | #include "cpu.h" | ||
28 | #include "system.h" | ||
29 | #include "system-target.h" | ||
30 | |||
31 | /******** | ||
32 | * APHB * | ||
33 | ********/ | ||
34 | |||
35 | #define HW_APBH_BASE 0x80004000 | ||
36 | |||
37 | /* APHB channels */ | ||
38 | #define HW_APBH_SSP(ssp) ssp | ||
39 | |||
40 | #define HW_APBH_CTRL0 (*(volatile uint32_t *)(HW_APBH_BASE + 0x0)) | ||
41 | #define HW_APBH_CTRL0__FREEZE_CHANNEL(i) (1 << (i)) | ||
42 | #define HW_APBH_CTRL0__CLKGATE_CHANNEL(i) (1 << ((i) + 8)) | ||
43 | #define HW_APBH_CTRL0__RESET_CHANNEL(i) (1 << ((i) + 16)) | ||
44 | #define HW_APBH_CTRL0__APB_BURST4_EN (1 << 28) | ||
45 | #define HW_APBH_CTRL0__APB_BURST8_EN (1 << 29) | ||
46 | |||
47 | #define HW_APBH_CTRL1 (*(volatile uint32_t *)(HW_APBH_BASE + 0x10)) | ||
48 | #define HW_APBH_CTRL1__CHx_CMDCMPLT_IRQ(i) (1 << (i)) | ||
49 | #define HW_APBH_CTRL1__CHx_CMDCMPLT_IRQ_EN(i) (1 << ((i) + 16)) | ||
50 | |||
51 | #define HW_APBH_CTRL2 (*(volatile uint32_t *)(HW_APBH_BASE + 0x20)) | ||
52 | #define HW_APBH_CTRL2__CHx_ERROR_IRQ(i) (1 << (i)) | ||
53 | #define HW_APBH_CTRL2__CHx_ERROR_STATUS(i) (1 << ((i) + 16)) | ||
54 | |||
55 | #define HW_APBH_CHx_CURCMDAR(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x40 + 0x70 * (i))) | ||
56 | |||
57 | #define HW_APBH_CHx_NXTCMDAR(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x50 + 0x70 * (i))) | ||
58 | |||
59 | #define HW_APBH_CHx_CMD(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x60 + 0x70 * (i))) | ||
60 | |||
61 | #define HW_APBH_CHx_BAR(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x70 + 0x70 * (i))) | ||
62 | |||
63 | #define HW_APBH_CHx_SEMA(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x80 + 0x70 * (i))) | ||
64 | |||
65 | #define HW_APBH_CHx_DEBUG1(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x90 + 0x70 * (i))) | ||
66 | |||
67 | #define HW_APBH_CHx_DEBUG2(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0xa0 + 0x70 * (i))) | ||
68 | |||
69 | /******** | ||
70 | * APHX * | ||
71 | ********/ | ||
72 | |||
73 | /* APHX channels */ | ||
74 | #define HW_APBX_AUDIO_ADC 0 | ||
75 | #define HW_APBX_AUDIO_DAC 1 | ||
76 | |||
77 | #define HW_APBX_BASE 0x80024000 | ||
78 | |||
79 | #define HW_APBX_CTRL0 (*(volatile uint32_t *)(HW_APBX_BASE + 0x0)) | ||
80 | |||
81 | #define HW_APBX_CTRL1 (*(volatile uint32_t *)(HW_APBX_BASE + 0x10)) | ||
82 | #define HW_APBX_CTRL1__CHx_CMDCMPLT_IRQ(i) (1 << (i)) | ||
83 | #define HW_APBX_CTRL1__CHx_CMDCMPLT_IRQ_EN(i) (1 << ((i) + 16)) | ||
84 | |||
85 | #define HW_APBX_CTRL2 (*(volatile uint32_t *)(HW_APBX_BASE + 0x20)) | ||
86 | #define HW_APBX_CTRL2__CHx_ERROR_IRQ(i) (1 << (i)) | ||
87 | #define HW_APBX_CTRL2__CHx_ERROR_STATUS(i) (1 << ((i) + 16)) | ||
88 | |||
89 | #define HW_APBX_CHANNEL_CTRL (*(volatile uint32_t *)(HW_APBX_BASE + 0x30)) | ||
90 | #define HW_APBX_CHANNEL_CTRL__FREEZE_CHANNEL(i) (1 << (i)) | ||
91 | #define HW_APBX_CHANNEL_CTRL__RESET_CHANNEL(i) (1 << ((i) + 16)) | ||
92 | |||
93 | #define HW_APBX_CHx_CURCMDAR(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x100 + (i) * 0x70)) | ||
94 | |||
95 | #define HW_APBX_CHx_NXTCMDAR(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x110 + (i) * 0x70)) | ||
96 | |||
97 | #define HW_APBX_CHx_CMD(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x120 + (i) * 0x70)) | ||
98 | |||
99 | #define HW_APBX_CHx_BAR(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x130 + (i) * 0x70)) | ||
100 | |||
101 | #define HW_APBX_CHx_SEMA(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x140 + (i) * 0x70)) | ||
102 | |||
103 | #define HW_APBX_CHx_DEBUG1(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x150 + (i) * 0x70)) | ||
104 | |||
105 | #define HW_APBX_CHx_DEBUG2(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x160 + (i) * 0x70)) | ||
106 | |||
107 | /********** | ||
108 | * COMMON * | ||
109 | **********/ | ||
110 | |||
111 | struct apb_dma_command_t | ||
112 | { | ||
113 | struct apb_dma_command_t *next; | ||
114 | uint32_t cmd; | ||
115 | void *buffer; | ||
116 | /* PIO words follow */ | ||
117 | }; | ||
118 | |||
119 | #define APBH_DMA_CHANNEL(i) i | ||
120 | #define APBX_DMA_CHANNEL(i) ((i) | 0x10) | ||
121 | #define APB_IS_APBX_CHANNEL(x) ((x) & 0x10) | ||
122 | #define APB_GET_DMA_CHANNEL(x) ((x) & 0xf) | ||
123 | |||
124 | #define APB_SSP(ssp) APBH_DMA_CHANNEL(HW_APBH_SSP(ssp)) | ||
125 | #define APB_AUDIO_ADC APBX_DMA_CHANNEL(HW_APBX_AUDIO_ADC) | ||
126 | |||
127 | #define HW_APB_CHx_CMD__COMMAND_BM 0x3 | ||
128 | #define HW_APB_CHx_CMD__COMMAND__NO_XFER 0 | ||
129 | #define HW_APB_CHx_CMD__COMMAND__WRITE 1 | ||
130 | #define HW_APB_CHx_CMD__COMMAND__READ 2 | ||
131 | #define HW_APB_CHx_CMD__COMMAND__SENSE 3 | ||
132 | #define HW_APB_CHx_CMD__CHAIN (1 << 2) | ||
133 | #define HW_APB_CHx_CMD__IRQONCMPLT (1 << 3) | ||
134 | /* those two are only available on APHB */ | ||
135 | #define HW_APBH_CHx_CMD__NANDLOCK (1 << 4) | ||
136 | #define HW_APBH_CHx_CMD__NANDWAIT4READY (1 << 5) | ||
137 | #define HW_APB_CHx_CMD__SEMAPHORE (1 << 6) | ||
138 | #define HW_APB_CHx_CMD__WAIT4ENDCMD (1 << 7) | ||
139 | #define HW_APB_CHx_CMD__HALTONTERMINATE (1 << 8) | ||
140 | #define HW_APB_CHx_CMD__CMDWORDS_BM 0xf000 | ||
141 | #define HW_APB_CHx_CMD__CMDWORDS_BP 12 | ||
142 | #define HW_APB_CHx_CMD__XFER_COUNT_BM 0xffff0000 | ||
143 | #define HW_APB_CHx_CMD__XFER_COUNT_BP 16 | ||
144 | |||
145 | #define HW_APB_CHx_SEMA__PHORE_BM 0xff0000 | ||
146 | #define HW_APB_CHx_SEMA__PHORE_BP 16 | ||
147 | |||
148 | void imx233_dma_init(void); | ||
149 | void imx233_dma_reset_channel(unsigned chan); | ||
150 | /* only apbh channel have clkgate control */ | ||
151 | void imx233_dma_clkgate_channel(unsigned chan, bool enable_clock); | ||
152 | |||
153 | void imx233_dma_enable_channel_interrupt(unsigned chan, bool enable); | ||
154 | /* clear both channel complete and error bits */ | ||
155 | void imx233_dma_clear_channel_interrupt(unsigned chan); | ||
156 | bool imx233_dma_is_channel_error_irq(unsigned chan); | ||
157 | /* assume no command is in progress */ | ||
158 | void imx233_dma_start_command(unsigned chan, struct apb_dma_command_t *cmd); | ||
159 | void imx233_dma_wait_completion(unsigned chan); | ||
160 | |||
161 | #endif // __DMA_IMX233_H__ | ||