diff options
Diffstat (limited to 'firmware/target/arm/imx233/dcp-imx233.h')
-rw-r--r-- | firmware/target/arm/imx233/dcp-imx233.h | 363 |
1 files changed, 363 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/dcp-imx233.h b/firmware/target/arm/imx233/dcp-imx233.h new file mode 100644 index 0000000000..375da16c04 --- /dev/null +++ b/firmware/target/arm/imx233/dcp-imx233.h | |||
@@ -0,0 +1,363 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2011 by amaury Pouly | ||
11 | * | ||
12 | * Based on Rockbox iriver bootloader by Linus Nielsen Feltzing | ||
13 | * and the ipodlinux bootloader by Daniel Palffy and Bernard Leach | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __DCP_IMX233_H__ | ||
25 | #define __DCP_IMX233_H__ | ||
26 | |||
27 | #include "cpu.h" | ||
28 | #include "system.h" | ||
29 | #include "system-target.h" | ||
30 | |||
31 | #define HW_DCP_BASE 0x80028000 | ||
32 | |||
33 | /* channels */ | ||
34 | #define HW_DCP_CH(x) (x) | ||
35 | #define HW_DCP_NUM_CHANNELS 4 | ||
36 | #define HW_DCP_CSC 8 | ||
37 | |||
38 | /* ciphers */ | ||
39 | #define HW_DCP_CIPHER_AES128 1 | ||
40 | |||
41 | /* hash */ | ||
42 | #define HW_DCP_HASH_SHA1 1 | ||
43 | #define HW_DCP_HASH_CRC32 2 | ||
44 | |||
45 | #define HW_DCP_CTRL (*(volatile uint32_t *)(HW_DCP_BASE + 0x0)) | ||
46 | #define HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE_BP 0 | ||
47 | #define HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE_BM 0xf | ||
48 | #define HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(x) (1 << (x)) | ||
49 | #define HW_DCP_CTRL__CSC_INTERRUPT_ENABLE (1 << 8) | ||
50 | #define HW_DCP_CTRL__ENABLE_CONTEXT_SWITCHING (1 << 21) | ||
51 | #define HW_DCP_CTRL__ENABLE_CONTEXT_CACHING (1 << 22) | ||
52 | #define HW_DCP_CTRL__GATHER_RESIDUAL_WRITES (1 << 23) | ||
53 | #define HW_DCP_CTRL__PRESENT_CSC (1 << 28) | ||
54 | #define HW_DCP_CTRL__PRESENT_CRYPTO (1 << 29) | ||
55 | |||
56 | #define HW_DCP_STAT (*(volatile uint32_t *)(HW_DCP_BASE + 0x10)) | ||
57 | #define HW_DCP_STAT__IRQ_BP 0 | ||
58 | #define HW_DCP_STAT__IRQ_BM 0xf | ||
59 | #define HW_DCP_STAT__IRQ(x) (1 << (x)) | ||
60 | #define HW_DCP_STAT__CSCIRQ (1 << 8) | ||
61 | #define HW_DCP_STAT__READY_CHANNELS_BP 16 | ||
62 | #define HW_DCP_STAT__READY_CHANNELS_BM (0xff << 16) | ||
63 | #define HW_DCP_STAT__READY_CHANNELS(x) (1 << (16 + (x))) | ||
64 | #define HW_DCP_STAT__CUR_CHANNEL_BP 24 | ||
65 | #define HW_DCP_STAT__CUR_CHANNEL_BM (0xf << 24) | ||
66 | #define HW_DCP_STAT__OTP_KEY_READY (1 << 28) | ||
67 | |||
68 | #define HW_DCP_CHANNELCTRL (*(volatile uint32_t *)(HW_DCP_BASE + 0x20)) | ||
69 | #define HW_DCP_CHANNELCTRL__ENABLE_CHANNEL_BP 0 | ||
70 | #define HW_DCP_CHANNELCTRL__ENABLE_CHANNEL_BM 0xff | ||
71 | #define HW_DCP_CHANNELCTRL__ENABLE_CHANNEL(x) (1 << (x)) | ||
72 | #define HW_DCP_CHANNELCTRL__HIGH_PRIORITY_CHANNEL_BP 8 | ||
73 | #define HW_DCP_CHANNELCTRL__HIGH_PRIORITY_CHANNEL_BM (0xff << 8) | ||
74 | #define HW_DCP_CHANNELCTRL__HIGH_PRIORITY_CHANNEL(x) (1 << (8 + (x))) | ||
75 | #define HW_DCP_CHANNELCTRL__CH0_IRQ_MERGED (1 << 16) | ||
76 | #define HW_DCP_CHANNELCTRL__CSC_PRIORITY_BP 17 | ||
77 | #define HW_DCP_CHANNELCTRL__CSC_PRIORITY_BM (3 << 17) | ||
78 | |||
79 | #define HW_DCP_CAPABILITY0 (*(volatile uint32_t *)(HW_DCP_BASE + 0x30)) | ||
80 | #define HW_DCP_CAPABILITY0__NUM_KEYS_BP 0 | ||
81 | #define HW_DCP_CAPABILITY0__NUM_KEYS_BM 0xff | ||
82 | #define HW_DCP_CAPABILITY0__NUM_CHANNELS_BP 8 | ||
83 | #define HW_DCP_CAPABILITY0__NUM_CHANNELS_BM 0xf00 | ||
84 | #define HW_DCP_CAPABILITY0__ENABLE_TZONE (1 << 30) | ||
85 | #define HW_DCP_CAPABILITY0__DISABLE_DECRYPT (1 << 31) | ||
86 | |||
87 | #define HW_DCP_CAPABILITY1 (*(volatile uint32_t *)(HW_DCP_BASE + 0x40)) | ||
88 | #define HW_DCP_CAPABILITY1__CIPHER_ALGORITHMS_BP 0 | ||
89 | #define HW_DCP_CAPABILITY1__CIPHER_ALGORITHMS_BM 0xffff | ||
90 | #define HW_DCP_CAPABILITY1__HASH_ALGORITHMS_BP 16 | ||
91 | #define HW_DCP_CAPABILITY1__HASH_ALGORITHMS_BM 0xffff0000 | ||
92 | |||
93 | #define HW_DCP_CONTEXT (*(volatile uint32_t *)(HW_DCP_BASE + 0x50)) | ||
94 | |||
95 | #define HW_DCP_KEY (*(volatile uint32_t *)(HW_DCP_BASE + 0x60)) | ||
96 | |||
97 | #define HW_DCP_KEYDATA (*(volatile uint32_t *)(HW_DCP_BASE + 0x70)) | ||
98 | |||
99 | #define HW_DCP_PACKET0 (*(volatile uint32_t *)(HW_DCP_BASE + 0x80)) | ||
100 | |||
101 | #define HW_DCP_PACKET1 (*(volatile uint32_t *)(HW_DCP_BASE + 0x90)) | ||
102 | |||
103 | #define HW_DCP_PACKET2 (*(volatile uint32_t *)(HW_DCP_BASE + 0xa0)) | ||
104 | |||
105 | #define HW_DCP_PACKET3 (*(volatile uint32_t *)(HW_DCP_BASE + 0xb0)) | ||
106 | |||
107 | #define HW_DCP_PACKET4 (*(volatile uint32_t *)(HW_DCP_BASE + 0xc0)) | ||
108 | |||
109 | #define HW_DCP_PACKET5 (*(volatile uint32_t *)(HW_DCP_BASE + 0xd0)) | ||
110 | |||
111 | #define HW_DCP_PACKET6 (*(volatile uint32_t *)(HW_DCP_BASE + 0xe0)) | ||
112 | |||
113 | #define HW_DCP_CHxCMDPTR(x) (*(volatile uint32_t *)(HW_DCP_BASE + 0x100 + (x) * 0x40)) | ||
114 | |||
115 | #define HW_DCP_CHxSEMA(x) (*(volatile uint32_t *)(HW_DCP_BASE + 0x110 + (x) * 0x40)) | ||
116 | #define HW_DCP_CHxSEMA__INCREMENT_BP 0 | ||
117 | #define HW_DCP_CHxSEMA__INCREMENT_BM 0xff | ||
118 | #define HW_DCP_CHxSEMA__VALUE_BP 16 | ||
119 | #define HW_DCP_CHxSEMA__VALUE_BM 0xff0000 | ||
120 | |||
121 | #define HW_DCP_CHxSTAT(x) (*(volatile uint32_t *)(HW_DCP_BASE + 0x120 + (x) * 0x40)) | ||
122 | |||
123 | #define HW_DCP_CHxOPTS(x) (*(volatile uint32_t *)(HW_DCP_BASE + 0x130 + (x) * 0x40)) | ||
124 | #define HW_DCP_CHxOPTS__RECOVERY_TIMER_BP 0 | ||
125 | #define HW_DCP_CHxOPTS__RECOVERY_TIMER_BM 0xffff | ||
126 | |||
127 | #define HW_DCP_CSCCTRL0 (*(volatile uint32_t *)(HW_DCP_BASE + 0x300)) | ||
128 | #define HW_DCP_CSCCTRL0__ENABLE (1 << 0) | ||
129 | #define HW_DCP_CSCCTRL0__YUV_FORMAT_BP 4 | ||
130 | #define HW_DCP_CSCCTRL0__YUV_FORMAT_BM 0xf0 | ||
131 | #define HW_DCP_CSCCTRL0__YUV_FORMAT__YUV420 0x0 | ||
132 | #define HW_DCP_CSCCTRL0__YUV_FORMAT__YUV422 0x2 | ||
133 | #define HW_DCP_CSCCTRL0__RGB_FORMAT_BP 8 | ||
134 | #define HW_DCP_CSCCTRL0__RGB_FORMAT_BM 0x300 | ||
135 | #define HW_DCP_CSCCTRL0__RGB_FORMAT__RGB16_565 0x0 | ||
136 | #define HW_DCP_CSCCTRL0__RGB_FORMAT__YCbCrI 0x1 | ||
137 | #define HW_DCP_CSCCTRL0__RGB_FORMAT__RGB24 0x2 | ||
138 | #define HW_DCP_CSCCTRL0__RGB_FORMAT__YUV422I 0x3 | ||
139 | #define HW_DCP_CSCCTRL0__DELTA (1 << 10) | ||
140 | #define HW_DCP_CSCCTRL0__SUBSAMPLE (1 << 11) | ||
141 | #define HW_DCP_CSCCTRL0__ROTATE (1 << 12) | ||
142 | #define HW_DCP_CSCCTRL0__SCALE (1 << 13) | ||
143 | #define HW_DCP_CSCCTRL0__UPSAMPLE (1 << 14) | ||
144 | #define HW_DCP_CSCCTRL0__CLIP (1 << 15) | ||
145 | |||
146 | #define HW_DCP_CSCSTAT (*(volatile uint32_t *)(HW_DCP_BASE + 0x310)) | ||
147 | #define HW_DCP_CSCSTAT__COMPLETE (1 << 0) | ||
148 | #define HW_DCP_CSCSTAT__ERROR_SETUP (1 << 2) | ||
149 | #define HW_DCP_CSCSTAT__ERROR_SRC (1 << 4) | ||
150 | #define HW_DCP_CSCSTAT__ERROR_DST (1 << 5) | ||
151 | #define HW_DCP_CSCSTAT__ERROR_PAGEFAULT (1 << 6) | ||
152 | #define HW_DCP_CSCSTAT__ERROR_CODE_BP 16 | ||
153 | #define HW_DCP_CSCSTAT__ERROR_CODE_BM (0xff << 16) | ||
154 | |||
155 | #define HW_DCP_CSCOUTBUFPARAM (*(volatile uint32_t *)(HW_DCP_BASE + 0x320)) | ||
156 | #define HW_DCP_CSCOUTBUFPARAM__LINE_SIZE_BP 0 | ||
157 | #define HW_DCP_CSCOUTBUFPARAM__LINE_SIZE_BM 0xfff | ||
158 | #define HW_DCP_CSCOUTBUFPARAM__FIELD_SIZE_BP 12 | ||
159 | #define HW_DCP_CSCOUTBUFPARAM__FIELD_SIZE_BM 0xfff000 | ||
160 | |||
161 | #define HW_DCP_CSCINBUFPARAM (*(volatile uint32_t *)(HW_DCP_BASE + 0x330)) | ||
162 | #define HW_DCP_CSCINBUFPARAM__LINE_SIZE_BP 0 | ||
163 | #define HW_DCP_CSCINBUFPARAM__LINE_SIZE_BM 0xfff | ||
164 | |||
165 | #define HW_DCP_CSCRGB (*(volatile uint32_t *)(HW_DCP_BASE + 0x340)) | ||
166 | |||
167 | #define HW_DCP_CSCLUMA (*(volatile uint32_t *)(HW_DCP_BASE + 0x350)) | ||
168 | |||
169 | #define HW_DCP_CSCCHROMAU (*(volatile uint32_t *)(HW_DCP_BASE + 0x360)) | ||
170 | |||
171 | #define HW_DCP_CSCCHROMAV (*(volatile uint32_t *)(HW_DCP_BASE + 0x370)) | ||
172 | |||
173 | #define HW_DCP_CSCCOEFF0 (*(volatile uint32_t *)(HW_DCP_BASE + 0x380)) | ||
174 | #define HW_DCP_CSCCOEFF0__Y_OFFSET_BP 0 | ||
175 | #define HW_DCP_CSCCOEFF0__Y_OFFSET_BM 0xff | ||
176 | #define HW_DCP_CSCCOEFF0__UV_OFFSET_BP 8 | ||
177 | #define HW_DCP_CSCCOEFF0__UV_OFFSET_BM 0xff00 | ||
178 | #define HW_DCP_CSCCOEFF0__C0_BP 16 | ||
179 | #define HW_DCP_CSCCOEFF0__C0_BM 0x3ff0000 | ||
180 | |||
181 | #define HW_DCP_CSCCOEFF1 (*(volatile uint32_t *)(HW_DCP_BASE + 0x390)) | ||
182 | #define HW_DCP_CSCCOEFF1__C4_BP 0 | ||
183 | #define HW_DCP_CSCCOEFF1__C4_BM 0x3ff | ||
184 | #define HW_DCP_CSCCOEFF1__C1_BP 16 | ||
185 | #define HW_DCP_CSCCOEFF1__C1_BM 0x3ff0000 | ||
186 | |||
187 | #define HW_DCP_CSCCOEFF2 (*(volatile uint32_t *)(HW_DCP_BASE + 0x3a0)) | ||
188 | #define HW_DCP_CSCCOEFF2__C3_BP 0 | ||
189 | #define HW_DCP_CSCCOEFF2__C3_BM 0x3ff | ||
190 | #define HW_DCP_CSCCOEFF2__C2_BP 16 | ||
191 | #define HW_DCP_CSCCOEFF2__C2_BM 0x3ff0000 | ||
192 | |||
193 | #define HW_DCP_CSCCLIP (*(volatile uint32_t *)(HW_DCP_BASE + 0x3b0)) | ||
194 | #define HW_DCP_CSCCLIP__WIDTH_BP 0 | ||
195 | #define HW_DCP_CSCCLIP__WIDTH_BM 0xfff | ||
196 | #define HW_DCP_CSCCLIP__HEIGHT_BP 12 | ||
197 | #define HW_DCP_CSCCLIP__HEIGHT_BM 0xfff000 | ||
198 | |||
199 | #define HW_DCP_CSCXSCALE (*(volatile uint32_t *)(HW_DCP_BASE + 0x3c0)) | ||
200 | #define HW_DCP_CSCXSCALE__WIDTH_BP 0 | ||
201 | #define HW_DCP_CSCXSCALE__WIDTH_BM 0xfff | ||
202 | #define HW_DCP_CSCXSCALE__FRAC_BP 12 | ||
203 | #define HW_DCP_CSCXSCALE__FRAC_BM 0xfff000 | ||
204 | #define HW_DCP_CSCXSCALE__INT_BP 24 | ||
205 | #define HW_DCP_CSCXSCALE__INT_BM 0x3000000 | ||
206 | |||
207 | #define HW_DCP_CSCYSCALE (*(volatile uint32_t *)(HW_DCP_BASE + 0x3d0)) | ||
208 | #define HW_DCP_CSCYSCALE__WIDTH_BP 0 | ||
209 | #define HW_DCP_CSCYSCALE__WIDTH_BM 0xfff | ||
210 | #define HW_DCP_CSCYSCALE__FRAC_BP 12 | ||
211 | #define HW_DCP_CSCYSCALE__FRAC_BM 0xfff000 | ||
212 | #define HW_DCP_CSCYSCALE__INT_BP 24 | ||
213 | #define HW_DCP_CSCYSCALE__INT_BM 0x3000000 | ||
214 | |||
215 | #define HW_DCP_PAGETABLE (*(volatile uint32_t *)(HW_DCP_BASE + 0x420)) | ||
216 | #define HW_DCP_PAGETABLE__ENABLE (1 << 0) | ||
217 | #define HW_DCP_PAGETABLE__FLUSH (1 << 1) | ||
218 | #define HW_DCP_PAGETABLE__BASE_BP 2 | ||
219 | #define HW_DCP_PAGETABLE__BASE_BM 0xfffffffc | ||
220 | |||
221 | struct imx233_dcp_packet_t | ||
222 | { | ||
223 | uint32_t next; | ||
224 | uint32_t ctrl0; | ||
225 | uint32_t ctrl1; | ||
226 | uint32_t src; | ||
227 | uint32_t dst; | ||
228 | uint32_t size; | ||
229 | uint32_t payload; | ||
230 | uint32_t status; | ||
231 | } __attribute__((packed)); | ||
232 | |||
233 | #define HW_DCP_CTRL0__INTERRUPT_ENABLE (1 << 0) | ||
234 | #define HW_DCP_CTRL0__DECR_SEMAPHORE (1 << 1) | ||
235 | #define HW_DCP_CTRL0__CHAIN (1 << 2) | ||
236 | #define HW_DCP_CTRL0__CHAIN_CONTINUOUS (1 << 3) | ||
237 | #define HW_DCP_CTRL0__ENABLE_MEMCOPY (1 << 4) | ||
238 | #define HW_DCP_CTRL0__ENABLE_CIPHER (1 << 5) | ||
239 | #define HW_DCP_CTRL0__ENABLE_HASH (1 << 6) | ||
240 | #define HW_DCP_CTRL0__ENABLE_BLIT (1 << 7) | ||
241 | #define HW_DCP_CTRL0__CIPHER_ENCRYPT (1 << 8) | ||
242 | #define HW_DCP_CTRL0__CIPHER_INIT (1 << 9) | ||
243 | #define HW_DCP_CTRL0__OTP_KEY (1 << 10) | ||
244 | #define HW_DCP_CTRL0__PAYLOAD_KEY (1 << 11) | ||
245 | #define HW_DCP_CTRL0__HASH_INIT (1 << 12) | ||
246 | #define HW_DCP_CTRL0__HASH_TERM (1 << 13) | ||
247 | #define HW_DCP_CTRL0__HASH_CHECK (1 << 14) | ||
248 | #define HW_DCP_CTRL0__HASH_OUTPUT (1 << 15) | ||
249 | #define HW_DCP_CTRL0__CONSTANT_FILL (1 << 16) | ||
250 | #define HW_DCP_CTRL0__TEST_SEMA_IRQ (1 << 17) | ||
251 | #define HW_DCP_CTRL0__KEY_BYTESWAP (1 << 18) | ||
252 | #define HW_DCP_CTRL0__KEY_WORDSWAP (1 << 19) | ||
253 | #define HW_DCP_CTRL0__INPUT_BYTESWAP (1 << 20) | ||
254 | #define HW_DCP_CTRL0__INPUT_WORDSWAP (1 << 21) | ||
255 | #define HW_DCP_CTRL0__OUTPUT_BYTESWAP (1 << 22) | ||
256 | #define HW_DCP_CTRL0__OUTPUT_WORDSWAP (1 << 23) | ||
257 | #define HW_DCP_CTRL0__TAG_BP 24 | ||
258 | #define HW_DCP_CTRL0__TAG_BM (0xff << 24) | ||
259 | |||
260 | #define HW_DCP_CTRL1__CIPHER_SELECT_BP 0 | ||
261 | #define HW_DCP_CTRL1__CIPHER_SELECT_BM 0xf | ||
262 | #define HW_DCP_CTRL1__CIPHER_MODE_BP 4 | ||
263 | #define HW_DCP_CTRL1__CIPHER_MODE_BM 0xf0 | ||
264 | #define HW_DCP_CTRL1__KEY_SELECT_BP 8 | ||
265 | #define HW_DCP_CTRL1__KEY_SELECT_BM 0xff00 | ||
266 | #define HW_DCP_CTRL1__FRAMEBUFFER_LENGTH_BP 0 | ||
267 | #define HW_DCP_CTRL1__FRAMEBUFFER_LENGTH_BM 0xffff | ||
268 | #define HW_DCP_CTRL1__HASH_SELECT_BP 16 | ||
269 | #define HW_DCP_CTRL1__HASH_SELECT_BM 0xf0000 | ||
270 | #define HW_DCP_CTRL1__CIPHER_CONFIG_BP 24 | ||
271 | #define HW_DCP_CTRL1__CIPHER_CONFIG_BM (0xff << 24) | ||
272 | |||
273 | #define HW_DCP_SIZE__BLIT_WIDTH_BP 0 | ||
274 | #define HW_DCP_SIZE__BLIT_WIDTH_BM 0xffff | ||
275 | #define HW_DCP_SIZE__NUMBER_LINES_BP 16 | ||
276 | #define HW_DCP_SIZE__NUMBER_LINES_BM 0xffff0000 | ||
277 | |||
278 | #define HW_DCP_STATUS__COMPLETE (1 << 0) | ||
279 | #define HW_DCP_STATUS__HASH_MISMATCH (1 << 1) | ||
280 | #define HW_DCP_STATUS__ERROR_SETUP (1 << 2) | ||
281 | #define HW_DCP_STATUS__ERROR_PACKET (1 << 3) | ||
282 | #define HW_DCP_STATUS__ERROR_SRC (1 << 4) | ||
283 | #define HW_DCP_STATUS__ERROR_DST (1 << 5) | ||
284 | #define HW_DCP_STATUS__ERROR_CODE_BP 16 | ||
285 | #define HW_DCP_STATUS__ERROR_CODE_BM (0xff << 16) | ||
286 | #define HW_DCP_STATUS__TAG_BP 24 | ||
287 | #define HW_DCP_STATUS__TAG_BM (0xff << 24) | ||
288 | |||
289 | struct imx233_dcp_channel_info_t | ||
290 | { | ||
291 | bool irq; | ||
292 | bool irq_en; | ||
293 | bool enable; | ||
294 | bool high_priority; | ||
295 | bool ready; | ||
296 | int sema; | ||
297 | uint32_t cmdptr; | ||
298 | }; | ||
299 | |||
300 | struct imx233_dcp_csc_info_t | ||
301 | { | ||
302 | bool irq; | ||
303 | bool irq_en; | ||
304 | bool enable; | ||
305 | int priority; | ||
306 | }; | ||
307 | |||
308 | struct imx233_dcp_info_t | ||
309 | { | ||
310 | /* capabilities */ | ||
311 | bool has_crypto; | ||
312 | bool has_csc; | ||
313 | int num_keys; | ||
314 | int num_channels; | ||
315 | unsigned ciphers; | ||
316 | unsigned hashs; | ||
317 | /* global state */ | ||
318 | bool context_switching; | ||
319 | bool context_caching; | ||
320 | bool gather_writes; | ||
321 | bool otp_key_ready; | ||
322 | bool ch0_merged; | ||
323 | /* channel state */ | ||
324 | struct imx233_dcp_channel_info_t channel[HW_DCP_NUM_CHANNELS]; | ||
325 | /* csc state */ | ||
326 | struct imx233_dcp_csc_info_t csc; | ||
327 | }; | ||
328 | |||
329 | #define DCP_INFO_CAPABILITIES (1 << 0) | ||
330 | #define DCP_INFO_GLOBAL_STATE (1 << 1) | ||
331 | #define DCP_INFO_CHANNELS (1 << 2) | ||
332 | #define DCP_INFO_CSC (1 << 3) | ||
333 | #define DCP_INFO_ALL 0xf | ||
334 | |||
335 | enum imx233_dcp_error_t | ||
336 | { | ||
337 | DCP_SUCCESS = 0, | ||
338 | DCP_TIMEOUT = -1, | ||
339 | DCP_ERROR_SETUP = -2, | ||
340 | DCP_ERROR_PACKET = -3, | ||
341 | DCP_ERROR_SRC = -4, | ||
342 | DCP_ERROR_DST = -5, | ||
343 | DCP_ERROR_CHAIN_IS_0 = -6, | ||
344 | DCP_ERROR_NO_CHAIN = -7, | ||
345 | DCP_ERROR_CONTEXT = -8, | ||
346 | DCP_ERROR_PAYLOAD = -9, | ||
347 | DCP_ERROR_MODE = -10, | ||
348 | DCP_ERROR = -11 | ||
349 | }; | ||
350 | |||
351 | void imx233_dcp_init(void); | ||
352 | // return OBJ_WAIT_TIMEOUT on failure | ||
353 | int imx233_dcp_acquire_channel(int timeout); | ||
354 | void imx233_dcp_release_channel(int chan); | ||
355 | // doesn't check that channel is in use! | ||
356 | void imx233_dcp_reserve_channel(int channel); | ||
357 | |||
358 | enum imx233_dcp_error_t imx233_dcp_memcpy_ex(int channel, void *src, void *dst, size_t len); | ||
359 | enum imx233_dcp_error_t imx233_dcp_memcpy(void *src, void *dst, size_t len, int tmo); | ||
360 | |||
361 | struct imx233_dcp_info_t imx233_dcp_get_info(unsigned flags); | ||
362 | |||
363 | #endif // __DMA_IMX233_H__ | ||