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Diffstat (limited to 'firmware/target/arm/imx233/clkctrl-imx233.h')
-rw-r--r--firmware/target/arm/imx233/clkctrl-imx233.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/clkctrl-imx233.h b/firmware/target/arm/imx233/clkctrl-imx233.h
index 8a52620f7e..ae2e0465a0 100644
--- a/firmware/target/arm/imx233/clkctrl-imx233.h
+++ b/firmware/target/arm/imx233/clkctrl-imx233.h
@@ -52,6 +52,7 @@
52#define HW_CLKCTRL_HBUS__SLOW_DIV_BM (0x7 << 16) 52#define HW_CLKCTRL_HBUS__SLOW_DIV_BM (0x7 << 16)
53#define HW_CLKCTRL_HBUS__AUTO_SLOW_MODE (1 << 20) 53#define HW_CLKCTRL_HBUS__AUTO_SLOW_MODE (1 << 20)
54 54
55/* warning: this register doesn't have a CLR/SET variant ! */
55#define HW_CLKCTRL_XBUS (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x40)) 56#define HW_CLKCTRL_XBUS (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x40))
56#define HW_CLKCTRL_XBUS__DIV_BP 0 57#define HW_CLKCTRL_XBUS__DIV_BP 0
57#define HW_CLKCTRL_XBUS__DIV_BM 0x3ff 58#define HW_CLKCTRL_XBUS__DIV_BM 0x3ff
@@ -62,14 +63,17 @@
62#define HW_CLKCTRL_XTAL__DRI_CLK24M_GATE (1 << 28) 63#define HW_CLKCTRL_XTAL__DRI_CLK24M_GATE (1 << 28)
63#define HW_CLKCTRL_XTAL__FILT_CLK24M_GATE (1 << 30) 64#define HW_CLKCTRL_XTAL__FILT_CLK24M_GATE (1 << 30)
64 65
66/* warning: this register doesn't have a CLR/SET variant ! */
65#define HW_CLKCTRL_PIX (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x60)) 67#define HW_CLKCTRL_PIX (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x60))
66#define HW_CLKCTRL_PIX__DIV_BP 0 68#define HW_CLKCTRL_PIX__DIV_BP 0
67#define HW_CLKCTRL_PIX__DIV_BM 0xfff 69#define HW_CLKCTRL_PIX__DIV_BM 0xfff
68 70
71/* warning: this register doesn't have a CLR/SET variant ! */
69#define HW_CLKCTRL_SSP (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x70)) 72#define HW_CLKCTRL_SSP (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x70))
70#define HW_CLKCTRL_SSP__DIV_BP 0 73#define HW_CLKCTRL_SSP__DIV_BP 0
71#define HW_CLKCTRL_SSP__DIV_BM 0x1ff 74#define HW_CLKCTRL_SSP__DIV_BM 0x1ff
72 75
76/* warning: this register doesn't have a CLR/SET variant ! */
73#define HW_CLKCTRL_EMI (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xa0)) 77#define HW_CLKCTRL_EMI (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xa0))
74#define HW_CLKCTRL_EMI__DIV_EMI_BP 0 78#define HW_CLKCTRL_EMI__DIV_EMI_BP 0
75#define HW_CLKCTRL_EMI__DIV_EMI_BM 0x3f 79#define HW_CLKCTRL_EMI__DIV_EMI_BM 0x3f
@@ -94,6 +98,7 @@
94#define HW_CLKCTRL_FRAC_XX__XX_STABLE (1 << 6) 98#define HW_CLKCTRL_FRAC_XX__XX_STABLE (1 << 6)
95#define HW_CLKCTRL_FRAC_XX__CLKGATEXX (1 << 7) 99#define HW_CLKCTRL_FRAC_XX__CLKGATEXX (1 << 7)
96 100
101/* warning: this register doesn't have a CLR/SET variant ! */
97#define HW_CLKCTRL_RESET (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x120)) 102#define HW_CLKCTRL_RESET (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x120))
98#define HW_CLKCTRL_RESET_CHIP 0x2 103#define HW_CLKCTRL_RESET_CHIP 0x2
99#define HW_CLKCTRL_RESET_DIG 0x1 104#define HW_CLKCTRL_RESET_DIG 0x1