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Diffstat (limited to 'firmware/target/arm/crt0-pp-bl.S')
-rw-r--r-- | firmware/target/arm/crt0-pp-bl.S | 179 |
1 files changed, 179 insertions, 0 deletions
diff --git a/firmware/target/arm/crt0-pp-bl.S b/firmware/target/arm/crt0-pp-bl.S new file mode 100644 index 0000000000..4f50cac699 --- /dev/null +++ b/firmware/target/arm/crt0-pp-bl.S | |||
@@ -0,0 +1,179 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | #include "config.h" | ||
20 | #include "cpu.h" | ||
21 | |||
22 | .section .init.text,"ax",%progbits | ||
23 | |||
24 | .global start | ||
25 | start: | ||
26 | |||
27 | /* PortalPlayer bootloader and startup code based on startup.s from the iPodLinux | ||
28 | * loader | ||
29 | * | ||
30 | * Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org) | ||
31 | * Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org> | ||
32 | * | ||
33 | */ | ||
34 | #if CONFIG_CPU == PP5002 | ||
35 | .equ PROC_ID, 0xc4000000 | ||
36 | .equ COP_CTRL, 0xcf004058 | ||
37 | .equ COP_STATUS, 0xcf004050 | ||
38 | .equ IIS_CONFIG, 0xc0002500 | ||
39 | .equ SLEEP, 0xca | ||
40 | .equ WAKE, 0xce | ||
41 | .equ SLEEPING, 0x4000 | ||
42 | #else | ||
43 | .equ PROC_ID, 0x60000000 | ||
44 | .equ COP_CTRL, 0x60007004 | ||
45 | .equ COP_STATUS, 0x60007004 | ||
46 | .equ IIS_CONFIG, 0x70002800 | ||
47 | .equ SLEEP, 0x80000000 | ||
48 | .equ WAKE, 0x0 | ||
49 | .equ SLEEPING, 0x80000000 | ||
50 | .equ CACHE_CTRL, 0x6000c000 | ||
51 | #endif | ||
52 | |||
53 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */ | ||
54 | |||
55 | /* 1 - Copy the bootloader to IRAM */ | ||
56 | /* get the high part of our execute address */ | ||
57 | ldr r7, =0xffffff00 | ||
58 | and r4, pc, r7 | ||
59 | |||
60 | /* Copy bootloader to safe area - 0x40000000 (IRAM) */ | ||
61 | mov r5, #0x40000000 | ||
62 | ldr r6, = _dataend | ||
63 | 1: | ||
64 | cmp r5, r6 | ||
65 | ldrcc r2, [r4], #4 | ||
66 | strcc r2, [r5], #4 | ||
67 | bcc 1b | ||
68 | |||
69 | #ifndef IPOD_ARCH | ||
70 | /* For builds on targets with mi4 firmware, scramble writes data to | ||
71 | 0xe0-0xeb, so jump past that.*/ | ||
72 | b pad_skip | ||
73 | |||
74 | .space 60*4 | ||
75 | |||
76 | pad_skip: | ||
77 | #endif | ||
78 | |||
79 | |||
80 | /* 2 - Jump both CPU and COP there */ | ||
81 | ldr pc, =start_loc /* jump to the relocated start_loc: */ | ||
82 | |||
83 | start_loc: | ||
84 | |||
85 | /* Find out which processor we are */ | ||
86 | ldr r0, =PROC_ID | ||
87 | ldr r0, [r0] | ||
88 | and r0, r0, #0xff | ||
89 | cmp r0, #0x55 | ||
90 | beq cpu | ||
91 | |||
92 | /* put us (co-processor) to sleep */ | ||
93 | ldr r4, =COP_CTRL | ||
94 | mov r3, #SLEEP | ||
95 | str r3, [r4] | ||
96 | ldr pc, =cop_wake_start | ||
97 | |||
98 | cop_wake_start: | ||
99 | #if CONFIG_CPU != PP5002 | ||
100 | /* COP: Invalidate cache */ | ||
101 | ldr r0, =0xf000f044 | ||
102 | ldr r1, [r0] | ||
103 | orr r1, r1, #0x6 | ||
104 | str r1, [r0] | ||
105 | |||
106 | ldr r0, =CACHE_CTRL | ||
107 | 1: | ||
108 | ldr r1, [r0] | ||
109 | tst r1, #0x8000 | ||
110 | bne 1b | ||
111 | #endif | ||
112 | |||
113 | ldr r0, =startup_loc | ||
114 | ldr pc, [r0] | ||
115 | |||
116 | cpu: | ||
117 | /* Wait for COP to be sleeping */ | ||
118 | ldr r4, =COP_STATUS | ||
119 | 1: | ||
120 | ldr r3, [r4] | ||
121 | ands r3, r3, #SLEEPING | ||
122 | beq 1b | ||
123 | |||
124 | /* Initialise bss section to zero */ | ||
125 | ldr r2, =_edata | ||
126 | ldr r3, =_end | ||
127 | mov r4, #0 | ||
128 | 1: | ||
129 | cmp r3, r2 | ||
130 | strhi r4, [r2], #4 | ||
131 | bhi 1b | ||
132 | |||
133 | /* Set up some stack and munge it with 0xdeadbeef */ | ||
134 | ldr sp, =stackend | ||
135 | mov r3, sp | ||
136 | ldr r2, =stackbegin | ||
137 | ldr r4, =0xdeadbeef | ||
138 | 1: | ||
139 | cmp r3, r2 | ||
140 | strhi r4, [r2], #4 | ||
141 | bhi 1b | ||
142 | |||
143 | /* execute the loader - this will load an image to 0x10000000 */ | ||
144 | bl main | ||
145 | |||
146 | ldr r1, =startup_loc | ||
147 | str r0, [r1] | ||
148 | |||
149 | #if CONFIG_CPU != PP5002 | ||
150 | /* Flush cache */ | ||
151 | ldr r3, =0xf000f044 | ||
152 | ldr r4, [r3] | ||
153 | orr r4, r4, #0x2 | ||
154 | str r4, [r3] | ||
155 | |||
156 | ldr r3, =CACHE_CTRL | ||
157 | 1: | ||
158 | ldr r4, [r3] | ||
159 | tst r4, #0x8000 | ||
160 | bne 1b | ||
161 | #endif | ||
162 | |||
163 | /* Wake up the coprocessor before executing the firmware */ | ||
164 | ldr r4, =COP_CTRL | ||
165 | mov r3, #WAKE | ||
166 | str r3, [r4] | ||
167 | |||
168 | mov pc, r0 | ||
169 | |||
170 | startup_loc: | ||
171 | .word 0x0 | ||
172 | |||
173 | #ifdef IPOD_ARCH | ||
174 | .align 8 /* starts at 0x100 */ | ||
175 | .global boot_table | ||
176 | boot_table: | ||
177 | /* here comes the boot table, don't move its offset */ | ||
178 | .space 400 | ||
179 | #endif | ||