diff options
Diffstat (limited to 'firmware/target/arm/at91sam/lyre_proto1/system-lyre_proto1.c')
-rw-r--r-- | firmware/target/arm/at91sam/lyre_proto1/system-lyre_proto1.c | 150 |
1 files changed, 150 insertions, 0 deletions
diff --git a/firmware/target/arm/at91sam/lyre_proto1/system-lyre_proto1.c b/firmware/target/arm/at91sam/lyre_proto1/system-lyre_proto1.c new file mode 100644 index 0000000000..e91ef7a918 --- /dev/null +++ b/firmware/target/arm/at91sam/lyre_proto1/system-lyre_proto1.c | |||
@@ -0,0 +1,150 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * | ||
9 | * | ||
10 | * Copyright (C) 2009 by Jorge Pinto | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | /* Include Standard files */ | ||
23 | #include "at91sam9260.h" | ||
24 | #include "debug-target.h" | ||
25 | #include "config.h" | ||
26 | |||
27 | /*----------------------------------------------------------------------------- | ||
28 | * Function Name : default_spurious_handler | ||
29 | * Object : default handler for spurious interrupt | ||
30 | *---------------------------------------------------------------------------*/ | ||
31 | void default_spurious_handler(void) | ||
32 | { | ||
33 | while (1); | ||
34 | } | ||
35 | |||
36 | /*----------------------------------------------------------------------------- | ||
37 | * Function Name : default_fiq_handler | ||
38 | * Object : default handler for fast interrupt | ||
39 | *---------------------------------------------------------------------------*/ | ||
40 | void default_fiq_handler(void) | ||
41 | { | ||
42 | while (1); | ||
43 | } | ||
44 | |||
45 | /*----------------------------------------------------------------------------- | ||
46 | * Function Name : default_irq_handler | ||
47 | * Object : default handler for irq | ||
48 | *---------------------------------------------------------------------------*/ | ||
49 | void default_irq_handler(void) | ||
50 | { | ||
51 | #if defined(BOOTLOADER) | ||
52 | while (1); | ||
53 | #endif | ||
54 | } | ||
55 | |||
56 | /*----------------------------------------------------------------------------- | ||
57 | * Function Name : lowlevel_init | ||
58 | * Object : This function performs very low level HW initialization | ||
59 | * this function can use a Stack, depending the compilation | ||
60 | * optimization mode | ||
61 | *---------------------------------------------------------------------------*/ | ||
62 | void lowlevel_init(void) | ||
63 | { | ||
64 | unsigned char i = 0; | ||
65 | |||
66 | /* void default_fiq_handler(void) | ||
67 | * Init PMC Step 1. Enable Main Oscillator | ||
68 | * Main Oscillator startup time is board specific: | ||
69 | * Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms | ||
70 | * (0x40 for AT91C_CKGR_OSCOUNT field) | ||
71 | */ | ||
72 | AT91C_PMC_MOR = (((AT91C_CKGR_OSCOUNT & (0x40 << 8)) | AT91C_CKGR_MOSCEN)); | ||
73 | /* Wait Main Oscillator stabilization */ | ||
74 | while (!(AT91C_PMC_SR & AT91C_PMC_MOSCS)); | ||
75 | |||
76 | /* Init PMC Step 2. | ||
77 | * Set PLLA to 198,608MHz | ||
78 | * PLL Startup time depends on PLL RC filter: worst case is choosen. | ||
79 | * | ||
80 | * Crystal frequency = 18.432MHz; PLLA = (18.432 * 96) / 9 = 198,608MHz. | ||
81 | */ | ||
82 | |||
83 | AT91C_PMC_PLLAR = (1 << 29) | | ||
84 | (0x60 << 16) | /* MULA = 96 */ | ||
85 | (0x2 << 14) | | ||
86 | (0x3f << 8) | | ||
87 | (0x09); /* DIVA = 9 */ | ||
88 | |||
89 | /* Wait for PLLA stabilization */ | ||
90 | while (!(AT91C_PMC_SR & AT91C_PMC_LOCKA)); | ||
91 | /* Wait until the master clock is established for the case we already */ | ||
92 | /* turn on the PLLA */ | ||
93 | while (!(AT91C_PMC_SR & AT91C_PMC_MCKRDY)); | ||
94 | |||
95 | /* Init PMC Step 3. | ||
96 | * Processor Clock = 198,608MHz (PLLA); Master clock = | ||
97 | * (198,608MHz (PLLA))/2 = 98,304MHz. | ||
98 | * The PMC_MCKR register must not be programmed in a single write operation | ||
99 | * (see. Product Errata Sheet) | ||
100 | */ | ||
101 | AT91C_PMC_MCKR = AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2; | ||
102 | /* Wait until the master clock is established */ | ||
103 | while (!(AT91C_PMC_SR & AT91C_PMC_MCKRDY)); | ||
104 | |||
105 | AT91C_PMC_MCKR |= AT91C_PMC_CSS_PLLA_CLK; | ||
106 | /* Wait until the master clock is established */ | ||
107 | while (!(AT91C_PMC_SR & AT91C_PMC_MCKRDY)); | ||
108 | |||
109 | /* Reset AIC: assign default handler for each interrupt source | ||
110 | */ | ||
111 | |||
112 | /* Disable the interrupt on the interrupt controller */ | ||
113 | AT91C_AIC_IDCR = (1 << AT91C_ID_SYS); | ||
114 | |||
115 | /* Assign default handler for each IRQ source */ | ||
116 | AT91C_AIC_SVR(AT91C_ID_FIQ) = (int) default_fiq_handler; | ||
117 | for (i = 1; i < 31; i++) | ||
118 | { | ||
119 | AT91C_AIC_SVR(i) = (int) default_irq_handler; | ||
120 | } | ||
121 | AT91C_AIC_SPU = (unsigned int) default_spurious_handler; | ||
122 | |||
123 | /* Perform 8 IT acknoledge (write any value in EOICR) */ | ||
124 | |||
125 | /* The End of Interrupt Command Register (AIC_EOICR) must be written in order | ||
126 | to indicate to the AIC that the current interrupt is finished. This causes the | ||
127 | current level to be popped from the stack, restoring the previous current level | ||
128 | if one exists on the stack. If another interrupt is pending, with lower or | ||
129 | equal priority than the old current level but with higher priority than the new | ||
130 | current level, the nIRQ line is re-asserted, but the interrupt sequence does | ||
131 | not immediately start because the āIā bit is set in the core. | ||
132 | SPSR_irq is restored. Finally, the saved value of the link register is restored | ||
133 | directly into the PC. This has the effect of returning from the interrupt to | ||
134 | whatever was being executed before, and of loading the CPSR with the stored | ||
135 | SPSR, masking or unmasking the interrupts depending on the state saved in | ||
136 | SPSR_irq. */ | ||
137 | for (i = 0; i < 8 ; i++) | ||
138 | { | ||
139 | AT91C_AIC_EOICR = 0; | ||
140 | } | ||
141 | |||
142 | /* Enable the interrupt on the interrupt controller */ | ||
143 | AT91C_AIC_IECR = (1 << AT91C_ID_SYS); | ||
144 | |||
145 | /* Disable Watchdog */ | ||
146 | AT91C_WDTC_WDMR = AT91C_WDTC_WDDIS; | ||
147 | |||
148 | /* Remap */ | ||
149 | AT91C_MATRIX_MRCR = AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D; | ||
150 | } | ||