diff options
Diffstat (limited to 'firmware/target/arm/as3525')
-rw-r--r-- | firmware/target/arm/as3525/usb-drv-as3525v2.c | 150 | ||||
-rw-r--r-- | firmware/target/arm/as3525/usb-drv-as3525v2.h | 2 |
2 files changed, 91 insertions, 61 deletions
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.c b/firmware/target/arm/as3525/usb-drv-as3525v2.c index a1ea7e30ab..2dfc69b580 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.c +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.c | |||
@@ -36,6 +36,8 @@ | |||
36 | #include "usb-drv-as3525v2.h" | 36 | #include "usb-drv-as3525v2.h" |
37 | #include "usb_core.h" | 37 | #include "usb_core.h" |
38 | 38 | ||
39 | #define panicf(...) ({logf(__VA_ARGS__); DCTL |= DCTL_sftdiscon; /* disconnect */}) | ||
40 | |||
39 | static int __in_ep_list[NUM_IN_EP] = {IN_EP_LIST}; | 41 | static int __in_ep_list[NUM_IN_EP] = {IN_EP_LIST}; |
40 | static int __out_ep_list[NUM_OUT_EP] = {OUT_EP_LIST}; | 42 | static int __out_ep_list[NUM_OUT_EP] = {OUT_EP_LIST}; |
41 | static int __in_ep_list_ep0[NUM_IN_EP + 1] = {0, IN_EP_LIST}; | 43 | static int __in_ep_list_ep0[NUM_IN_EP + 1] = {0, IN_EP_LIST}; |
@@ -77,6 +79,7 @@ struct usb_endpoint | |||
77 | bool busy; /* true is a transfer is pending */ | 79 | bool busy; /* true is a transfer is pending */ |
78 | int status; /* completion status (0 for success) */ | 80 | int status; /* completion status (0 for success) */ |
79 | struct wakeup complete; /* wait object */ | 81 | struct wakeup complete; /* wait object */ |
82 | void *buffer; /* buffer address */ | ||
80 | }; | 83 | }; |
81 | 84 | ||
82 | /* state of EP0 (to correctly schedule setup packet enqueing) */ | 85 | /* state of EP0 (to correctly schedule setup packet enqueing) */ |
@@ -108,7 +111,7 @@ void usb_attach(void) | |||
108 | usb_enable(true); | 111 | usb_enable(true); |
109 | } | 112 | } |
110 | 113 | ||
111 | static void usb_delay(void) | 114 | static inline void usb_delay(void) |
112 | { | 115 | { |
113 | int i = 0; | 116 | int i = 0; |
114 | while(i < 0x300) | 117 | while(i < 0x300) |
@@ -126,7 +129,7 @@ static void as3525v2_connect(void) | |||
126 | usb_delay(); | 129 | usb_delay(); |
127 | /* 2) enable usb phy clock */ | 130 | /* 2) enable usb phy clock */ |
128 | /* PHY clock */ | 131 | /* PHY clock */ |
129 | CGU_USB = 1<<5 /* enable */ | 132 | CGU_USB = 1<<5 /* enable */ |
130 | | (CLK_DIV(AS3525_PLLA_FREQ, 60000000)) << 2 | 133 | | (CLK_DIV(AS3525_PLLA_FREQ, 60000000)) << 2 |
131 | | 1; /* source = PLLA */ | 134 | | 1; /* source = PLLA */ |
132 | usb_delay(); | 135 | usb_delay(); |
@@ -177,10 +180,13 @@ static void enable_device_interrupts(void) | |||
177 | GOTGINT = 0xffffffff; | 180 | GOTGINT = 0xffffffff; |
178 | /* Enable interrupts */ | 181 | /* Enable interrupts */ |
179 | GINTMSK = GINTMSK_usbreset | 182 | GINTMSK = GINTMSK_usbreset |
180 | | GINTMSK_enumdone | 183 | | GINTMSK_enumdone |
181 | | GINTMSK_inepintr | 184 | | GINTMSK_inepintr |
182 | | GINTMSK_outepintr | 185 | | GINTMSK_outepintr |
183 | | GINTMSK_disconnect; | 186 | | GINTMSK_disconnect |
187 | | GINTMSK_usbsuspend | ||
188 | | GINTMSK_wkupintr | ||
189 | | GINTMSK_otgintr; | ||
184 | } | 190 | } |
185 | 191 | ||
186 | static void flush_tx_fifos(int nums) | 192 | static void flush_tx_fifos(int nums) |
@@ -197,12 +203,27 @@ static void flush_tx_fifos(int nums) | |||
197 | udelay(1); | 203 | udelay(1); |
198 | } | 204 | } |
199 | 205 | ||
206 | static void flush_rx_fifo(void) | ||
207 | { | ||
208 | unsigned int i = 0; | ||
209 | |||
210 | GRSTCTL = GRSTCTL_rxfflsh_flush; | ||
211 | while(GRSTCTL & GRSTCTL_rxfflsh_flush && i < 0x300) | ||
212 | i++; | ||
213 | if(GRSTCTL & GRSTCTL_rxfflsh_flush) | ||
214 | panicf("usb-drv: hang of flush rx fifo"); | ||
215 | /* wait 3 phy clocks */ | ||
216 | udelay(1); | ||
217 | } | ||
218 | |||
200 | static void prepare_setup_ep0(void) | 219 | static void prepare_setup_ep0(void) |
201 | { | 220 | { |
202 | logf("usb-drv: prepare EP0"); | 221 | logf("usb-drv: prepare EP0"); |
203 | /* setup DMA */ | 222 | /* setup DMA */ |
204 | clean_dcache_range((void*)&ep0_setup_pkt, sizeof ep0_setup_pkt); /* force write back */ | 223 | //memset(&ep0_setup_pkt, 0, sizeof ep0_setup_pkt); |
205 | DOEPDMA(0) = (unsigned long)&ep0_setup_pkt; /* virtual address=physical address */ | 224 | //clean_dcache_range((void*)&ep0_setup_pkt, sizeof ep0_setup_pkt); /* force write back */ |
225 | clean_dcache(); | ||
226 | DOEPDMA(0) = (unsigned long)AS3525_PHYSICAL_ADDR(&ep0_setup_pkt); /* virtual address=physical address */ | ||
206 | 227 | ||
207 | /* Setup EP0 OUT with the following parameters: | 228 | /* Setup EP0 OUT with the following parameters: |
208 | * packet count = 1 | 229 | * packet count = 1 |
@@ -214,11 +235,8 @@ static void prepare_setup_ep0(void) | |||
214 | | 8; | 235 | | 8; |
215 | 236 | ||
216 | /* Enable endpoint, clear nak */ | 237 | /* Enable endpoint, clear nak */ |
217 | DOEPCTL(0) |= DEPCTL_epena | DEPCTL_cnak; | ||
218 | |||
219 | if(!(DOEPCTL(0) & DEPCTL_epena)) | ||
220 | panicf("usb-drv: failed to enable EP0 !"); | ||
221 | ep0_state = EP0_WAIT_SETUP; | 238 | ep0_state = EP0_WAIT_SETUP; |
239 | DOEPCTL(0) |= DEPCTL_epena | DEPCTL_cnak; | ||
222 | } | 240 | } |
223 | 241 | ||
224 | static void handle_ep0_complete(bool is_ack) | 242 | static void handle_ep0_complete(bool is_ack) |
@@ -259,7 +277,6 @@ static void handle_ep0_setup(void) | |||
259 | if(ep0_state != EP0_WAIT_SETUP) | 277 | if(ep0_state != EP0_WAIT_SETUP) |
260 | { | 278 | { |
261 | logf("usb-drv: EP0 SETUP while in state %d", ep0_state); | 279 | logf("usb-drv: EP0 SETUP while in state %d", ep0_state); |
262 | DCTL |= DCTL_sftdiscon; | ||
263 | return; | 280 | return; |
264 | } | 281 | } |
265 | /* determine is there is a data phase */ | 282 | /* determine is there is a data phase */ |
@@ -269,24 +286,38 @@ static void handle_ep0_setup(void) | |||
269 | else | 286 | else |
270 | /* yes: wait ack and data */ | 287 | /* yes: wait ack and data */ |
271 | ep0_state = EP0_WAIT_DATA_ACK; | 288 | ep0_state = EP0_WAIT_DATA_ACK; |
289 | logf("usb-drv: EP0 state updated to %d", ep0_state); | ||
272 | } | 290 | } |
273 | 291 | ||
274 | static void reset_endpoints(void) | 292 | static void reset_endpoints(void) |
275 | { | 293 | { |
276 | int i, ep; | 294 | int i, ep; |
277 | /* disable all endpoints except EP0 */ | 295 | /* disable all endpoints except EP0 */ |
278 | FOR_EACH_IN_EP(i, ep) | 296 | FOR_EACH_IN_EP_AND_EP0(i, ep) |
297 | { | ||
298 | endpoints[ep][DIR_IN].active = false; | ||
299 | endpoints[ep][DIR_IN].busy = false; | ||
300 | if(endpoints[ep][DIR_IN].wait) | ||
301 | wakeup_signal(&endpoints[ep][DIR_IN].complete); | ||
302 | endpoints[ep][DIR_IN].wait = false; | ||
279 | if(DIEPCTL(ep) & DEPCTL_epena) | 303 | if(DIEPCTL(ep) & DEPCTL_epena) |
280 | DIEPCTL(ep) = DEPCTL_epdis | DEPCTL_snak; | 304 | DIEPCTL(ep) = DEPCTL_epdis | DEPCTL_snak; |
281 | else | 305 | else |
282 | DIEPCTL(ep) = 0; | 306 | DIEPCTL(ep) = 0; |
307 | } | ||
283 | 308 | ||
284 | FOR_EACH_OUT_EP(i, ep) | 309 | FOR_EACH_OUT_EP_AND_EP0(i, ep) |
310 | { | ||
311 | endpoints[ep][DIR_OUT].active = false; | ||
312 | endpoints[ep][DIR_OUT].busy = false; | ||
313 | if(endpoints[ep][DIR_OUT].wait) | ||
314 | wakeup_signal(&endpoints[ep][DIR_OUT].complete); | ||
315 | endpoints[ep][DIR_OUT].wait = false; | ||
285 | if(DOEPCTL(ep) & DEPCTL_epena) | 316 | if(DOEPCTL(ep) & DEPCTL_epena) |
286 | DOEPCTL(ep) = DEPCTL_epdis | DEPCTL_snak; | 317 | DOEPCTL(ep) = DEPCTL_epdis | DEPCTL_snak; |
287 | else | 318 | else |
288 | DOEPCTL(ep) = 0; | 319 | DOEPCTL(ep) = 0; |
289 | 320 | } | |
290 | /* 64 bytes packet size, active endpoint */ | 321 | /* 64 bytes packet size, active endpoint */ |
291 | DOEPCTL(0) = (DEPCTL_MPS_64 << DEPCTL_mps_bitp) | DEPCTL_usbactep | DEPCTL_snak; | 322 | DOEPCTL(0) = (DEPCTL_MPS_64 << DEPCTL_mps_bitp) | DEPCTL_usbactep | DEPCTL_snak; |
292 | DIEPCTL(0) = (DEPCTL_MPS_64 << DEPCTL_mps_bitp) | DEPCTL_usbactep | DEPCTL_snak; | 323 | DIEPCTL(0) = (DEPCTL_MPS_64 << DEPCTL_mps_bitp) | DEPCTL_usbactep | DEPCTL_snak; |
@@ -325,7 +356,7 @@ static void core_dev_init(void) | |||
325 | /* Restart the phy clock */ | 356 | /* Restart the phy clock */ |
326 | PCGCCTL = 0; | 357 | PCGCCTL = 0; |
327 | /* Set phy speed : high speed */ | 358 | /* Set phy speed : high speed */ |
328 | DCFG = (DCFG & ~bitm(DCFG, devspd)) | DCFG_devspd_hs_phy_hs; | 359 | DCFG = (DCFG & ~bitm(DCFG, devspd)) | DCFG_devspd_hs_phy_fs; |
329 | 360 | ||
330 | /* Check hardware capabilities */ | 361 | /* Check hardware capabilities */ |
331 | if(extract(GHWCFG2, arch) != GHWCFG2_ARCH_INTERNAL_DMA) | 362 | if(extract(GHWCFG2, arch) != GHWCFG2_ARCH_INTERNAL_DMA) |
@@ -346,14 +377,6 @@ static void core_dev_init(void) | |||
346 | panicf("usb-drv: wrong data fifo size"); | 377 | panicf("usb-drv: wrong data fifo size"); |
347 | #endif /* USE_CUSTOM_FIFO_LAYOUT */ | 378 | #endif /* USE_CUSTOM_FIFO_LAYOUT */ |
348 | 379 | ||
349 | /* do some logging */ | ||
350 | /* | ||
351 | logf("hwcfg1: %08lx", GHWCFG1); | ||
352 | logf("hwcfg2: %08lx", GHWCFG2); | ||
353 | logf("hwcfg3: %08lx", GHWCFG3); | ||
354 | logf("hwcfg4: %08lx", GHWCFG4); | ||
355 | */ | ||
356 | |||
357 | if(USB_NUM_ENDPOINTS != extract(GHWCFG2, num_ep)) | 380 | if(USB_NUM_ENDPOINTS != extract(GHWCFG2, num_ep)) |
358 | panicf("usb-drv: wrong endpoint number"); | 381 | panicf("usb-drv: wrong endpoint number"); |
359 | 382 | ||
@@ -378,17 +401,6 @@ static void core_dev_init(void) | |||
378 | 401 | ||
379 | reset_endpoints(); | 402 | reset_endpoints(); |
380 | 403 | ||
381 | /* fixme: threshold tweaking only takes place if we use multiple tx fifos it seems */ | ||
382 | /* only dump them for now, leave threshold disabled */ | ||
383 | /* | ||
384 | logf("threshold control:"); | ||
385 | logf(" non_iso_thr_en: %d", (DTHRCTL & DTHRCTL_non_iso_thr_en) ? 1 : 0); | ||
386 | logf(" iso_thr_en: %d", (DTHRCTL & DTHRCTL_iso_thr_en) ? 1 : 0); | ||
387 | logf(" tx_thr_len: %lu", extract(DTHRCTL, tx_thr_len)); | ||
388 | logf(" rx_thr_en: %d", (DTHRCTL & DTHRCTL_rx_thr_en) ? 1 : 0); | ||
389 | logf(" rx_thr_len: %lu", extract(DTHRCTL, rx_thr_len)); | ||
390 | */ | ||
391 | |||
392 | /* enable USB interrupts */ | 404 | /* enable USB interrupts */ |
393 | enable_device_interrupts(); | 405 | enable_device_interrupts(); |
394 | } | 406 | } |
@@ -399,11 +411,12 @@ static void core_init(void) | |||
399 | DCTL |= DCTL_sftdiscon; | 411 | DCTL |= DCTL_sftdiscon; |
400 | /* Select UTMI+ 16 */ | 412 | /* Select UTMI+ 16 */ |
401 | GUSBCFG |= GUSBCFG_phy_if; | 413 | GUSBCFG |= GUSBCFG_phy_if; |
414 | GUSBCFG = (GUSBCFG & ~bitm(GUSBCFG, toutcal)) | 7 << GUSBCFG_toutcal_bitp; | ||
402 | 415 | ||
403 | /* fixme: the current code is for internal DMA only, the clip+ architecture | 416 | /* fixme: the current code is for internal DMA only, the clip+ architecture |
404 | * define the internal DMA model */ | 417 | * define the internal DMA model */ |
405 | /* Set burstlen and enable DMA*/ | 418 | /* Set burstlen and enable DMA*/ |
406 | GAHBCFG = (GAHBCFG_INT_DMA_BURST_INCR4 << GAHBCFG_hburstlen_bitp) | 419 | GAHBCFG = (GAHBCFG_INT_DMA_BURST_INCR << GAHBCFG_hburstlen_bitp) |
407 | | GAHBCFG_dma_enable; | 420 | | GAHBCFG_dma_enable; |
408 | /* Disable HNP and SRP, not sure it's useful because we already forced dev mode */ | 421 | /* Disable HNP and SRP, not sure it's useful because we already forced dev mode */ |
409 | GUSBCFG &= ~(GUSBCFG_srpcap | GUSBCFG_hnpcapp); | 422 | GUSBCFG &= ~(GUSBCFG_srpcap | GUSBCFG_hnpcapp); |
@@ -469,13 +482,14 @@ static void handle_ep_int(int ep, bool dir_in) | |||
469 | { | 482 | { |
470 | endpoint->busy = false; | 483 | endpoint->busy = false; |
471 | endpoint->status = 0; | 484 | endpoint->status = 0; |
472 | /* works even for PE0 */ | 485 | /* works even for EP0 */ |
473 | int transfered = endpoint->len - (DIEPTSIZ(ep) & DEPTSIZ_xfersize_bits); | 486 | int transfered = endpoint->len - (DIEPTSIZ(ep) & DEPTSIZ_xfersize_bits); |
474 | logf("len=%d reg=%ld xfer=%d", endpoint->len, | 487 | logf("len=%d reg=%ld xfer=%d", endpoint->len, |
475 | (DIEPTSIZ(ep) & DEPTSIZ_xfersize_bits), | 488 | (DIEPTSIZ(ep) & DEPTSIZ_xfersize_bits), |
476 | transfered); | 489 | transfered); |
477 | invalidate_dcache_range((void *)DIEPDMA(ep), transfered); | 490 | //invalidate_dcache_range(endpoint->buffer, transfered); |
478 | DIEPCTL(ep) |= DEPCTL_snak; | 491 | invalidate_dcache(); |
492 | //DIEPCTL(ep) |= DEPCTL_snak; | ||
479 | /* handle EP0 state if necessary, | 493 | /* handle EP0 state if necessary, |
480 | * this is a ack if length is 0 */ | 494 | * this is a ack if length is 0 */ |
481 | if(ep == 0) | 495 | if(ep == 0) |
@@ -493,7 +507,7 @@ static void handle_ep_int(int ep, bool dir_in) | |||
493 | endpoint->status = 1; | 507 | endpoint->status = 1; |
494 | /* for safety, act as if no bytes as been transfered */ | 508 | /* for safety, act as if no bytes as been transfered */ |
495 | endpoint->len = 0; | 509 | endpoint->len = 0; |
496 | DIEPCTL(ep) |= DEPCTL_snak; | 510 | //DIEPCTL(ep) |= DEPCTL_snak; |
497 | usb_core_transfer_complete(ep, USB_DIR_IN, 1, 0); | 511 | usb_core_transfer_complete(ep, USB_DIR_IN, 1, 0); |
498 | wakeup_signal(&endpoint->complete); | 512 | wakeup_signal(&endpoint->complete); |
499 | } | 513 | } |
@@ -517,13 +531,14 @@ static void handle_ep_int(int ep, bool dir_in) | |||
517 | logf("len=%d reg=%ld xfer=%d", endpoint->len, | 531 | logf("len=%d reg=%ld xfer=%d", endpoint->len, |
518 | (DOEPTSIZ(ep) & DEPTSIZ_xfersize_bits), | 532 | (DOEPTSIZ(ep) & DEPTSIZ_xfersize_bits), |
519 | transfered); | 533 | transfered); |
520 | invalidate_dcache_range((void *)DOEPDMA(ep), transfered); | 534 | //invalidate_dcache_range(endpoint->buffer, transfered); |
535 | invalidate_dcache(); | ||
521 | /* handle EP0 state if necessary, | 536 | /* handle EP0 state if necessary, |
522 | * this is a ack if length is 0 */ | 537 | * this is a ack if length is 0 */ |
523 | if(ep == 0) | 538 | if(ep == 0) |
524 | handle_ep0_complete(endpoint->len == 0); | 539 | handle_ep0_complete(endpoint->len == 0); |
525 | else | 540 | //else |
526 | DOEPCTL(ep) |= DEPCTL_snak; | 541 | // DOEPCTL(ep) |= DEPCTL_snak; |
527 | usb_core_transfer_complete(ep, USB_DIR_OUT, 0, transfered); | 542 | usb_core_transfer_complete(ep, USB_DIR_OUT, 0, transfered); |
528 | wakeup_signal(&endpoint->complete); | 543 | wakeup_signal(&endpoint->complete); |
529 | } | 544 | } |
@@ -536,16 +551,14 @@ static void handle_ep_int(int ep, bool dir_in) | |||
536 | if((DOEPTSIZ(ep) & DEPTSIZ_xfersize_bits) != 0) | 551 | if((DOEPTSIZ(ep) & DEPTSIZ_xfersize_bits) != 0) |
537 | { | 552 | { |
538 | logf("usb-drv: ignore spurious setup (xfersize=%ld)", DOEPTSIZ(ep) & DEPTSIZ_xfersize_bits); | 553 | logf("usb-drv: ignore spurious setup (xfersize=%ld)", DOEPTSIZ(ep) & DEPTSIZ_xfersize_bits); |
554 | prepare_setup_ep0(); | ||
539 | } | 555 | } |
540 | else | 556 | else |
541 | { | 557 | { |
542 | DOEPCTL(ep) |= DEPCTL_snak; | 558 | //DOEPCTL(ep) |= DEPCTL_snak; |
543 | logf("DOEPCTL0=%lx", DOEPCTL(ep)); | ||
544 | logf("DOEPTSIZE0=%lx", DOEPTSIZ(ep)); | ||
545 | if(DOEPDMA(ep) != 8 + (unsigned long)&ep0_setup_pkt) | ||
546 | panicf("usb-drv: EP0 wrong DMA adr (%lx vs %lx)", (unsigned long)&ep0_setup_pkt, DOEPDMA(ep)); | ||
547 | /* handle the set address here because of a bug in the usb core */ | 559 | /* handle the set address here because of a bug in the usb core */ |
548 | invalidate_dcache_range((void*)&ep0_setup_pkt, sizeof ep0_setup_pkt); | 560 | //invalidate_dcache_range((void*)&ep0_setup_pkt, sizeof ep0_setup_pkt); |
561 | invalidate_dcache(); | ||
549 | /* handle EP0 state */ | 562 | /* handle EP0 state */ |
550 | handle_ep0_setup(); | 563 | handle_ep0_setup(); |
551 | logf(" rt=%x r=%x", ep0_setup_pkt.bRequestType, ep0_setup_pkt.bRequest); | 564 | logf(" rt=%x r=%x", ep0_setup_pkt.bRequestType, ep0_setup_pkt.bRequest); |
@@ -590,10 +603,11 @@ void INT_USB(void) | |||
590 | logf("usb-drv: bus reset"); | 603 | logf("usb-drv: bus reset"); |
591 | 604 | ||
592 | /* Clear the Remote Wakeup Signalling */ | 605 | /* Clear the Remote Wakeup Signalling */ |
593 | //DCTL &= ~DCTL_rmtwkupsig; | 606 | DCTL &= ~DCTL_rmtwkupsig; |
594 | 607 | ||
595 | /* Flush FIFOs */ | 608 | /* Flush FIFOs */ |
596 | flush_tx_fifos(0x10); | 609 | flush_tx_fifos(0x10); |
610 | flush_rx_fifo(); | ||
597 | 611 | ||
598 | reset_endpoints(); | 612 | reset_endpoints(); |
599 | 613 | ||
@@ -617,6 +631,22 @@ void INT_USB(void) | |||
617 | prepare_setup_ep0(); | 631 | prepare_setup_ep0(); |
618 | } | 632 | } |
619 | 633 | ||
634 | if(sts & GINTMSK_usbsuspend) | ||
635 | { | ||
636 | logf("usb-drv: suspend"); | ||
637 | } | ||
638 | |||
639 | if(sts & GINTMSK_wkupintr) | ||
640 | { | ||
641 | logf("usb-drv: wake up"); | ||
642 | } | ||
643 | |||
644 | if(sts & GINTMSK_otgintr) | ||
645 | { | ||
646 | logf("usb-drv: otg int"); | ||
647 | GOTGINT = 0xffffffff; | ||
648 | } | ||
649 | |||
620 | if(sts & (GINTMSK_outepintr | GINTMSK_inepintr)) | 650 | if(sts & (GINTMSK_outepintr | GINTMSK_inepintr)) |
621 | { | 651 | { |
622 | handle_ep_ints(); | 652 | handle_ep_ints(); |
@@ -629,7 +659,7 @@ void INT_USB(void) | |||
629 | usb_enable(false); | 659 | usb_enable(false); |
630 | } | 660 | } |
631 | 661 | ||
632 | GINTSTS = GINTSTS; | 662 | GINTSTS = sts; |
633 | } | 663 | } |
634 | 664 | ||
635 | int usb_drv_port_speed(void) | 665 | int usb_drv_port_speed(void) |
@@ -692,11 +722,13 @@ static int usb_drv_transfer(int ep, void *ptr, int len, bool dir_in, bool blocki | |||
692 | 722 | ||
693 | if(endpoint->busy) | 723 | if(endpoint->busy) |
694 | logf("usb-drv: EP%d %s is already busy", ep, dir_in ? "IN" : "OUT"); | 724 | logf("usb-drv: EP%d %s is already busy", ep, dir_in ? "IN" : "OUT"); |
725 | |||
726 | if(dir_in) | ||
727 | logf("GNPTXSTS=%lx", GNPTXSTS); | ||
695 | 728 | ||
696 | endpoint->busy = true; | 729 | endpoint->busy = true; |
697 | endpoint->len = len; | 730 | endpoint->len = len; |
698 | endpoint->wait = blocking; | 731 | endpoint->wait = blocking; |
699 | DEPCTL |= DEPCTL_usbactep; | ||
700 | 732 | ||
701 | int mps = 64; | 733 | int mps = 64; |
702 | int nb_packets = (len + mps - 1) / mps; | 734 | int nb_packets = (len + mps - 1) / mps; |
@@ -705,14 +737,14 @@ static int usb_drv_transfer(int ep, void *ptr, int len, bool dir_in, bool blocki | |||
705 | DEPTSIZ = 1 << DEPTSIZ_pkcnt_bitp; | 737 | DEPTSIZ = 1 << DEPTSIZ_pkcnt_bitp; |
706 | else | 738 | else |
707 | DEPTSIZ = (nb_packets << DEPTSIZ_pkcnt_bitp) | len; | 739 | DEPTSIZ = (nb_packets << DEPTSIZ_pkcnt_bitp) | len; |
708 | clean_dcache_range(ptr, len); | 740 | //clean_dcache_range(ptr, len); |
709 | DEPDMA = (unsigned long)ptr; | 741 | clean_dcache(); |
710 | DEPCTL |= DEPCTL_epena | DEPCTL_cnak; | 742 | DEPDMA = (unsigned long)AS3525_PHYSICAL_ADDR(ptr); |
711 | 743 | ||
712 | /* fixme: check if endpoint was really enabled ? */ | 744 | logf("pkt=%d dma=%lx", nb_packets, DEPDMA); |
713 | if((DEPCTL & DEPCTL_epena) == 0) | ||
714 | panicf("usb-drv: couldn't start xfer on EP%d %s", ep, dir_in ? "IN" : "OUT"); | ||
715 | 745 | ||
746 | DEPCTL |= DEPCTL_epena | DEPCTL_cnak | DEPCTL_usbactep; | ||
747 | |||
716 | if(blocking) | 748 | if(blocking) |
717 | wakeup_wait(&endpoint->complete, TIMEOUT_BLOCK); | 749 | wakeup_wait(&endpoint->complete, TIMEOUT_BLOCK); |
718 | if(endpoint->status != 0) | 750 | if(endpoint->status != 0) |
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.h b/firmware/target/arm/as3525/usb-drv-as3525v2.h index e5cad2ee05..8a7fee15f0 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.h +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.h | |||
@@ -33,8 +33,6 @@ | |||
33 | * extract a field of the register | 33 | * extract a field of the register |
34 | * - bitm(reg_name,field_name) | 34 | * - bitm(reg_name,field_name) |
35 | * build a bitmask for the field | 35 | * build a bitmask for the field |
36 | * - make(reg_name,field_name,value) | ||
37 | * build the value of the field (doesn't mask) | ||
38 | */ | 36 | */ |
39 | #define extract(reg_name, field_name) \ | 37 | #define extract(reg_name, field_name) \ |
40 | ((reg_name >> reg_name##_##field_name##_bitp) & reg_name##_##field_name##_bits) | 38 | ((reg_name >> reg_name##_##field_name##_bitp) & reg_name##_##field_name##_bits) |