diff options
Diffstat (limited to 'firmware/target/arm/as3525')
-rw-r--r-- | firmware/target/arm/as3525/sd-as3525v2.c | 73 |
1 files changed, 51 insertions, 22 deletions
diff --git a/firmware/target/arm/as3525/sd-as3525v2.c b/firmware/target/arm/as3525/sd-as3525v2.c index 035dac7490..862cf3ca13 100644 --- a/firmware/target/arm/as3525/sd-as3525v2.c +++ b/firmware/target/arm/as3525/sd-as3525v2.c | |||
@@ -70,10 +70,11 @@ static void printf(const char *format, ...) | |||
70 | 70 | ||
71 | /* | 71 | /* |
72 | * STATUS register | 72 | * STATUS register |
73 | * & 0xBA80 | 73 | * & 0xBA80 = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \ |
74 | * & 8 | 74 | * MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE |
75 | * & 0x428 | 75 | * & 8 = MCI_INT_DTO |
76 | * & 0x418 | 76 | * & 0x428 = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO |
77 | * & 0x418 = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO | ||
77 | */ | 78 | */ |
78 | 79 | ||
79 | /* | 80 | /* |
@@ -178,6 +179,26 @@ static void printf(const char *format, ...) | |||
178 | * status clear */ | 179 | * status clear */ |
179 | #define MCI_STATUS SD_REG(0x48) | 180 | #define MCI_STATUS SD_REG(0x48) |
180 | 181 | ||
182 | /* interrupt bits */ | ||
183 | #define MCI_INT_CRDDET (1<<0) | ||
184 | #define MCI_INT_RE (1<<1) | ||
185 | #define MCI_INT_CD (1<<2) | ||
186 | #define MCI_INT_DTO (1<<3) | ||
187 | #define MCI_INT_TXDR (1<<4) | ||
188 | #define MCI_INT_RXDR (1<<5) | ||
189 | #define MCI_INT_RCRC (1<<6) | ||
190 | #define MCI_INT_DCRC (1<<7) | ||
191 | #define MCI_INT_RTO (1<<8) | ||
192 | #define MCI_INT_DRTO (1<<9) | ||
193 | #define MCI_INT_HTO (1<<10) | ||
194 | #define MCI_INT_FRUN (1<<11) | ||
195 | #define MCI_INT_HLE (1<<12) | ||
196 | #define MCI_INT_SBE (1<<13) | ||
197 | #define MCI_INT_ACD (1<<14) | ||
198 | #define MCI_INT_EBE (1<<15) | ||
199 | #define MCI_INT_SDIO (0xf<<16) | ||
200 | |||
201 | |||
181 | #define MCI_FIFOTH SD_REG(0x4C) /* FIFO threshold */ | 202 | #define MCI_FIFOTH SD_REG(0x4C) /* FIFO threshold */ |
182 | #define MCI_CDETECT SD_REG(0x50) /* card detect */ | 203 | #define MCI_CDETECT SD_REG(0x50) /* card detect */ |
183 | #define MCI_WRTPRT SD_REG(0x54) /* write protect */ | 204 | #define MCI_WRTPRT SD_REG(0x54) /* write protect */ |
@@ -248,12 +269,18 @@ void INT_NAND(void) | |||
248 | //static int x = 0; | 269 | //static int x = 0; |
249 | switch(status) | 270 | switch(status) |
250 | { | 271 | { |
251 | case 0x4: /* cmd received ? */ | 272 | case 0x4: /* cmd received ? = MCI_INT_CDMCI_INT_CD */ |
252 | case 0x104: /* ? 1 time in init (10th interrupt) */ | 273 | |
253 | case 0x2000: /* ? after cmd read_mul_blocks | 0x2200 */ | 274 | case 0x104: /* ? 1 time in init (10th interrupt) |
275 | * = MCI_INT_CD | MCI_INT_RTO */ | ||
254 | 276 | ||
255 | case 0x820: /* ? 1 time while copy from FIFO (not DMA) */ | 277 | case 0x2000: /* ? after cmd read_mul_blocks | 0x2200 |
256 | case 0x20: /* ? rx fifo empty */ | 278 | * = MCI_INT_SBE */ |
279 | |||
280 | case 0x820: /* ? 1 time while copy from FIFO (not DMA) | ||
281 | * = MCI_INT_RXDR | MCI_INT_FRUN */ | ||
282 | |||
283 | case 0x20: /* ? rx fifo empty = MCI_INT_RXDR */ | ||
257 | break; | 284 | break; |
258 | #if 0 | 285 | #if 0 |
259 | default: | 286 | default: |
@@ -262,18 +289,20 @@ void INT_NAND(void) | |||
262 | #endif | 289 | #endif |
263 | } | 290 | } |
264 | /* | 291 | /* |
265 | * 0x48 = some kind of status | 292 | * MCI_STATUS = |
266 | * 0x106 | 293 | * 0x106 = MCI_INT_RE | MCI_INT_CD | MCI_INT_RTO |
267 | * 0x4106 | 294 | * 0x4106 |= MCI_INT_ACD |
268 | * 1B906 | 295 | * 1B906 = MCI_INT_RE | MCI_INT_CD | MCI_INT_RTO | MCI_INT_FRUN |
269 | * 1F906 | 296 | * | MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE |
297 | * 1F906 |= MCI_INT_ACD | ||
270 | * 1B906 | 298 | * 1B906 |
271 | * 1F906 | 299 | * 1F906 |
272 | * 1F906 | 300 | * 1F906 |
273 | * 1906 | 301 | * 1906 |
274 | * ... | 302 | * ... |
275 | * 6906 | 303 | * 6906 = MCI_INT_RE | MCI_INT_CD | MCI_INT_RTO | MCI_INT_FRUN | |
276 | * 6D06 (dma) | 304 | * MCI_INT_SBE | MCI_INT_ACD |
305 | * 6D06 (dma) |= MCI_INT_HTO | ||
277 | * | 306 | * |
278 | * read resp (6, 7, 12, 42) : while bit 9 is unset ; | 307 | * read resp (6, 7, 12, 42) : while bit 9 is unset ; |
279 | * | 308 | * |
@@ -500,7 +529,6 @@ static void init_controller(void) | |||
500 | ; | 529 | ; |
501 | 530 | ||
502 | MCI_RAW_STATUS = 0xffffffff; | 531 | MCI_RAW_STATUS = 0xffffffff; |
503 | MCI_MASK = 0xffffbffe; | ||
504 | 532 | ||
505 | MCI_CTRL |= INT_ENABLE; | 533 | MCI_CTRL |= INT_ENABLE; |
506 | MCI_TMOUT = 0xffffffff; | 534 | MCI_TMOUT = 0xffffffff; |
@@ -514,12 +542,12 @@ static void init_controller(void) | |||
514 | int max = 10; | 542 | int max = 10; |
515 | while(max-- && (MCI_COMMAND & (1<<31))) ; | 543 | while(max-- && (MCI_COMMAND & (1<<31))) ; |
516 | 544 | ||
517 | MCI_DEBNCE = 0xfffff; | 545 | MCI_DEBNCE = 0xfffff; /* default value */ |
518 | 546 | ||
519 | MCI_FIFOTH = ~0x7fff0fff; | 547 | MCI_FIFOTH = ~0x7fff0fff; |
520 | MCI_FIFOTH |= 0x503f0080; | 548 | MCI_FIFOTH |= 0x503f0080; |
521 | 549 | ||
522 | MCI_MASK = 0xffffbffe; | 550 | MCI_MASK = 0xffffffff & (~MCI_INT_ACD & ~MCI_INTCRDRET); |
523 | } | 551 | } |
524 | 552 | ||
525 | int sd_init(void) | 553 | int sd_init(void) |
@@ -682,10 +710,11 @@ static int sd_transfer_sectors(unsigned long start, int count, void* buf, bool w | |||
682 | while(MCI_CTRL & FIFO_RESET) | 710 | while(MCI_CTRL & FIFO_RESET) |
683 | ; | 711 | ; |
684 | 712 | ||
685 | MCI_FIFOTH &= ~0x7fff0fff; | ||
686 | |||
687 | MCI_CTRL |= DMA_ENABLE; | 713 | MCI_CTRL |= DMA_ENABLE; |
688 | MCI_MASK = 0xBE8C; | 714 | MCI_MASK = MCI_INT_CD|MCI_INT_DTO|MCI_INT_DCRC|MCI_INT_DRTO| \ |
715 | MCI_INT_HTO|MCI_INT_FRUN|MCI_INT_HLE|MCI_INT_SBE|MCI_INT_EBE; | ||
716 | |||
717 | MCI_FIFOTH &= ~0x7fff0fff; | ||
689 | MCI_FIFOTH |= 0x503f0080; | 718 | MCI_FIFOTH |= 0x503f0080; |
690 | 719 | ||
691 | 720 | ||