diff options
Diffstat (limited to 'firmware/target/arm/as3525')
-rw-r--r-- | firmware/target/arm/as3525/usb-drv-as3525v2.c | 343 | ||||
-rw-r--r-- | firmware/target/arm/as3525/usb-drv-as3525v2.h | 250 |
2 files changed, 431 insertions, 162 deletions
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.c b/firmware/target/arm/as3525/usb-drv-as3525v2.c index 98805ca578..db79ac4d20 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.c +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.c | |||
@@ -25,8 +25,12 @@ | |||
25 | #include "clock-target.h" | 25 | #include "clock-target.h" |
26 | #include "ascodec.h" | 26 | #include "ascodec.h" |
27 | #include "as3514.h" | 27 | #include "as3514.h" |
28 | #include <stdbool.h> | 28 | #include "stdbool.h" |
29 | #include "string.h" | ||
30 | #include "stdio.h" | ||
29 | #include "panic.h" | 31 | #include "panic.h" |
32 | #include "mmu-arm.h" | ||
33 | #include "system.h" | ||
30 | #define LOGF_ENABLE | 34 | #define LOGF_ENABLE |
31 | #include "logf.h" | 35 | #include "logf.h" |
32 | #include "usb-drv-as3525v2.h" | 36 | #include "usb-drv-as3525v2.h" |
@@ -47,9 +51,11 @@ struct usb_endpoint | |||
47 | #if 0 | 51 | #if 0 |
48 | static struct usb_endpoint endpoints[USB_NUM_ENDPOINTS*2]; | 52 | static struct usb_endpoint endpoints[USB_NUM_ENDPOINTS*2]; |
49 | #endif | 53 | #endif |
54 | static struct usb_ctrlrequest ep0_setup_pkt; | ||
50 | 55 | ||
51 | void usb_attach(void) | 56 | void usb_attach(void) |
52 | { | 57 | { |
58 | logf("usb: attach"); | ||
53 | usb_enable(true); | 59 | usb_enable(true); |
54 | } | 60 | } |
55 | 61 | ||
@@ -79,7 +85,7 @@ static void as3525v2_connect(void) | |||
79 | USB_PCGCCTL &= ~0x8; | 85 | USB_PCGCCTL &= ~0x8; |
80 | usb_delay(); | 86 | usb_delay(); |
81 | /* 6) set "power on program done" */ | 87 | /* 6) set "power on program done" */ |
82 | USB_DCTL |= 0x800; | 88 | USB_DCTL |= USB_DCTL_pwronprgdone; |
83 | usb_delay(); | 89 | usb_delay(); |
84 | /* 7) core soft reset */ | 90 | /* 7) core soft reset */ |
85 | USB_GRSTCTL |= USB_GRSTCTL_csftrst; | 91 | USB_GRSTCTL |= USB_GRSTCTL_csftrst; |
@@ -91,8 +97,8 @@ static void as3525v2_connect(void) | |||
91 | USB_GRSTCTL |= 0x3f; | 97 | USB_GRSTCTL |= 0x3f; |
92 | usb_delay(); | 98 | usb_delay(); |
93 | /* 10) force device mode*/ | 99 | /* 10) force device mode*/ |
94 | USB_GUSBCFG &= ~0x20000000; | 100 | USB_GUSBCFG &= ~USB_GUSBCFG_force_host_mode; |
95 | USB_GUSBCFG |= 0x40000000; | 101 | USB_GUSBCFG |= USB_GUSBCFG_force_device_mode; |
96 | usb_delay(); | 102 | usb_delay(); |
97 | /* 11) Do something that is probably CCU related but undocumented*/ | 103 | /* 11) Do something that is probably CCU related but undocumented*/ |
98 | CCU_USB_THINGY &= ~0x1000; | 104 | CCU_USB_THINGY &= ~0x1000; |
@@ -111,14 +117,9 @@ static void usb_enable_common_interrupts(void) | |||
111 | /* Clear any pending interrupt */ | 117 | /* Clear any pending interrupt */ |
112 | USB_GINTSTS = 0Xffffffff; | 118 | USB_GINTSTS = 0Xffffffff; |
113 | /* Enable interrupts */ | 119 | /* Enable interrupts */ |
114 | USB_GINTMSK |= USB_GINTMSK_modemismatch | | 120 | USB_GINTMSK = USB_GINTMSK_otgintr |
115 | USB_GINTMSK_otgintr | | 121 | | USB_GINTMSK_conidstschng |
116 | USB_GINTMSK_rxstsqlvl | /* for dma */ | 122 | | USB_GINTMSK_disconnect; |
117 | USB_GINTMSK_conidstschng | | ||
118 | USB_GINTMSK_wkupintr | | ||
119 | USB_GINTMSK_disconnect | | ||
120 | USB_GINTMSK_usbsuspend | | ||
121 | USB_GINTMSK_sessreqintr; | ||
122 | } | 123 | } |
123 | 124 | ||
124 | static void usb_enable_device_interrupts(void) | 125 | static void usb_enable_device_interrupts(void) |
@@ -130,20 +131,10 @@ static void usb_enable_device_interrupts(void) | |||
130 | /* Enable common interrupts */ | 131 | /* Enable common interrupts */ |
131 | usb_enable_common_interrupts(); | 132 | usb_enable_common_interrupts(); |
132 | /* Enable interrupts */ | 133 | /* Enable interrupts */ |
133 | USB_GINTMSK |= | 134 | USB_GINTMSK |= USB_GINTMSK_usbreset |
134 | USB_GINTMSK_usb_rst | 135 | | USB_GINTMSK_enumdone |
135 | | USB_GINTMSK_enumdone | 136 | | USB_GINTMSK_inepintr |
136 | | USB_GINTMSK_inepintr | 137 | | USB_GINTMSK_outepintr; |
137 | | USB_GINTMSK_outepintr | ||
138 | | USB_GINTMSK_erlysuspend | ||
139 | | USB_GINTMSK_epmismatch /* only if multiple tx fifos enabled */ | ||
140 | #if 0 /* only if periodic fifo used */ | ||
141 | | USB_GINTMSK_isooutdrop | ||
142 | | USB_GINTMSK_eopframe | ||
143 | | USB_GINTMSK_incomplisoin | ||
144 | | USB_GINTMSK_incomplisoout | ||
145 | #endif | ||
146 | ; | ||
147 | } | 138 | } |
148 | 139 | ||
149 | static void usb_flush_tx_fifos(int nums) | 140 | static void usb_flush_tx_fifos(int nums) |
@@ -158,31 +149,28 @@ static void usb_flush_tx_fifos(int nums) | |||
158 | if(USB_GRSTCTL & USB_GRSTCTL_txfflsh_flush) | 149 | if(USB_GRSTCTL & USB_GRSTCTL_txfflsh_flush) |
159 | panicf("usb: hang of flush tx fifos (%x)", nums); | 150 | panicf("usb: hang of flush tx fifos (%x)", nums); |
160 | /* wait 3 phy clocks */ | 151 | /* wait 3 phy clocks */ |
161 | sleep(1); | 152 | udelay(1); |
162 | } | 153 | } |
163 | 154 | ||
164 | static void usb_flush_rx_fifo(void) | 155 | static void usb_flush_rx_fifo(void) |
165 | { | 156 | { |
166 | unsigned int i = 0; | 157 | unsigned int i = 0; |
167 | 158 | ||
168 | USB_GRSTCTL |= USB_GRSTCTL_rxfflsh_flush; | 159 | USB_GRSTCTL = USB_GRSTCTL_rxfflsh_flush; |
169 | while(USB_GRSTCTL & USB_GRSTCTL_rxfflsh_flush && i < 0x300) | 160 | while(USB_GRSTCTL & USB_GRSTCTL_rxfflsh_flush && i < 0x300) |
170 | i++; | 161 | i++; |
171 | if(USB_GRSTCTL & USB_GRSTCTL_rxfflsh_flush) | 162 | if(USB_GRSTCTL & USB_GRSTCTL_rxfflsh_flush) |
172 | panicf("usb: hang of flush rx fifo"); | 163 | panicf("usb: hang of flush rx fifo"); |
173 | /* wait 3 phy clocks */ | 164 | /* wait 3 phy clocks */ |
174 | sleep(1); | 165 | udelay(1); |
175 | } | 166 | } |
176 | 167 | ||
177 | static void core_reset(void) | 168 | static void core_reset(void) |
178 | { | 169 | { |
179 | unsigned int i = 0; | 170 | unsigned int i = 0; |
180 | /* Wait for AHB master IDLE state. */ | 171 | /* Wait for AHB master IDLE state. */ |
181 | while((USB_GRSTCTL & USB_GRSTCTL_ahbidle) == 0); | 172 | while((USB_GRSTCTL & USB_GRSTCTL_ahbidle) == 0) |
182 | { | 173 | udelay(10); |
183 | /*udelay(10);*/ | ||
184 | sleep(1); | ||
185 | } | ||
186 | /* Core Soft Reset */ | 174 | /* Core Soft Reset */ |
187 | USB_GRSTCTL |= USB_GRSTCTL_csftrst; | 175 | USB_GRSTCTL |= USB_GRSTCTL_csftrst; |
188 | /* Waits for the hardware to clear reset bit */ | 176 | /* Waits for the hardware to clear reset bit */ |
@@ -193,8 +181,7 @@ static void core_reset(void) | |||
193 | panicf("oops, usb core soft reset hang :("); | 181 | panicf("oops, usb core soft reset hang :("); |
194 | 182 | ||
195 | /* Wait for 3 PHY Clocks */ | 183 | /* Wait for 3 PHY Clocks */ |
196 | /*mdelay(100);*/ | 184 | udelay(1); |
197 | sleep(1); | ||
198 | } | 185 | } |
199 | 186 | ||
200 | static void core_dev_init(void) | 187 | static void core_dev_init(void) |
@@ -216,12 +203,6 @@ static void core_dev_init(void) | |||
216 | panicf("usb: wrong HS phy type (%ld)", USB_GHWCFG2_HS_PHY_TYPE); | 203 | panicf("usb: wrong HS phy type (%ld)", USB_GHWCFG2_HS_PHY_TYPE); |
217 | if(USB_GHWCFG2_FS_PHY_TYPE != USB_PHY_TYPE_UNSUPPORTED) | 204 | if(USB_GHWCFG2_FS_PHY_TYPE != USB_PHY_TYPE_UNSUPPORTED) |
218 | panicf("usb: wrong FS phy type (%ld)", USB_GHWCFG2_FS_PHY_TYPE); | 205 | panicf("usb: wrong FS phy type (%ld)", USB_GHWCFG2_FS_PHY_TYPE); |
219 | #ifdef USB_USE_CUSTOM_FIFO_LAYOUT | ||
220 | if(USB_GHWCFG2_DYN_FIFO != 1) | ||
221 | panicf("usb: no dynamic fifo"); | ||
222 | if(USB_GRXFSIZ != USB_DATA_FIFO_DEPTH) | ||
223 | panicf("usb: wrong data fifo size"); | ||
224 | #endif /* USB_USE_CUSTOM_FIFO_LAYOUT */ | ||
225 | if(USB_GHWCFG4_UTMI_PHY_DATA_WIDTH != 0x2) | 206 | if(USB_GHWCFG4_UTMI_PHY_DATA_WIDTH != 0x2) |
226 | panicf("usb: wrong utmi data width (%ld)", USB_GHWCFG4_UTMI_PHY_DATA_WIDTH); | 207 | panicf("usb: wrong utmi data width (%ld)", USB_GHWCFG4_UTMI_PHY_DATA_WIDTH); |
227 | if(USB_GHWCFG4_DED_FIFO_EN != 1) /* it seems to be multiple tx fifo support */ | 208 | if(USB_GHWCFG4_DED_FIFO_EN != 1) /* it seems to be multiple tx fifo support */ |
@@ -264,52 +245,12 @@ static void core_dev_init(void) | |||
264 | USB_GET_FIFOSIZE_DEPTH(USB_DIEPTXFSIZ(i))); | 245 | USB_GET_FIFOSIZE_DEPTH(USB_DIEPTXFSIZ(i))); |
265 | } | 246 | } |
266 | 247 | ||
267 | #ifdef USB_USE_CUSTOM_FIFO_LAYOUT | ||
268 | /* Setup FIFOs */ | ||
269 | /* Organize FIFO as follow: | ||
270 | * 0 -> rxfsize : RX fifo | ||
271 | * rxfsize -> rxfsize + nptxfsize : TX fifo for first IN ep | ||
272 | * rxfsize + nptxfsize -> rxfsize + 2 * nptxfsize : TX fifo for second IN ep | ||
273 | * rxfsize + 2 * nptxfsize -> rxfsize + 3 * nptxfsize : TX fifo for third IN ep | ||
274 | * ... | ||
275 | */ | ||
276 | |||
277 | unsigned short adr = 0; | ||
278 | unsigned short depth = USB_RX_FIFO_SIZE; | ||
279 | USB_GRXFSIZ = depth; | ||
280 | adr += depth; | ||
281 | depth = USB_NPTX_FIFO_SIZE; | ||
282 | USB_GNPTXFSIZ = USB_MAKE_FIFOSIZE_DATA(adr, depth); | ||
283 | adr += depth; | ||
284 | |||
285 | for(i = 1; i <= USB_NUM_IN_EP; i++) | ||
286 | { | ||
287 | depth = USB_EPTX_FIFO_SIZE; | ||
288 | USB_DIEPTXFSIZ(i) = USB_MAKE_FIFOSIZE_DATA(adr, depth); | ||
289 | adr += depth; | ||
290 | } | ||
291 | |||
292 | logf("used:"); | ||
293 | logf(" rx fifo: [%04x,+%4lx]", 0, USB_GRXFSIZ); | ||
294 | logf(" nptx fifo: [%04lx,+%4lx]", USB_GET_FIFOSIZE_START_ADR(USB_GNPTXFSIZ), | ||
295 | USB_GET_FIFOSIZE_DEPTH(USB_GNPTXFSIZ)); | ||
296 | for(i = 1; i <= USB_NUM_IN_EP; i++) | ||
297 | { | ||
298 | logf(" dieptx fifo(%2u): [%04lx,+%4lx]", i, | ||
299 | USB_GET_FIFOSIZE_START_ADR(USB_DIEPTXFSIZ(i)), | ||
300 | USB_GET_FIFOSIZE_DEPTH(USB_DIEPTXFSIZ(i))); | ||
301 | } | ||
302 | |||
303 | if(adr > USB_DATA_FIFO_DEPTH) | ||
304 | panicf("usb: total data fifo size exceeded"); | ||
305 | #endif /* USB_USE_CUSTOM_FIFO_LAYOUT */ | ||
306 | |||
307 | /* flush the fifos */ | 248 | /* flush the fifos */ |
308 | usb_flush_tx_fifos(0x10); /* flush all */ | 249 | usb_flush_tx_fifos(0x10); /* flush all */ |
309 | usb_flush_rx_fifo(); | 250 | usb_flush_rx_fifo(); |
310 | 251 | ||
311 | /* flush learning queue */ | 252 | /* flush learning queue */ |
312 | USB_GRSTCTL |= USB_GRSTCTL_intknqflsh; | 253 | USB_GRSTCTL = USB_GRSTCTL_intknqflsh; |
313 | 254 | ||
314 | /* Clear all pending device interrupts */ | 255 | /* Clear all pending device interrupts */ |
315 | USB_DIEPMSK = 0; | 256 | USB_DIEPMSK = 0; |
@@ -361,33 +302,30 @@ static void core_dev_init(void) | |||
361 | 302 | ||
362 | static void core_init(void) | 303 | static void core_init(void) |
363 | { | 304 | { |
364 | /* Reset the Controller */ | 305 | /* Setup phy for high speed */ |
306 | USB_GUSBCFG &= ~USB_GUSBCFG_ulpi_ext_vbus_drv; | ||
307 | /* Disable external TS Dline pulsing (???) */ | ||
308 | USB_GUSBCFG &= ~USB_GUSBCFG_term_sel_dl_pulse; | ||
309 | /* core reset */ | ||
365 | core_reset(); | 310 | core_reset(); |
366 | 311 | ||
367 | /* Setup phy for high speed */ | 312 | /* Select UTMI */ |
368 | /* 1) select utmi */ | 313 | USB_GUSBCFG &= ~USB_GUSBCFG_ulpi_utmi_sel; |
369 | /* fixme: the clip+ hardware support utmi only, this is useless */ | 314 | /* Select UTMI+ 16 */ |
370 | //USB_GUSBCFG &= ~USB_GUSBCFG_ulpi_utmi_sel; | ||
371 | /* 2) select utmi 16-bit wide bus */ | ||
372 | USB_GUSBCFG |= USB_GUSBCFG_phy_if; | 315 | USB_GUSBCFG |= USB_GUSBCFG_phy_if; |
373 | /* 3) core reset */ | 316 | /* core reset */ |
374 | /* fixme: linux patch says the phy parameters survive the soft reset so | ||
375 | * perhaps this part can be done only one type but I don't know | ||
376 | * what happened when phy goes to standby mode and clock are disabled */ | ||
377 | core_reset(); | 317 | core_reset(); |
378 | 318 | ||
379 | /* fixme: at this point, the linux patch sets ulpi bits to 0 on utmi selection | 319 | /* fixme: the linux code does that but the clip+ doesn't use ULPI it seems */ |
380 | * but the clip+ hardware does not support it so don't bother with | 320 | USB_GUSBCFG &= ~(USB_GUSBCFG_ulpi_fsls | USB_GUSBCFG_ulpi_clk_sus_m); |
381 | * that */ | ||
382 | 321 | ||
383 | /* fixme: the current code is for internal DMA only, the clip+ architecture | 322 | /* fixme: the current code is for internal DMA only, the clip+ architecture |
384 | * define the internal DMA model */ | 323 | * define the internal DMA model */ |
385 | /* Set burstlen */ | 324 | /* Set burstlen and enable DMA*/ |
386 | USB_GAHBCFG |= USB_GAHBCFG_INT_DMA_BURST_INCR << USB_GAHBCFG_hburstlen_bit_pos; | 325 | USB_GAHBCFG = (USB_GAHBCFG_INT_DMA_BURST_INCR << USB_GAHBCFG_hburstlen_bit_pos) |
387 | /* Enable DMA */ | 326 | | USB_GAHBCFG_dma_enable; |
388 | USB_GAHBCFG |= USB_GAHBCFG_dma_enable; | ||
389 | /* Disable HNP and SRP, not sure it's useful because we already forced dev mode */ | 327 | /* Disable HNP and SRP, not sure it's useful because we already forced dev mode */ |
390 | USB_GUSBCFG &= ~(USB_GUSBCFG_SRP_cap | USB_GUSBCFG_HNP_cap); | 328 | USB_GUSBCFG &= ~(USB_GUSBCFG_srpcap | USB_GUSBCFG_hnpcapp); |
391 | 329 | ||
392 | /* enable basic interrupts */ | 330 | /* enable basic interrupts */ |
393 | usb_enable_common_interrupts(); | 331 | usb_enable_common_interrupts(); |
@@ -472,13 +410,212 @@ int usb_drv_send_nonblocking(int ep, void *ptr, int len) | |||
472 | return -1; | 410 | return -1; |
473 | } | 411 | } |
474 | 412 | ||
413 | static void activate_ep0(void) | ||
414 | { | ||
415 | /* Setup EP0 OUT to receive setup packets and | ||
416 | * EP0 IN to transmit packets | ||
417 | * The setup takes enumeration speed into account | ||
418 | */ | ||
419 | |||
420 | /* Setup packet size of IN ep based of enumerated speed */ | ||
421 | switch((USB_DSTS & USB_DSTS_enumspd_bits) >> USB_DSTS_enumspd_bit_pos) | ||
422 | { | ||
423 | case USB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: | ||
424 | case USB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: | ||
425 | case USB_DSTS_ENUMSPD_FS_PHY_48MHZ: | ||
426 | /* Use 64 bytes packet size */ | ||
427 | USB_DIEPCTL(0) = (USB_DIEPCTL(0) & (~USB_DEPCTL_mps_bits)) | ||
428 | | (USB_DEPCTL_MPS_64 << USB_DEPCTL_mps_bit_pos); | ||
429 | break; | ||
430 | case USB_DSTS_ENUMSPD_LS_PHY_6MHZ: | ||
431 | USB_DIEPCTL(0) = (USB_DIEPCTL(0) & (~USB_DEPCTL_mps_bits)) | ||
432 | | (USB_DEPCTL_MPS_8 << USB_DEPCTL_mps_bit_pos); | ||
433 | break; | ||
434 | default: | ||
435 | panicf("usb: invalid enum speed"); | ||
436 | } | ||
437 | |||
438 | /* Enable OUT ep for receive */ | ||
439 | USB_DOEPCTL(0) |= USB_DEPCTL_epena; | ||
440 | |||
441 | /* Clear non periodic NAK for IN ep */ | ||
442 | USB_DCTL |= USB_DCTL_cgnpinnak; | ||
443 | } | ||
444 | |||
445 | static void ep0_out_start(void) | ||
446 | { | ||
447 | /* Setup EP0 OUT with the following parameters: | ||
448 | * packet count = 1 | ||
449 | * setup packet count = 1 | ||
450 | * transfer size = 8 (=sizeof setup packet) | ||
451 | */ | ||
452 | |||
453 | USB_DOEPTSIZ(0) = (1 << USB_DEPTSIZ0_supcnt_bit_pos) | ||
454 | | (1 << USB_DEPTSIZ0_pkcnt_bit_pos) | ||
455 | | 8; | ||
456 | |||
457 | /* setup DMA */ | ||
458 | clean_dcache_range((void*)&ep0_setup_pkt, sizeof ep0_setup_pkt); /* force write back */ | ||
459 | USB_DOEPDMA(0) = (unsigned long)&ep0_setup_pkt; /* virtual address=physical address */ | ||
460 | |||
461 | /* enable EP */ | ||
462 | USB_DOEPCTL(0) |= USB_DEPCTL_epena | USB_DEPCTL_usbactep; | ||
463 | } | ||
464 | |||
465 | static bool handle_usb_reset(void) | ||
466 | { | ||
467 | unsigned int i; | ||
468 | logf("usb: bus reset"); | ||
469 | |||
470 | /* Clear the Remote Wakeup Signalling */ | ||
471 | USB_DCTL &= ~USB_DCTL_rmtwkupsig; | ||
472 | |||
473 | /* Set NAK for all OUT EPs */ | ||
474 | for(i = 0; i <= USB_NUM_OUT_EP; i++) | ||
475 | USB_DOEPCTL(i) = USB_DEPCTL_snak; | ||
476 | |||
477 | /* Flush the NP Tx FIFO */ | ||
478 | usb_flush_tx_fifos(0); | ||
479 | |||
480 | /* Flush the Learning Queue */ | ||
481 | USB_GRSTCTL = USB_GRSTCTL_intknqflsh; | ||
482 | |||
483 | /* Setup interrupt masks */ | ||
484 | USB_DAINTMSK = USB_DAINT_IN_EP(0) | USB_DAINT_OUT_EP(0); | ||
485 | USB_DOEPMSK = USB_DOEPINT_setup | USB_DOEPINT_xfercompl | USB_DOEPINT_ahberr | ||
486 | | USB_DOEPINT_epdisabled; | ||
487 | USB_DIEPMSK = USB_DIEPINT_xfercompl | USB_DIEPINT_timeout | ||
488 | | USB_DIEPINT_epdisabled | USB_DIEPINT_ahberr | ||
489 | | USB_DIEPINT_intknepmis; | ||
490 | |||
491 | /* Reset Device Address */ | ||
492 | USB_DCFG &= ~USB_DCFG_devadr_bits; | ||
493 | |||
494 | /* setup EP0 to receive SETUP packets */ | ||
495 | ep0_out_start(); | ||
496 | /* Clear interrupt */ | ||
497 | USB_GINTSTS = USB_GINTMSK_usbreset; | ||
498 | |||
499 | usb_disable_global_interrupts(); | ||
500 | |||
501 | return true; | ||
502 | } | ||
503 | |||
504 | static bool handle_enum_done(void) | ||
505 | { | ||
506 | logf("usb: enum done"); | ||
507 | |||
508 | /* Enable EP0 to receive SETUP packets */ | ||
509 | activate_ep0(); | ||
510 | |||
511 | /* Set USB turnaround time | ||
512 | * fixme: unsure about this */ | ||
513 | //USB_GUSBCFG = (USB_GUSBCFG & ~USB_GUSBCFG_usbtrdtim_bits) | (5 << USB_GUSBCFG_usbtrdtim_bit_pos); | ||
514 | //panicf("usb: turnaround time is %d", (USB_GUSBCFG & USB_GUSBCFG_usbtrdtim_bits) >> USB_GUSBCFG_usbtrdtim_bit_pos); | ||
515 | |||
516 | /* Clear interrupt */ | ||
517 | USB_GINTSTS = USB_GINTMSK_enumdone; | ||
518 | |||
519 | return true; | ||
520 | } | ||
521 | |||
522 | static bool handle_in_ep_int(void) | ||
523 | { | ||
524 | logf("usb: in ep int"); | ||
525 | return false; | ||
526 | } | ||
527 | |||
528 | static bool handle_out_ep_int(void) | ||
529 | { | ||
530 | logf("usb: out ep int"); | ||
531 | return false; | ||
532 | } | ||
533 | |||
534 | static void dump_intsts(char *buffer, size_t size, unsigned long sts) | ||
535 | { | ||
536 | (void) size; | ||
537 | buffer[0] = 0; | ||
538 | #define DUMP_CASE(name) \ | ||
539 | if(sts & USB_GINTMSK_##name) strcat(buffer, #name " "); | ||
540 | |||
541 | DUMP_CASE(modemismatch) | ||
542 | DUMP_CASE(otgintr) | ||
543 | DUMP_CASE(sofintr) | ||
544 | DUMP_CASE(rxstsqlvl) | ||
545 | DUMP_CASE(nptxfempty) | ||
546 | DUMP_CASE(ginnakeff) | ||
547 | DUMP_CASE(goutnakeff) | ||
548 | DUMP_CASE(i2cintr) | ||
549 | DUMP_CASE(erlysuspend) | ||
550 | DUMP_CASE(usbsuspend) | ||
551 | DUMP_CASE(usbreset) | ||
552 | DUMP_CASE(enumdone) | ||
553 | DUMP_CASE(isooutdrop) | ||
554 | DUMP_CASE(eopframe) | ||
555 | DUMP_CASE(epmismatch) | ||
556 | DUMP_CASE(inepintr) | ||
557 | DUMP_CASE(outepintr) | ||
558 | DUMP_CASE(incomplisoin) | ||
559 | DUMP_CASE(incomplisoout) | ||
560 | DUMP_CASE(portintr) | ||
561 | DUMP_CASE(hcintr) | ||
562 | DUMP_CASE(ptxfempty) | ||
563 | DUMP_CASE(conidstschng) | ||
564 | DUMP_CASE(disconnect) | ||
565 | DUMP_CASE(sessreqintr) | ||
566 | DUMP_CASE(wkupintr) | ||
567 | |||
568 | buffer[strlen(buffer) - 1] = 0; | ||
569 | } | ||
570 | |||
475 | /* interrupt service routine */ | 571 | /* interrupt service routine */ |
476 | void INT_USB(void) | 572 | void INT_USB(void) |
477 | { | 573 | { |
478 | panicf("USB interrupt !"); | 574 | static char buffer[256]; |
575 | /* some bits in GINTSTS can be set even though we didn't enable the interrupt source | ||
576 | * so AND it with the actual mask */ | ||
577 | unsigned long sts = USB_GINTSTS & USB_GINTMSK; | ||
578 | unsigned long handled_one = 0; /* mask of all listed one (either handled or not) */ | ||
579 | |||
580 | #define HANDLED_CASE(bitmask, callfn) \ | ||
581 | handled_one |= bitmask; \ | ||
582 | if(sts & bitmask) \ | ||
583 | { \ | ||
584 | if(!callfn()) \ | ||
585 | goto Lerr; \ | ||
586 | } | ||
587 | |||
588 | #define UNHANDLED_CASE(bitmask) \ | ||
589 | handled_one |= bitmask; \ | ||
590 | if(sts & bitmask) \ | ||
591 | goto Lunhandled; | ||
592 | |||
593 | /* device part */ | ||
594 | HANDLED_CASE(USB_GINTMSK_usbreset, handle_usb_reset) | ||
595 | HANDLED_CASE(USB_GINTMSK_enumdone, handle_enum_done) | ||
596 | HANDLED_CASE(USB_GINTMSK_inepintr, handle_in_ep_int) | ||
597 | HANDLED_CASE(USB_GINTMSK_outepintr, handle_out_ep_int) | ||
598 | |||
599 | /* common part */ | ||
600 | UNHANDLED_CASE(USB_GINTMSK_otgintr) | ||
601 | UNHANDLED_CASE(USB_GINTMSK_conidstschng) | ||
602 | UNHANDLED_CASE(USB_GINTMSK_disconnect) | ||
603 | |||
604 | /* unlisted ones */ | ||
605 | if(sts & ~handled_one) | ||
606 | goto Lunhandled; | ||
607 | |||
608 | return; | ||
609 | |||
610 | Lunhandled: | ||
611 | dump_intsts(buffer, sizeof buffer, sts); | ||
612 | panicf("unhandled usb int: %lx (%s)", sts, buffer); | ||
613 | |||
614 | Lerr: | ||
615 | dump_intsts(buffer, sizeof buffer, sts); | ||
616 | panicf("error in usb int: %lx (%s)", sts, buffer); | ||
479 | } | 617 | } |
480 | 618 | ||
481 | /* (not essential? , not implemented in usb-tcc.c) */ | ||
482 | void usb_drv_set_test_mode(int mode) | 619 | void usb_drv_set_test_mode(int mode) |
483 | { | 620 | { |
484 | (void) mode; | 621 | (void) mode; |
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.h b/firmware/target/arm/as3525/usb-drv-as3525v2.h index 4d312a833e..e2932d0dd6 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.h +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.h | |||
@@ -54,22 +54,25 @@ | |||
54 | /** Device IN Endpoint Transmit FIFO (ep) Size Register */ | 54 | /** Device IN Endpoint Transmit FIFO (ep) Size Register */ |
55 | #define USB_DIEPTXFSIZ(ep) (*(volatile unsigned long *)(USB_BASE + 0x100 + 4 * (ep))) | 55 | #define USB_DIEPTXFSIZ(ep) (*(volatile unsigned long *)(USB_BASE + 0x100 + 4 * (ep))) |
56 | 56 | ||
57 | /** Build the content of a FIFO size register like USB_DIEPTXFSIZ(i) and USB_GNPTXFSIZ*/ | ||
57 | #define USB_MAKE_FIFOSIZE_DATA(startadr, depth) \ | 58 | #define USB_MAKE_FIFOSIZE_DATA(startadr, depth) \ |
58 | (((startadr) & 0xffff) | ((depth) << 16)) | 59 | (((startadr) & 0xffff) | ((depth) << 16)) |
59 | 60 | ||
61 | /** Retrieve fifo size for such registers */ | ||
60 | #define USB_GET_FIFOSIZE_DEPTH(data) \ | 62 | #define USB_GET_FIFOSIZE_DEPTH(data) \ |
61 | ((data) >> 16) | 63 | ((data) >> 16) |
62 | 64 | ||
65 | /** Retrieve fifo start address for such registers */ | ||
63 | #define USB_GET_FIFOSIZE_START_ADR(data) \ | 66 | #define USB_GET_FIFOSIZE_START_ADR(data) \ |
64 | ((data) & 0xffff) | 67 | ((data) & 0xffff) |
65 | 68 | ||
66 | #define USB_GRSTCTL_csftrst (1 << 0) /** Core soft reset */ | 69 | #define USB_GRSTCTL_csftrst (1 << 0) /** Core soft reset */ |
67 | #define USB_GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */ | 70 | #define USB_GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */ |
68 | #define USB_GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */ | 71 | #define USB_GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */ |
72 | #define USB_GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */ | ||
73 | #define USB_GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */ | ||
69 | #define USB_GRSTCTL_txfnum_bit_pos 6 /** TxFIFO Number */ | 74 | #define USB_GRSTCTL_txfnum_bit_pos 6 /** TxFIFO Number */ |
70 | #define USB_GRSTCTL_txfnum_bits (0x1f << 6) | 75 | #define USB_GRSTCTL_txfnum_bits (0x1f << 6) |
71 | #define USB_GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */ | ||
72 | #define USB_GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */ | ||
73 | #define USB_GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/ | 76 | #define USB_GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/ |
74 | 77 | ||
75 | #define USB_GHWCFG1_IN_EP(ep) ((USB_GHWCFG1 >> ((ep) *2)) & 0x1) /** 1 if EP(ep) has in cap */ | 78 | #define USB_GHWCFG1_IN_EP(ep) ((USB_GHWCFG1 >> ((ep) *2)) & 0x1) /** 1 if EP(ep) has in cap */ |
@@ -81,59 +84,75 @@ | |||
81 | #define USB_GHWCFG2_NUM_EP ((USB_GHWCFG2 >> 10) & 0xf) /** Number of endpoints */ | 84 | #define USB_GHWCFG2_NUM_EP ((USB_GHWCFG2 >> 10) & 0xf) /** Number of endpoints */ |
82 | #define USB_GHWCFG2_DYN_FIFO ((USB_GHWCFG2 >> 19) & 0x1) /** Dynamic FIFO */ | 85 | #define USB_GHWCFG2_DYN_FIFO ((USB_GHWCFG2 >> 19) & 0x1) /** Dynamic FIFO */ |
83 | 86 | ||
87 | /* For USB_GHWCFG2_HS_PHY_TYPE and USB_GHWCFG2_SS_PHY_TYPE */ | ||
84 | #define USB_PHY_TYPE_UNSUPPORTED 0 | 88 | #define USB_PHY_TYPE_UNSUPPORTED 0 |
85 | #define USB_PHY_TYPE_UTMI 1 | 89 | #define USB_PHY_TYPE_UTMI 1 |
86 | #define USB_INT_DMA_ARCH 2 | 90 | #define USB_INT_DMA_ARCH 2 |
87 | 91 | ||
88 | #define USB_GHWCFG3_DFIFO_LEN (USB_GHWCFG3 >> 16) /** Total fifo size */ | 92 | #define USB_GHWCFG3_DFIFO_LEN (USB_GHWCFG3 >> 16) /** Total fifo size */ |
89 | 93 | ||
90 | #define USB_GHWCFG4_UTMI_PHY_DATA_WIDTH ((USB_GHWCFG4 >> 14) & 0x3) | 94 | #define USB_GHWCFG4_UTMI_PHY_DATA_WIDTH ((USB_GHWCFG4 >> 14) & 0x3) /** UTMI+ data bus width (format is unsure) */ |
91 | #define USB_GHWCFG4_DED_FIFO_EN ((USB_GHWCFG4 >> 25) & 0x1) | 95 | #define USB_GHWCFG4_DED_FIFO_EN ((USB_GHWCFG4 >> 25) & 0x1) /** Dedicated Tx FIFOs */ |
92 | #define USB_GHWCFG4_NUM_IN_EP ((USB_GHWCFG4 >> 26) & 0xf) /** Number of IN endpoints */ | 96 | #define USB_GHWCFG4_NUM_IN_EP ((USB_GHWCFG4 >> 26) & 0xf) /** Number of IN endpoints */ |
93 | 97 | ||
94 | #define USB_GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */ | 98 | #define USB_GUSBCFG_toutcal_bit_pos 0 |
99 | #define USB_GUSBCFG_toutcal_bits (0x7 << USB_GUSBCFG_toutcal_bit_pos) | ||
95 | #define USB_GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */ | 100 | #define USB_GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */ |
96 | #define USB_GUSBCFG_SRP_cap 0x100 | 101 | #define USB_GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */ |
97 | #define USB_GUSBCFG_HNP_cap 0x200 | 102 | #define USB_GUSBCFG_fsintf (1 << 5) |
103 | #define USB_GUSBCFG_physel (1 << 6) | ||
104 | #define USB_GUSBCFG_ddrsel (1 << 7) | ||
105 | #define USB_GUSBCFG_srpcap (1 << 8) | ||
106 | #define USB_GUSBCFG_hnpcapp (1 << 9) | ||
107 | #define USB_GUSBCFG_usbtrdtim_bit_pos 10 | ||
108 | #define USB_GUSBCFG_usbtrdtim_bits (0xf << USB_GUSBCFG_usbtrdtim_bit_pos) | ||
109 | #define USB_GUSBCFG_nptxfrwnden (1 << 14) | ||
110 | #define USB_GUSBCFG_phylpwrclksel (1 << 15) | ||
111 | #define USB_GUSBCFG_otgutmifssel (1 << 16) | ||
112 | #define USB_GUSBCFG_ulpi_fsls (1 << 17) | ||
113 | #define USB_GUSBCFG_ulpi_auto_res (1 << 18) | ||
114 | #define USB_GUSBCFG_ulpi_clk_sus_m (1 << 19) | ||
115 | #define USB_GUSBCFG_ulpi_ext_vbus_drv (1 << 20) | ||
116 | #define USB_GUSBCFG_ulpi_int_vbus_indicator (1 << 21) | ||
117 | #define USB_GUSBCFG_term_sel_dl_pulse (1 << 22) | ||
118 | #define USB_GUSBCFG_force_host_mode (1 << 29) | ||
119 | #define USB_GUSBCFG_force_device_mode (1 << 30) | ||
120 | #define USB_GUSBCFG_corrupt_tx_packet (1 << 31) | ||
98 | 121 | ||
99 | #define USB_GAHBCFG_glblintrmsk (1 << 0) | 122 | #define USB_GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */ |
100 | #define USB_GAHBCFG_hburstlen_bit_pos 1 | 123 | #define USB_GAHBCFG_hburstlen_bit_pos 1 |
101 | #define USB_GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */ | 124 | #define USB_GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */ |
102 | #define USB_GAHBCFG_dma_enable (1 << 5) | 125 | #define USB_GAHBCFG_dma_enable (1 << 5) /** Enable DMA */ |
103 | 126 | ||
104 | #define USB_GINTMSK_usb_rst 0x00001000 /*!< USB Reset Mask */ | 127 | /* NOTE: USB_GINTSTS bits are the same as in USB_GINTMSK plus the following one */ |
105 | #define USB_GINTMSK_EnumDone 0x00000200 /*!< Enumeration Done Mask */ | 128 | #define USB_GINTSTS_curmode (1 << 0) /** Current mode: 1 for host, 0 for device */ |
106 | #define USB_GINTMSK_ErlySusp 0x00000400 /*!< Early Suspend Mask */ | 129 | |
107 | #define USB_GINTMSK_USBSusp 0x00000800 /*!< USB Suspend Mask */ | 130 | #define USB_GINTMSK_modemismatch (1 << 1) /** mode mismatch ? */ |
108 | #define USB_GINTMSK_SOF 0x00000008 /*!< Start of (micro)Frame Mask */ | ||
109 | #define USB_GINTMSK_NPTxFEmp 0x00000020 /*!< Non-periodic TxFIFO Empty Mask */ | ||
110 | |||
111 | #define USB_GINTMSK_wkupintr (1 << 31) | ||
112 | #define USB_GINTMSK_sessreqintr (1 << 30) | ||
113 | #define USB_GINTMSK_disconnect (1 << 29) | ||
114 | #define USB_GINTMSK_conidstschng (1 << 28) | ||
115 | #define USB_GINTMSK_ptxfempty (1 << 26) | ||
116 | #define USB_GINTMSK_hcintr (1 << 25) | ||
117 | #define USB_GINTMSK_portintr (1 << 24) | ||
118 | #define USB_GINTMSK_incomplisoout (1 << 21) | ||
119 | #define USB_GINTMSK_incomplisoin (1 << 20) | ||
120 | #define USB_GINTMSK_outepintr (1 << 19) | ||
121 | #define USB_GINTMSK_inepintr (1 << 18) | ||
122 | #define USB_GINTMSK_epmismatch (1 << 17) | ||
123 | #define USB_GINTMSK_eopframe (1 << 15) | ||
124 | #define USB_GINTMSK_isooutdrop (1 << 14) | ||
125 | #define USB_GINTMSK_enumdone (1 << 13) | ||
126 | #define USB_GINTMSK_usbreset (1 << 12) | ||
127 | #define USB_GINTMSK_usbsuspend (1 << 11) | ||
128 | #define USB_GINTMSK_erlysuspend (1 << 10) | ||
129 | #define USB_GINTMSK_i2cintr (1 << 9) | ||
130 | #define USB_GINTMSK_goutnakeff (1 << 7) | ||
131 | #define USB_GINTMSK_ginnakeff (1 << 6) | ||
132 | #define USB_GINTMSK_nptxfempty (1 << 5) | ||
133 | #define USB_GINTMSK_rxstsqlvl (1 << 4) | ||
134 | #define USB_GINTMSK_sofintr (1 << 3) | ||
135 | #define USB_GINTMSK_otgintr (1 << 2) | 131 | #define USB_GINTMSK_otgintr (1 << 2) |
136 | #define USB_GINTMSK_modemismatch (1 << 1) | 132 | #define USB_GINTMSK_sofintr (1 << 3) |
133 | #define USB_GINTMSK_rxstsqlvl (1 << 4) | ||
134 | #define USB_GINTMSK_nptxfempty (1 << 5) /** Non-periodic TX fifo empty ? */ | ||
135 | #define USB_GINTMSK_ginnakeff (1 << 6) | ||
136 | #define USB_GINTMSK_goutnakeff (1 << 7) | ||
137 | #define USB_GINTMSK_i2cintr (1 << 9) | ||
138 | #define USB_GINTMSK_erlysuspend (1 << 10) | ||
139 | #define USB_GINTMSK_usbsuspend (1 << 11) /** USB suspend */ | ||
140 | #define USB_GINTMSK_usbreset (1 << 12) /** USB reset */ | ||
141 | #define USB_GINTMSK_enumdone (1 << 13) /** Enumeration done */ | ||
142 | #define USB_GINTMSK_isooutdrop (1 << 14) | ||
143 | #define USB_GINTMSK_eopframe (1 << 15) | ||
144 | #define USB_GINTMSK_epmismatch (1 << 17) /** endpoint mismatch ? */ | ||
145 | #define USB_GINTMSK_inepintr (1 << 18) /** in pending ? */ | ||
146 | #define USB_GINTMSK_outepintr (1 << 19) /** out pending ? */ | ||
147 | #define USB_GINTMSK_incomplisoin (1 << 20) /** ISP in complete ? */ | ||
148 | #define USB_GINTMSK_incomplisoout (1 << 21) /** ISO out complete ? */ | ||
149 | #define USB_GINTMSK_portintr (1 << 24) /** Port status change ? */ | ||
150 | #define USB_GINTMSK_hcintr (1 << 25) | ||
151 | #define USB_GINTMSK_ptxfempty (1 << 26) /** Periodic TX fifof empty ? */ | ||
152 | #define USB_GINTMSK_conidstschng (1 << 28) | ||
153 | #define USB_GINTMSK_disconnect (1 << 29) /** Disconnect */ | ||
154 | #define USB_GINTMSK_sessreqintr (1 << 30) /** Session request */ | ||
155 | #define USB_GINTMSK_wkupintr (1 << 31) /** Wake up */ | ||
137 | 156 | ||
138 | /** | 157 | /** |
139 | * Device Registers Base Addresses | 158 | * Device Registers Base Addresses |
@@ -157,9 +176,25 @@ | |||
157 | #define USB_DTKNQR4 (*(volatile unsigned long *)(USB_DEVICE + 0x34)) /** Device IN Token Queue Read Register 4 (RO) */ | 176 | #define USB_DTKNQR4 (*(volatile unsigned long *)(USB_DEVICE + 0x34)) /** Device IN Token Queue Read Register 4 (RO) */ |
158 | #define USB_FFEMPTYMSK (*(volatile unsigned long *)(USB_DEVICE + 0x34)) /** Device IN EPs empty Inr. Mask Register */ | 177 | #define USB_FFEMPTYMSK (*(volatile unsigned long *)(USB_DEVICE + 0x34)) /** Device IN EPs empty Inr. Mask Register */ |
159 | 178 | ||
160 | #define USB_DCFG_devspd_bits 0x3 | 179 | #define USB_DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */ |
180 | #define USB_DCTL_sftdiscon (1 << 1) /** Soft Disconnect */ | ||
181 | #define USB_DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */ | ||
182 | #define USB_DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */ | ||
183 | #define USB_DCTL_tstctl_bit_pos 4 /** Test Control */ | ||
184 | #define USB_DCTL_tstctl_bits (0x7 << USB_DCTL_tstctl_bit_pos) | ||
185 | #define USB_DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */ | ||
186 | #define USB_DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */ | ||
187 | #define USB_DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */ | ||
188 | #define USB_DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */ | ||
189 | /* "documented" in usb_constants.h only */ | ||
190 | #define USB_DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */ | ||
191 | |||
192 | #define USB_DCFG_devspd_bits 0x3 /** Device Speed */ | ||
161 | #define USB_DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */ | 193 | #define USB_DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */ |
162 | #define USB_DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */ | 194 | #define USB_DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */ |
195 | #define USB_DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */ | ||
196 | #define USB_DCFG_devadr_bit_pos 4 /** Device Address */ | ||
197 | #define USB_DCFG_devadr_bits (0x7f << USB_DCFG_devadr_bit_pos) | ||
163 | #define USB_DCFG_perfrint_bit_pos 11 /** Periodic Frame Interval */ | 198 | #define USB_DCFG_perfrint_bit_pos 11 /** Periodic Frame Interval */ |
164 | #define USB_DCFG_perfrint_bits (0x3 << USB_DCFG_perfrint_bit_pos) | 199 | #define USB_DCFG_perfrint_bits (0x3 << USB_DCFG_perfrint_bit_pos) |
165 | #define USB_DCFG_FRAME_INTERVAL_80 0 | 200 | #define USB_DCFG_FRAME_INTERVAL_80 0 |
@@ -167,6 +202,17 @@ | |||
167 | #define USB_DCFG_FRAME_INTERVAL_90 2 | 202 | #define USB_DCFG_FRAME_INTERVAL_90 2 |
168 | #define USB_DCFG_FRAME_INTERVAL_95 3 | 203 | #define USB_DCFG_FRAME_INTERVAL_95 3 |
169 | 204 | ||
205 | #define USB_DSTS_suspsts (1 << 0) /** Suspend status */ | ||
206 | #define USB_DSTS_enumspd_bit_pos 1 /** Enumerated speed */ | ||
207 | #define USB_DSTS_enumspd_bits (0x3 << USB_DSTS_enumspd_bit_pos) | ||
208 | #define USB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 | ||
209 | #define USB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 | ||
210 | #define USB_DSTS_ENUMSPD_LS_PHY_6MHZ 2 | ||
211 | #define USB_DSTS_ENUMSPD_FS_PHY_48MHZ 3 | ||
212 | #define USB_DSTS_errticerr (1 << 3) /** Erratic errors ? */ | ||
213 | #define USB_DSTS_soffn_bit_pos 7 /** Frame or Microframe Number of the received SOF */ | ||
214 | #define USB_DSTS_soffn_bits (0x3fff << USB_DSTS_soffn_bit_pos) | ||
215 | |||
170 | #define USB_DTHRCTL_non_iso_thr_en (1 << 0) | 216 | #define USB_DTHRCTL_non_iso_thr_en (1 << 0) |
171 | #define USB_DTHRCTL_iso_thr_en (1 << 1) | 217 | #define USB_DTHRCTL_iso_thr_en (1 << 1) |
172 | #define USB_DTHRCTL_tx_thr_len_bit_pos 2 | 218 | #define USB_DTHRCTL_tx_thr_len_bit_pos 2 |
@@ -198,6 +244,13 @@ | |||
198 | #define USB_DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */ | 244 | #define USB_DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */ |
199 | #define USB_DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */ | 245 | #define USB_DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */ |
200 | 246 | ||
247 | /* the following also apply to DOEPMSK */ | ||
248 | #define USB_DOEPINT_xfercompl (1 << 0) /** Transfer complete */ | ||
249 | #define USB_DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */ | ||
250 | #define USB_DOEPINT_ahberr (1 << 2) /** AHB error */ | ||
251 | #define USB_DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/ | ||
252 | |||
253 | /* 0<=ep<=15, you can use ep=0 */ | ||
201 | /** Device OUT Endpoint (ep) Control Register */ | 254 | /** Device OUT Endpoint (ep) Control Register */ |
202 | #define USB_DOEPCTL(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20)) | 255 | #define USB_DOEPCTL(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20)) |
203 | /** Device OUT Endpoint (ep) Frame number Register */ | 256 | /** Device OUT Endpoint (ep) Frame number Register */ |
@@ -209,27 +262,106 @@ | |||
209 | /** Device Endpoint (ep) DMA Address Register */ | 262 | /** Device Endpoint (ep) DMA Address Register */ |
210 | #define USB_DOEPDMA(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20 + 0x14)) | 263 | #define USB_DOEPDMA(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20 + 0x14)) |
211 | 264 | ||
212 | #define USB_PCGCCTL (*(volatile unsigned long *)(USB_BASE + 0xE00)) /** Power and Clock Gating Control Register */ | 265 | #define USB_PCGCCTL (*(volatile unsigned long *)(USB_BASE + 0xE00)) /** Power and Clock Gating Control Register */ |
266 | |||
267 | |||
268 | /** Maximum Packet Size | ||
269 | * IN/OUT EPn | ||
270 | * IN/OUT EP0 - 2 bits | ||
271 | * 2'b00: 64 Bytes | ||
272 | * 2'b01: 32 | ||
273 | * 2'b10: 16 | ||
274 | * 2'b11: 8 */ | ||
275 | #define USB_DEPCTL_mps_bits 0x7ff | ||
276 | #define USB_DEPCTL_mps_bit_pos 0 | ||
277 | #define USB_DEPCTL_MPS_64 0 | ||
278 | #define USB_DEPCTL_MPS_32 1 | ||
279 | #define USB_DEPCTL_MPS_16 2 | ||
280 | #define USB_DEPCTL_MPS_8 3 | ||
281 | /** Next Endpoint | ||
282 | * IN EPn/IN EP0 | ||
283 | * OUT EPn/OUT EP0 - reserved */ | ||
284 | #define USB_DEPCTL_nextep_bit_pos 11 | ||
285 | #define USB_DEPCTL_nextep_bits (0xf << USB_DEPCTL_nextep_bit_pos) | ||
286 | #define USB_DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */ | ||
287 | /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) | ||
288 | * This field contains the PID of the packet going to | ||
289 | * be received or transmitted on this endpoint. The | ||
290 | * application should program the PID of the first | ||
291 | * packet going to be received or transmitted on this | ||
292 | * endpoint , after the endpoint is | ||
293 | * activated. Application use the SetD1PID and | ||
294 | * SetD0PID fields of this register to program either | ||
295 | * D0 or D1 PID. | ||
296 | * | ||
297 | * The encoding for this field is | ||
298 | * - 0: D0 | ||
299 | * - 1: D1 | ||
300 | */ | ||
301 | #define USB_DEPCTL_dpid (1 << 16) | ||
302 | #define USB_DEPCTL_naksts (1 << 17) /** NAK Status */ | ||
303 | /** Endpoint Type | ||
304 | * 2'b00: Control | ||
305 | * 2'b01: Isochronous | ||
306 | * 2'b10: Bulk | ||
307 | * 2'b11: Interrupt */ | ||
308 | #define USB_DEPCTL_eptype_bit_pos 18 | ||
309 | #define USB_DEPCTL_eptype_bits (0x3 << USB_DEPCTL_eptype_bit_pos) | ||
310 | /** Snoop Mode | ||
311 | * OUT EPn/OUT EP0 | ||
312 | * IN EPn/IN EP0 - reserved */ | ||
313 | #define USB_DEPCTL_snp (1 << 20) | ||
314 | #define USB_DEPCTL_stall (1 << 21) /** Stall Handshake */ | ||
315 | /** Tx Fifo Number | ||
316 | * IN EPn/IN EP0 | ||
317 | * OUT EPn/OUT EP0 - reserved */ | ||
318 | #define USB_DEPCTL_txfnum_bit_pos 22 | ||
319 | #define USB_DEPCTL_txfnum_bits (0xf << USB_DEPCTL_txfnum_bit_pos) | ||
320 | |||
321 | #define USB_DEPCTL_cnak (1 << 26) /** Clear NAK */ | ||
322 | #define USB_DEPCTL_snak (1 << 27) /** Set NAK */ | ||
323 | /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) | ||
324 | * Writing to this field sets the Endpoint DPID (DPID) | ||
325 | * field in this register to DATA0. Set Even | ||
326 | * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) | ||
327 | * Writing to this field sets the Even/Odd | ||
328 | * (micro)frame (EO_FrNum) field to even (micro) | ||
329 | * frame. | ||
330 | */ | ||
331 | #define USB_DEPCTL_setd0pid (1 << 28) | ||
332 | /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) | ||
333 | * Writing to this field sets the Endpoint DPID (DPID) | ||
334 | * field in this register to DATA1 Set Odd | ||
335 | * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) | ||
336 | * Writing to this field sets the Even/Odd | ||
337 | * (micro)frame (EO_FrNum) field to odd (micro) frame. | ||
338 | */ | ||
339 | #define USB_DEPCTL_setd1pid (1 << 29) | ||
340 | #define USB_DEPCTL_epdis (1 << 30) /** Endpoint disable */ | ||
341 | #define USB_DEPCTL_epena (1 << 31) /** Endpoint enable */ | ||
342 | |||
343 | |||
344 | /* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */ | ||
345 | #define USB_DEPTSIZ_xfersize_bits 0x7ffff /** Transfer Size */ | ||
346 | #define USB_DEPTSIZ_pkcnt_bit_pos 19 /** Packet Count */ | ||
347 | #define USB_DEPTSIZ_pkcnt_bits (0x3ff << USB_DEPTSIZ_pkcnt_bit_pos) | ||
348 | #define USB_DEPTSIZ_mc_bit_pos 29 /** Multi Count - Periodic IN endpoints */ | ||
349 | #define USB_DEPTSIZ_mc_bits (0x3 << USB_DEPTSIZ_mc_bit_pos) | ||
350 | |||
351 | /* idem but for i=0 */ | ||
352 | #define USB_DEPTSIZ0_xfersize_bits 0x7f /** Transfer Size */ | ||
353 | #define USB_DEPTSIZ0_pkcnt_bit_pos 19 /** Packet Count */ | ||
354 | #define USB_DEPTSIZ0_pkcnt_bits (0x1 << USB_DEPTSIZ0_pkcnt_bit_pos) | ||
355 | #define USB_DEPTSIZ0_supcnt_bit_pos 29 /** Setup Packet Count (DOEPTSIZ0 Only) */ | ||
356 | #define USB_DEPTSIZ0_supcnt_bits (0x3 << USB_DEPTSIZ0_supcnt_bit_pos) | ||
213 | 357 | ||
214 | #define USB_DEPCTL_epena (1 << 31) /** Endpoint enable */ | 358 | /* valid for USB_DAINT and USB_DAINTMSK, for 0<=ep<=15 */ |
215 | #define USB_DEPCTL_epdis (1 << 30) /** Endpoint disable */ | 359 | #define USB_DAINT_IN_EP(i) (1 << (i)) |
216 | #define USB_DEPCTL_snak (1 << 27) /** Set NAK */ | 360 | #define USB_DAINT_OUT_EP(i) (1 << ((i) + 16)) |
217 | #define USB_DEPCTL_cnak (1 << 28) /** Clear NAK */ | ||
218 | 361 | ||
219 | /** | 362 | /** |
220 | * Parameters | 363 | * Parameters |
221 | */ | 364 | */ |
222 | #ifdef USB_USE_CUSTOM_FIFO_LAYOUT | ||
223 | /* Data fifo: includes RX fifo, non period TX fifo and periodic fifos | ||
224 | * NOTE: this is a hardware parameter, it cannot be changed ! */ | ||
225 | #define USB_DATA_FIFO_DEPTH 1333u | ||
226 | /* size of the FX fifo */ | ||
227 | #define USB_RX_FIFO_SIZE 256u | ||
228 | /* size of the non periodic TX fifo */ | ||
229 | #define USB_NPTX_FIFO_SIZE 256u | ||
230 | /* size of each TX ep fifo size */ | ||
231 | #define USB_EPTX_FIFO_SIZE 256u | ||
232 | #endif /* USB_USE_CUSTOM_FIFO_LAYOUT */ | ||
233 | /* Number of IN/OUT endpoints */ | 365 | /* Number of IN/OUT endpoints */ |
234 | #define USB_NUM_IN_EP 3u | 366 | #define USB_NUM_IN_EP 3u |
235 | #define USB_NUM_OUT_EP 2u | 367 | #define USB_NUM_OUT_EP 2u |