diff options
Diffstat (limited to 'firmware/target/arm/as3525')
-rw-r--r-- | firmware/target/arm/as3525/usb-drv-as3525v2.c | 70 | ||||
-rw-r--r-- | firmware/target/arm/as3525/usb-drv-as3525v2.h | 11 |
2 files changed, 58 insertions, 23 deletions
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.c b/firmware/target/arm/as3525/usb-drv-as3525v2.c index e408236b1a..8218fa4bd9 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.c +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.c | |||
@@ -81,6 +81,29 @@ static void usb_delay(void) | |||
81 | } | 81 | } |
82 | } | 82 | } |
83 | 83 | ||
84 | #if AS3525_MCLK_SEL != AS3525_CLK_PLLB | ||
85 | static inline void usb_enable_pll(void) | ||
86 | { | ||
87 | CGU_COUNTB = CGU_LOCK_CNT; | ||
88 | CGU_PLLB = AS3525_PLLB_SETTING; | ||
89 | CGU_PLLBSUP = 0; /* enable PLLB */ | ||
90 | while(!(CGU_INTCTRL & CGU_PLLB_LOCK)); /* wait until PLLB is locked */ | ||
91 | } | ||
92 | |||
93 | static inline void usb_disable_pll(void) | ||
94 | { | ||
95 | CGU_PLLBSUP = CGU_PLL_POWERDOWN; | ||
96 | } | ||
97 | #else | ||
98 | static inline void usb_enable_pll(void) | ||
99 | { | ||
100 | } | ||
101 | |||
102 | static inline void usb_disable_pll(void) | ||
103 | { | ||
104 | } | ||
105 | #endif /* AS3525_MCLK_SEL != AS3525_CLK_PLLB */ | ||
106 | |||
84 | static void as3525v2_connect(void) | 107 | static void as3525v2_connect(void) |
85 | { | 108 | { |
86 | logf("usb: init as3525v2"); | 109 | logf("usb: init as3525v2"); |
@@ -88,7 +111,15 @@ static void as3525v2_connect(void) | |||
88 | CGU_PERI |= CGU_USB_CLOCK_ENABLE; | 111 | CGU_PERI |= CGU_USB_CLOCK_ENABLE; |
89 | usb_delay(); | 112 | usb_delay(); |
90 | /* 2) enable usb phy clock */ | 113 | /* 2) enable usb phy clock */ |
91 | CGU_USB |= 0x20; | 114 | /* PHY clock */ |
115 | #if 0 | ||
116 | usb_enable_pll(); | ||
117 | CGU_USB = 1<<5 /* enable */ | ||
118 | | (CLK_DIV(AS3525_PLLB_FREQ, 48000000) / 2) << 2 | ||
119 | | 2; /* source = PLLB */ | ||
120 | #else | ||
121 | CGU_USB = 0x20; | ||
122 | #endif | ||
92 | usb_delay(); | 123 | usb_delay(); |
93 | /* 3) clear "stop pclk" */ | 124 | /* 3) clear "stop pclk" */ |
94 | PCGCCTL &= ~0x1; | 125 | PCGCCTL &= ~0x1; |
@@ -144,9 +175,8 @@ static void flush_tx_fifos(int nums) | |||
144 | { | 175 | { |
145 | unsigned int i = 0; | 176 | unsigned int i = 0; |
146 | 177 | ||
147 | GRSTCTL = (GRSTCTL & ~bitm(GRSTCTL, txfnum)) | 178 | GRSTCTL = (nums << GRSTCTL_txfnum_bitp) |
148 | | (nums << GRSTCTL_txfnum_bitp) | 179 | | GRSTCTL_txfflsh_flush; |
149 | | GRSTCTL_txfflsh_flush; | ||
150 | while(GRSTCTL & GRSTCTL_txfflsh_flush && i < 0x300) | 180 | while(GRSTCTL & GRSTCTL_txfflsh_flush && i < 0x300) |
151 | i++; | 181 | i++; |
152 | if(GRSTCTL & GRSTCTL_txfflsh_flush) | 182 | if(GRSTCTL & GRSTCTL_txfflsh_flush) |
@@ -178,8 +208,8 @@ static void reset_endpoints(void) | |||
178 | */ | 208 | */ |
179 | 209 | ||
180 | DOEPTSIZ(0) = (1 << DEPTSIZ0_supcnt_bitp) | 210 | DOEPTSIZ(0) = (1 << DEPTSIZ0_supcnt_bitp) |
181 | | (1 << DEPTSIZ0_pkcnt_bitp) | 211 | | (1 << DEPTSIZ0_pkcnt_bitp) |
182 | | 8; | 212 | | 8; |
183 | 213 | ||
184 | /* setup DMA */ | 214 | /* setup DMA */ |
185 | clean_dcache_range((void*)&ep0_setup_pkt, sizeof ep0_setup_pkt); /* force write back */ | 215 | clean_dcache_range((void*)&ep0_setup_pkt, sizeof ep0_setup_pkt); /* force write back */ |
@@ -187,11 +217,11 @@ static void reset_endpoints(void) | |||
187 | 217 | ||
188 | /* Enable endpoint, clear nak */ | 218 | /* Enable endpoint, clear nak */ |
189 | DOEPCTL(0) = DEPCTL_epena | DEPCTL_cnak | DEPCTL_usbactep | 219 | DOEPCTL(0) = DEPCTL_epena | DEPCTL_cnak | DEPCTL_usbactep |
190 | | (DEPCTL_MPS_8 << DEPCTL_mps_bitp); | 220 | | (DEPCTL_MPS_64 << DEPCTL_mps_bitp); |
191 | 221 | ||
192 | /* 64 bytes packet size, active endpoint */ | 222 | /* 64 bytes packet size, active endpoint */ |
193 | DIEPCTL(0) = (DEPCTL_MPS_8 << DEPCTL_mps_bitp) | 223 | DIEPCTL(0) = (DEPCTL_MPS_64 << DEPCTL_mps_bitp) |
194 | | DEPCTL_usbactep; | 224 | | DEPCTL_usbactep; |
195 | 225 | ||
196 | DCTL = DCTL_cgnpinnak | DCTL_cgoutnak; | 226 | DCTL = DCTL_cgnpinnak | DCTL_cgoutnak; |
197 | } | 227 | } |
@@ -236,13 +266,20 @@ static void core_dev_init(void) | |||
236 | num_out_ep = 0; | 266 | num_out_ep = 0; |
237 | for(i = 0; i < extract(GHWCFG2, num_ep); i++) | 267 | for(i = 0; i < extract(GHWCFG2, num_ep); i++) |
238 | { | 268 | { |
239 | if(GHWCFG1 & GHWCFG1_IN_EP(i)) | 269 | bool in = false, out = false; |
270 | switch((GHWCFG1 >> GHWCFG1_epdir_bitp(i)) & GHWCFG1_epdir_bits) | ||
271 | { | ||
272 | case GHWCFG1_EPDIR_BIDIR: in = out = true; break; | ||
273 | case GHWCFG1_EPDIR_IN: in = true; break; | ||
274 | case GHWCFG1_EPDIR_OUT: out = true; break; | ||
275 | default: panicf("usb: invalid epdir"); | ||
276 | } | ||
277 | /* don't count EP0 which is special and always bidirectional */ | ||
278 | if(in && i != 0) | ||
240 | num_in_ep++; | 279 | num_in_ep++; |
241 | if(GHWCFG1 & GHWCFG1_OUT_EP(i)) | 280 | if(out && i != 0) |
242 | num_out_ep++; | 281 | num_out_ep++; |
243 | logf(" EP%d: IN=%s OUT=%s", i, | 282 | logf(" EP%d: IN=%s OUT=%s", i, in ? "yes" : "no", out ? "yes" : "no"); |
244 | GHWCFG1 & GHWCFG1_IN_EP(i) ? "yes" : "no", | ||
245 | GHWCFG1 & GHWCFG1_OUT_EP(i) ? "yes" : "no"); | ||
246 | } | 283 | } |
247 | 284 | ||
248 | if(num_in_ep != extract(GHWCFG4, num_in_ep)) | 285 | if(num_in_ep != extract(GHWCFG4, num_in_ep)) |
@@ -317,8 +354,6 @@ static void core_dev_init(void) | |||
317 | logf(" rx_thr_len: %lu", extract(DTHRCTL, rx_thr_len)); | 354 | logf(" rx_thr_len: %lu", extract(DTHRCTL, rx_thr_len)); |
318 | */ | 355 | */ |
319 | 356 | ||
320 | DTHRCTL = 0; | ||
321 | |||
322 | /* enable USB interrupts */ | 357 | /* enable USB interrupts */ |
323 | enable_device_interrupts(); | 358 | enable_device_interrupts(); |
324 | } | 359 | } |
@@ -386,9 +421,6 @@ static bool handle_reset(void) | |||
386 | /* Flush FIFOs */ | 421 | /* Flush FIFOs */ |
387 | flush_tx_fifos(0x10); | 422 | flush_tx_fifos(0x10); |
388 | 423 | ||
389 | /* Flush the Learning Queue */ | ||
390 | GRSTCTL = GRSTCTL_intknqflsh; | ||
391 | |||
392 | reset_endpoints(); | 424 | reset_endpoints(); |
393 | 425 | ||
394 | /* Reset Device Address */ | 426 | /* Reset Device Address */ |
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.h b/firmware/target/arm/as3525/usb-drv-as3525v2.h index 0cd58a1544..c058b4e062 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.h +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.h | |||
@@ -169,9 +169,12 @@ | |||
169 | #define GSNPSID BASE_REG(0x040) | 169 | #define GSNPSID BASE_REG(0x040) |
170 | 170 | ||
171 | /** User HW Config1 Register */ | 171 | /** User HW Config1 Register */ |
172 | #define GHWCFG1 BASE_REG(0x044) | 172 | #define GHWCFG1 BASE_REG(0x044) |
173 | #define GHWCFG1_IN_EP(ep) (1 << (2 * (ep))) /** 1 if EP(ep) has in cap */ | 173 | #define GHWCFG1_epdir_bitp(ep) (2 * (ep)) |
174 | #define GHWCFG1_OUT_EP(ep) (1 << (1 + 2 * (ep))) /** same for out */ | 174 | #define GHWCFG1_epdir_bits 0x3 |
175 | #define GHWCFG1_EPDIR_BIDIR 0 | ||
176 | #define GHWCFG1_EPDIR_IN 1 | ||
177 | #define GHWCFG1_EPDIR_OUT 2 | ||
175 | 178 | ||
176 | /** User HW Config2 Register */ | 179 | /** User HW Config2 Register */ |
177 | #define GHWCFG2 BASE_REG(0x048) | 180 | #define GHWCFG2 BASE_REG(0x048) |
@@ -449,7 +452,7 @@ | |||
449 | /** | 452 | /** |
450 | * Parameters | 453 | * Parameters |
451 | */ | 454 | */ |
452 | #define USE_CUSTOM_FIFO_LAYOUT | 455 | //#define USE_CUSTOM_FIFO_LAYOUT |
453 | 456 | ||
454 | #ifdef USE_CUSTOM_FIFO_LAYOUT | 457 | #ifdef USE_CUSTOM_FIFO_LAYOUT |
455 | /* Data fifo: includes RX fifo, non period TX fifo and periodic fifos | 458 | /* Data fifo: includes RX fifo, non period TX fifo and periodic fifos |