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-rw-r--r--firmware/target/arm/as3525/usb-drv-as3525v2.h398
1 files changed, 5 insertions, 393 deletions
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.h b/firmware/target/arm/as3525/usb-drv-as3525v2.h
index 8a7fee15f0..7f45f52014 100644
--- a/firmware/target/arm/as3525/usb-drv-as3525v2.h
+++ b/firmware/target/arm/as3525/usb-drv-as3525v2.h
@@ -22,149 +22,12 @@
22#define __USB_DRV_AS3525v2_H__ 22#define __USB_DRV_AS3525v2_H__
23 23
24#include "as3525v2.h" 24#include "as3525v2.h"
25 25#include "usb-s3c6400x.h"
26/* All multi-bit fields in the driver use the following convention.
27 * If the register name is NAME, then there is one define NAME_bitp
28 * which holds the bit position and one define NAME_bits which holds
29 * a mask of the bits within the register (after shift).
30 * These macros allow easy access and construction of such fields */
31/* Usage:
32 * - extract(reg_name,field_name)
33 * extract a field of the register
34 * - bitm(reg_name,field_name)
35 * build a bitmask for the field
36 */
37#define extract(reg_name, field_name) \
38 ((reg_name >> reg_name##_##field_name##_bitp) & reg_name##_##field_name##_bits)
39
40#define bitm(reg_name, field_name) \
41 (reg_name##_##field_name##_bits << reg_name##_##field_name##_bitp)
42
43#define USB_DEVICE (USB_BASE + 0x0800) /** USB Device base address */
44 26
45/** 27/**
46 * Core Global Registers 28 * Registers not present in usb-s3c6400
47 */ 29 */
48#define BASE_REG(offset) (*(volatile unsigned long *)(USB_BASE + offset)) 30#define BASE_REG(offset) (*(volatile uint32_t*)(OTGBASE + offset))
49
50/** OTG Control and Status Register */
51#define GOTGCTL BASE_REG(0x000)
52
53/** OTG Interrupt Register */
54#define GOTGINT BASE_REG(0x004)
55
56/** Core AHB Configuration Register */
57#define GAHBCFG BASE_REG(0x008)
58#define GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */
59#define GAHBCFG_hburstlen_bitp 1
60#define GAHBCFG_hburstlen_bits 0xf
61#define GAHBCFG_INT_DMA_BURST_SINGLE 0
62#define GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */
63#define GAHBCFG_INT_DMA_BURST_INCR4 3
64#define GAHBCFG_INT_DMA_BURST_INCR8 5
65#define GAHBCFG_INT_DMA_BURST_INCR16 7
66#define GAHBCFG_dma_enable (1 << 5) /** Enable DMA */
67
68/** Core USB Configuration Register */
69#define GUSBCFG BASE_REG(0x00C)
70#define GUSBCFG_toutcal_bitp 0
71#define GUSBCFG_toutcal_bits 0x7
72#define GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */
73#define GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */
74#define GUSBCFG_fsintf (1 << 5)
75#define GUSBCFG_physel (1 << 6)
76#define GUSBCFG_ddrsel (1 << 7)
77#define GUSBCFG_srpcap (1 << 8)
78#define GUSBCFG_hnpcapp (1 << 9)
79#define GUSBCFG_usbtrdtim_bitp 10
80#define GUSBCFG_usbtrdtim_bits 0xf
81#define GUSBCFG_nptxfrwnden (1 << 14)
82#define GUSBCFG_phylpwrclksel (1 << 15)
83#define GUSBCFG_otgutmifssel (1 << 16)
84#define GUSBCFG_ulpi_fsls (1 << 17)
85#define GUSBCFG_ulpi_auto_res (1 << 18)
86#define GUSBCFG_ulpi_clk_sus_m (1 << 19)
87#define GUSBCFG_ulpi_ext_vbus_drv (1 << 20)
88#define GUSBCFG_ulpi_int_vbus_indicator (1 << 21)
89#define GUSBCFG_term_sel_dl_pulse (1 << 22)
90#define GUSBCFG_force_host_mode (1 << 29)
91#define GUSBCFG_force_device_mode (1 << 30)
92#define GUSBCFG_corrupt_tx_packet (1 << 31)
93
94/** Core Reset Register */
95#define GRSTCTL BASE_REG(0x010)
96#define GRSTCTL_csftrst (1 << 0) /** Core soft reset */
97#define GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */
98#define GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */
99#define GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */
100#define GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */
101#define GRSTCTL_txfnum_bitp 6 /** TxFIFO Number */
102#define GRSTCTL_txfnum_bits 0x1f
103#define GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/
104
105/** Core Interrupt Register */
106#define GINTSTS BASE_REG(0x014)
107/* NOTE: GINTSTS bits are the same as in GINTMSK plus this one */
108#define GINTSTS_curmode (1 << 0) /** Current mode, 0 for device */
109
110/** Core Interrupt Mask Register */
111#define GINTMSK BASE_REG(0x018)
112#define GINTMSK_modemismatch (1 << 1) /** mode mismatch ? */
113#define GINTMSK_otgintr (1 << 2)
114#define GINTMSK_sofintr (1 << 3)
115#define GINTMSK_rxstsqlvl (1 << 4)
116#define GINTMSK_nptxfempty (1 << 5) /** Non-periodic TX fifo empty ? */
117#define GINTMSK_ginnakeff (1 << 6)
118#define GINTMSK_goutnakeff (1 << 7)
119#define GINTMSK_i2cintr (1 << 9)
120#define GINTMSK_erlysuspend (1 << 10)
121#define GINTMSK_usbsuspend (1 << 11) /** USB suspend */
122#define GINTMSK_usbreset (1 << 12) /** USB reset */
123#define GINTMSK_enumdone (1 << 13) /** Enumeration done */
124#define GINTMSK_isooutdrop (1 << 14)
125#define GINTMSK_eopframe (1 << 15)
126#define GINTMSK_epmismatch (1 << 17) /** endpoint mismatch ? */
127#define GINTMSK_inepintr (1 << 18) /** in pending ? */
128#define GINTMSK_outepintr (1 << 19) /** out pending ? */
129#define GINTMSK_incomplisoin (1 << 20) /** ISP in complete ? */
130#define GINTMSK_incomplisoout (1 << 21) /** ISO out complete ? */
131#define GINTMSK_portintr (1 << 24) /** Port status change ? */
132#define GINTMSK_hcintr (1 << 25)
133#define GINTMSK_ptxfempty (1 << 26) /** Periodic TX fifof empty ? */
134#define GINTMSK_conidstschng (1 << 28)
135#define GINTMSK_disconnect (1 << 29) /** Disconnect */
136#define GINTMSK_sessreqintr (1 << 30) /** Session request */
137#define GINTMSK_wkupintr (1 << 31) /** Wake up */
138
139/** Receive Status Debug Read Register (Read Only) */
140#define GRXSTSR BASE_REG(0x01C)
141
142/** Receive Status Read /Pop Register (Read Only) */
143#define GRXSTSP BASE_REG(0x020)
144
145/** Receive FIFO Size Register */
146#define GRXFSIZ BASE_REG(0x024)
147
148/** Periodic Transmit FIFO Size Register */
149#define GNPTXFSIZ BASE_REG(0x028)
150
151/** Non-Periodic Transmit FIFO/Queue Status Register */
152#define GNPTXSTS BASE_REG(0x02C)
153
154/** I2C Access Register */
155#define GI2CCTL BASE_REG(0x030)
156
157/** PHY Vendor Control Register */
158#define GPVNDCTL BASE_REG(0x034)
159
160/** General Purpose Input/Output Register */
161#define GGPIO BASE_REG(0x038)
162
163/** User ID Register */
164#define GUID BASE_REG(0x03C)
165
166/** Synopsys ID Register */
167#define GSNPSID BASE_REG(0x040)
168 31
169/** User HW Config1 Register */ 32/** User HW Config1 Register */
170#define GHWCFG1 BASE_REG(0x044) 33#define GHWCFG1 BASE_REG(0x044)
@@ -203,261 +66,10 @@
203#define GHWCFG4_num_in_ep_bitp 26 /** Number of IN endpoints */ 66#define GHWCFG4_num_in_ep_bitp 26 /** Number of IN endpoints */
204#define GHWCFG4_num_in_ep_bits 0xf 67#define GHWCFG4_num_in_ep_bits 0xf
205 68
206/* 1<=ep<=15, don't use ep=0 !!! */
207/** Device IN Endpoint Transmit FIFO (ep) Size Register */
208#define DIEPTXFSIZ(ep) BASE_REG(0x100 + 4 * (ep))
209
210/** Build the content of a FIFO size register like DIEPTXFSIZ(i) and GNPTXFSIZ*/
211#define MAKE_FIFOSIZE_DATA(startadr, depth) \
212 (((startadr) & 0xffff) | ((depth) << 16))
213/** Retrieve fifo size for such registers */
214#define GET_FIFOSIZE_DEPTH(data) \
215 ((data) >> 16)
216/** Retrieve fifo start address for such registers */
217#define GET_FIFOSIZE_START_ADR(data) \
218 ((data) & 0xffff)
219
220/**
221 * Device Registers Base Addresses
222 */
223#define DEV_REG(offset) (*(volatile unsigned long *)(USB_DEVICE + offset))
224
225/** Device Configuration Register */
226#define DCFG DEV_REG(0x00)
227#define DCFG_devspd_bitp 0 /** Device Speed */
228#define DCFG_devspd_bits 0x3
229#define DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */
230#define DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */
231#define DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */
232#define DCFG_devadr_bitp 4 /** Device Address */
233#define DCFG_devadr_bits 0x7f
234#define DCFG_perfrint_bitp 11 /** Periodic Frame Interval */
235#define DCFG_perfrint_bits 0x3
236#define DCFG_FRAME_INTERVAL_80 0
237#define DCFG_FRAME_INTERVAL_85 1
238#define DCFG_FRAME_INTERVAL_90 2
239#define DCFG_FRAME_INTERVAL_95 3
240
241/** Device Control Register */
242#define DCTL DEV_REG(0x04)
243#define DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */
244#define DCTL_sftdiscon (1 << 1) /** Soft Disconnect */
245#define DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */
246#define DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */
247#define DCTL_tstctl_bitp 4 /** Test Control */
248#define DCTL_tstctl_bits 0x7
249#define DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */
250#define DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */
251#define DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */
252#define DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */
253#define DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */
254
255/** Device Status Register */
256#define DSTS DEV_REG(0x08)
257#define DSTS_suspsts (1 << 0) /** Suspend status */
258#define DSTS_enumspd_bitp 1 /** Enumerated speed */
259#define DSTS_enumspd_bits 0x3
260#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
261#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
262#define DSTS_ENUMSPD_LS_PHY_6MHZ 2
263#define DSTS_ENUMSPD_FS_PHY_48MHZ 3
264#define DSTS_errticerr (1 << 3) /** Erratic errors ? */
265#define DSTS_soffn_bitp 8 /** Frame or Microframe Number of the received SOF */
266#define DSTS_soffn_bits 0x3fff
267
268/** Device IN Endpoint Common Interrupt Mask Register */
269#define DIEPMSK DEV_REG(0x10)
270/* the following apply to DIEPMSK and DIEPINT */
271#define DIEPINT_xfercompl (1 << 0) /** Transfer complete */
272#define DIEPINT_epdisabled (1 << 1) /** Endpoint disabled */
273#define DIEPINT_ahberr (1 << 2) /** AHB error */
274#define DIEPINT_timeout (1 << 3) /** Timeout handshake (non-iso TX) */
275#define DIEPINT_intktxfemp (1 << 4) /** IN token received with tx fifo empty */
276#define DIEPINT_intknepmis (1 << 5) /** IN token received with ep mismatch */
277#define DIEPINT_inepnakeff (1 << 6) /** IN endpoint NAK effective */
278#define DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */
279#define DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */
280
281/** Device OUT Endpoint Common Interrupt Mask Register */
282#define DOEPMSK DEV_REG(0x14)
283/* the following apply to DOEPMSK and DOEPINT */
284#define DOEPINT_xfercompl (1 << 0) /** Transfer complete */
285#define DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */
286#define DOEPINT_ahberr (1 << 2) /** AHB error */
287#define DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/
288
289/** Device All Endpoints Interrupt Register */
290#define DAINT DEV_REG(0x18)
291/* valid for DAINT and DAINTMSK, for 0<=ep<=15 */
292#define DAINT_IN_EP(i) (1 << (i))
293#define DAINT_OUT_EP(i) (1 << ((i) + 16))
294
295/** Device Endpoints Interrupt Mask Register */
296#define DAINTMSK DEV_REG(0x1C)
297
298/** Device IN Token Sequence Learning Queue Read Register 1 */
299#define DTKNQR1 DEV_REG(0x20)
300
301/** Device IN Token Sequence Learning Queue Register 2 */
302#define DTKNQR2 DEV_REG(0x24)
303
304/** Device IN Token Queue Pop register */
305#define DTKNQP DEV_REG(0x28)
306
307/* fixme: those registers are not present in registers.h but are in dwc_otgh_regs.h.
308 * the previous registers exists but has a different name :( */
309/** Device VBUS discharge register*/
310#define DVBUSDIS DEV_REG(0x28)
311
312/** Device VBUS pulse register */
313#define DVBUSPULSE DEV_REG(0x2C)
314
315/** Device IN Token Queue Read Register 3 (RO) */
316#define DTKNQR3 DEV_REG(0x30)
317
318/** Device Thresholding control register */
319#define DTHRCTL DEV_REG(0x30)
320#define DTHRCTL_non_iso_thr_en (1 << 0)
321#define DTHRCTL_iso_thr_en (1 << 1)
322#define DTHRCTL_tx_thr_len_bitp 2
323#define DTHRCTL_tx_thr_len_bits 0x1FF
324#define DTHRCTL_rx_thr_en (1 << 16)
325#define DTHRCTL_rx_thr_len_bitp 17
326#define DTHRCTL_rx_thr_len_bits 0x1FF
327
328/** Device IN Token Queue Read Register 4 (RO) */
329#define DTKNQR4 DEV_REG(0x34)
330
331/** Device IN EPs empty Inr. Mask Register */
332#define FFEMPTYMSK DEV_REG(0x34)
333
334#define PCGCCTL BASE_REG(0xE00) /** Power and Clock Gating Control Register */
335
336/** Device IN Endpoint (ep) Control Register */
337#define DIEPCTL(ep) DEV_REG(0x100 + (ep) * 0x20)
338/** Device OUT Endpoint (ep) Control Register */
339#define DOEPCTL(ep) DEV_REG(0x300 + (ep) * 0x20)
340
341/** Maximum Packet Size
342 * IN/OUT EPn
343 * IN/OUT EP0 - 2 bits
344 * 2'b00: 64 Bytes
345 * 2'b01: 32
346 * 2'b10: 16
347 * 2'b11: 8 */
348#define DEPCTL_mps_bitp 0
349#define DEPCTL_mps_bits 0x7ff
350#define DEPCTL_MPS_64 0
351#define DEPCTL_MPS_32 1
352#define DEPCTL_MPS_16 2
353#define DEPCTL_MPS_8 3
354/** Next Endpoint
355 * IN EPn/IN EP0
356 * OUT EPn/OUT EP0 - reserved */
357#define DEPCTL_nextep_bitp 11
358#define DEPCTL_nextep_bits 0xf
359#define DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */
360/** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
361 * This field contains the PID of the packet going to
362 * be received or transmitted on this endpoint. The
363 * application should program the PID of the first
364 * packet going to be received or transmitted on this
365 * endpoint , after the endpoint is
366 * activated. Application use the SetD1PID and
367 * SetD0PID fields of this register to program either
368 * D0 or D1 PID.
369 *
370 * The encoding for this field is
371 * - 0: D0
372 * - 1: D1
373 */
374#define DEPCTL_dpid (1 << 16)
375#define DEPCTL_naksts (1 << 17) /** NAK Status */
376/** Endpoint Type
377 * 2'b00: Control
378 * 2'b01: Isochronous
379 * 2'b10: Bulk
380 * 2'b11: Interrupt */
381#define DEPCTL_eptype_bitp 18
382#define DEPCTL_eptype_bits 0x3
383/** Snoop Mode
384 * OUT EPn/OUT EP0
385 * IN EPn/IN EP0 - reserved */
386#define DEPCTL_snp (1 << 20)
387#define DEPCTL_stall (1 << 21) /** Stall Handshake */
388/** Tx Fifo Number
389 * IN EPn/IN EP0
390 * OUT EPn/OUT EP0 - reserved */
391#define DEPCTL_txfnum_bitp 22
392#define DEPCTL_txfnum_bits 0xf
393
394#define DEPCTL_cnak (1 << 26) /** Clear NAK */
395#define DEPCTL_snak (1 << 27) /** Set NAK */
396/** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
397 * Writing to this field sets the Endpoint DPID (DPID)
398 * field in this register to DATA0. Set Even
399 * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
400 * Writing to this field sets the Even/Odd
401 * (micro)frame (EO_FrNum) field to even (micro)
402 * frame.
403 */
404#define DEPCTL_setd0pid (1 << 28)
405/** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
406 * Writing to this field sets the Endpoint DPID (DPID)
407 * field in this register to DATA1 Set Odd
408 * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
409 * Writing to this field sets the Even/Odd
410 * (micro)frame (EO_FrNum) field to odd (micro) frame.
411 */
412#define DEPCTL_setd1pid (1 << 29)
413#define DEPCTL_epdis (1 << 30) /** Endpoint disable */
414#define DEPCTL_epena (1 << 31) /** Endpoint enable */
415
416/** Device IN Endpoint (ep) Transfer Size Register */
417#define DIEPTSIZ(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x10)
418/** Device OUT Endpoint (ep) Transfer Size Register */
419#define DOEPTSIZ(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x10)
420
421/* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */
422#define DEPTSIZ_xfersize_bitp 0 /** Transfer Size */
423#define DEPTSIZ_xfersize_bits 0x7ffff
424#define DEPTSIZ_pkcnt_bitp 19 /** Packet Count */
425#define DEPTSIZ_pkcnt_bits 0x3ff
426#define DEPTSIZ_mc_bitp 29 /** Multi Count - Periodic IN endpoints */
427#define DEPTSIZ_mc_bits 0x3
428
429/* idem but for i=0 */
430#define DEPTSIZ0_xfersize_bitp 0 /** Transfer Size */
431#define DEPTSIZ0_xfersize_bits 0x7f
432#define DEPTSIZ0_pkcnt_bitp 19 /** Packet Count */
433#define DEPTSIZ0_pkcnt_bits 0x3
434#define DEPTSIZ0_supcnt_bitp 29 /** Setup Packet Count (DOEPTSIZ0 Only) */
435#define DEPTSIZ0_supcnt_bits 0x3
436
437/** Device IN Endpoint (ep) Interrupt Register */
438#define DIEPINT(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x8)
439/** Device IN Endpoint (ep) DMA Address Register */
440#define DIEPDMA(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x14)
441/** Device IN Endpoint (ep) Transmit FIFO Status Register */ 69/** Device IN Endpoint (ep) Transmit FIFO Status Register */
442#define DTXFSTS(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x18) 70#define DTXFSTS(ep) (*((const void* volatile*)(OTGBASE + 0x918 + 0x20 * (x))))
443 71
444/** Device OUT Endpoint (ep) Frame number Register */ 72/** Device OUT Endpoint (ep) Frame number Register */
445#define DOEPFN(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x4) 73#define DOEPFN(ep) (*((const void* volatile*)(OTGBASE + 0xB04 + 0x20 * (x))))
446/** Device Endpoint (ep) Interrupt Register */
447#define DOEPINT(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x8)
448/** Device Endpoint (ep) DMA Address Register */
449#define DOEPDMA(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x14)
450
451/**
452 * Parameters
453 */
454
455/* Number of IN/OUT endpoints */
456#define NUM_IN_EP 3
457#define NUM_OUT_EP 2
458
459/* List of IN enpoints */
460#define IN_EP_LIST 1, 3, 5
461#define OUT_EP_LIST 2, 4
462 74
463#endif /* __USB_DRV_AS3525v2_H__ */ 75#endif /* __USB_DRV_AS3525v2_H__ */
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