diff options
Diffstat (limited to 'firmware/target/arm/as3525/usb-drv-as3525v2.h')
-rw-r--r-- | firmware/target/arm/as3525/usb-drv-as3525v2.h | 250 |
1 files changed, 191 insertions, 59 deletions
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.h b/firmware/target/arm/as3525/usb-drv-as3525v2.h index 4d312a833e..e2932d0dd6 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.h +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.h | |||
@@ -54,22 +54,25 @@ | |||
54 | /** Device IN Endpoint Transmit FIFO (ep) Size Register */ | 54 | /** Device IN Endpoint Transmit FIFO (ep) Size Register */ |
55 | #define USB_DIEPTXFSIZ(ep) (*(volatile unsigned long *)(USB_BASE + 0x100 + 4 * (ep))) | 55 | #define USB_DIEPTXFSIZ(ep) (*(volatile unsigned long *)(USB_BASE + 0x100 + 4 * (ep))) |
56 | 56 | ||
57 | /** Build the content of a FIFO size register like USB_DIEPTXFSIZ(i) and USB_GNPTXFSIZ*/ | ||
57 | #define USB_MAKE_FIFOSIZE_DATA(startadr, depth) \ | 58 | #define USB_MAKE_FIFOSIZE_DATA(startadr, depth) \ |
58 | (((startadr) & 0xffff) | ((depth) << 16)) | 59 | (((startadr) & 0xffff) | ((depth) << 16)) |
59 | 60 | ||
61 | /** Retrieve fifo size for such registers */ | ||
60 | #define USB_GET_FIFOSIZE_DEPTH(data) \ | 62 | #define USB_GET_FIFOSIZE_DEPTH(data) \ |
61 | ((data) >> 16) | 63 | ((data) >> 16) |
62 | 64 | ||
65 | /** Retrieve fifo start address for such registers */ | ||
63 | #define USB_GET_FIFOSIZE_START_ADR(data) \ | 66 | #define USB_GET_FIFOSIZE_START_ADR(data) \ |
64 | ((data) & 0xffff) | 67 | ((data) & 0xffff) |
65 | 68 | ||
66 | #define USB_GRSTCTL_csftrst (1 << 0) /** Core soft reset */ | 69 | #define USB_GRSTCTL_csftrst (1 << 0) /** Core soft reset */ |
67 | #define USB_GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */ | 70 | #define USB_GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */ |
68 | #define USB_GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */ | 71 | #define USB_GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */ |
72 | #define USB_GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */ | ||
73 | #define USB_GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */ | ||
69 | #define USB_GRSTCTL_txfnum_bit_pos 6 /** TxFIFO Number */ | 74 | #define USB_GRSTCTL_txfnum_bit_pos 6 /** TxFIFO Number */ |
70 | #define USB_GRSTCTL_txfnum_bits (0x1f << 6) | 75 | #define USB_GRSTCTL_txfnum_bits (0x1f << 6) |
71 | #define USB_GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */ | ||
72 | #define USB_GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */ | ||
73 | #define USB_GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/ | 76 | #define USB_GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/ |
74 | 77 | ||
75 | #define USB_GHWCFG1_IN_EP(ep) ((USB_GHWCFG1 >> ((ep) *2)) & 0x1) /** 1 if EP(ep) has in cap */ | 78 | #define USB_GHWCFG1_IN_EP(ep) ((USB_GHWCFG1 >> ((ep) *2)) & 0x1) /** 1 if EP(ep) has in cap */ |
@@ -81,59 +84,75 @@ | |||
81 | #define USB_GHWCFG2_NUM_EP ((USB_GHWCFG2 >> 10) & 0xf) /** Number of endpoints */ | 84 | #define USB_GHWCFG2_NUM_EP ((USB_GHWCFG2 >> 10) & 0xf) /** Number of endpoints */ |
82 | #define USB_GHWCFG2_DYN_FIFO ((USB_GHWCFG2 >> 19) & 0x1) /** Dynamic FIFO */ | 85 | #define USB_GHWCFG2_DYN_FIFO ((USB_GHWCFG2 >> 19) & 0x1) /** Dynamic FIFO */ |
83 | 86 | ||
87 | /* For USB_GHWCFG2_HS_PHY_TYPE and USB_GHWCFG2_SS_PHY_TYPE */ | ||
84 | #define USB_PHY_TYPE_UNSUPPORTED 0 | 88 | #define USB_PHY_TYPE_UNSUPPORTED 0 |
85 | #define USB_PHY_TYPE_UTMI 1 | 89 | #define USB_PHY_TYPE_UTMI 1 |
86 | #define USB_INT_DMA_ARCH 2 | 90 | #define USB_INT_DMA_ARCH 2 |
87 | 91 | ||
88 | #define USB_GHWCFG3_DFIFO_LEN (USB_GHWCFG3 >> 16) /** Total fifo size */ | 92 | #define USB_GHWCFG3_DFIFO_LEN (USB_GHWCFG3 >> 16) /** Total fifo size */ |
89 | 93 | ||
90 | #define USB_GHWCFG4_UTMI_PHY_DATA_WIDTH ((USB_GHWCFG4 >> 14) & 0x3) | 94 | #define USB_GHWCFG4_UTMI_PHY_DATA_WIDTH ((USB_GHWCFG4 >> 14) & 0x3) /** UTMI+ data bus width (format is unsure) */ |
91 | #define USB_GHWCFG4_DED_FIFO_EN ((USB_GHWCFG4 >> 25) & 0x1) | 95 | #define USB_GHWCFG4_DED_FIFO_EN ((USB_GHWCFG4 >> 25) & 0x1) /** Dedicated Tx FIFOs */ |
92 | #define USB_GHWCFG4_NUM_IN_EP ((USB_GHWCFG4 >> 26) & 0xf) /** Number of IN endpoints */ | 96 | #define USB_GHWCFG4_NUM_IN_EP ((USB_GHWCFG4 >> 26) & 0xf) /** Number of IN endpoints */ |
93 | 97 | ||
94 | #define USB_GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */ | 98 | #define USB_GUSBCFG_toutcal_bit_pos 0 |
99 | #define USB_GUSBCFG_toutcal_bits (0x7 << USB_GUSBCFG_toutcal_bit_pos) | ||
95 | #define USB_GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */ | 100 | #define USB_GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */ |
96 | #define USB_GUSBCFG_SRP_cap 0x100 | 101 | #define USB_GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */ |
97 | #define USB_GUSBCFG_HNP_cap 0x200 | 102 | #define USB_GUSBCFG_fsintf (1 << 5) |
103 | #define USB_GUSBCFG_physel (1 << 6) | ||
104 | #define USB_GUSBCFG_ddrsel (1 << 7) | ||
105 | #define USB_GUSBCFG_srpcap (1 << 8) | ||
106 | #define USB_GUSBCFG_hnpcapp (1 << 9) | ||
107 | #define USB_GUSBCFG_usbtrdtim_bit_pos 10 | ||
108 | #define USB_GUSBCFG_usbtrdtim_bits (0xf << USB_GUSBCFG_usbtrdtim_bit_pos) | ||
109 | #define USB_GUSBCFG_nptxfrwnden (1 << 14) | ||
110 | #define USB_GUSBCFG_phylpwrclksel (1 << 15) | ||
111 | #define USB_GUSBCFG_otgutmifssel (1 << 16) | ||
112 | #define USB_GUSBCFG_ulpi_fsls (1 << 17) | ||
113 | #define USB_GUSBCFG_ulpi_auto_res (1 << 18) | ||
114 | #define USB_GUSBCFG_ulpi_clk_sus_m (1 << 19) | ||
115 | #define USB_GUSBCFG_ulpi_ext_vbus_drv (1 << 20) | ||
116 | #define USB_GUSBCFG_ulpi_int_vbus_indicator (1 << 21) | ||
117 | #define USB_GUSBCFG_term_sel_dl_pulse (1 << 22) | ||
118 | #define USB_GUSBCFG_force_host_mode (1 << 29) | ||
119 | #define USB_GUSBCFG_force_device_mode (1 << 30) | ||
120 | #define USB_GUSBCFG_corrupt_tx_packet (1 << 31) | ||
98 | 121 | ||
99 | #define USB_GAHBCFG_glblintrmsk (1 << 0) | 122 | #define USB_GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */ |
100 | #define USB_GAHBCFG_hburstlen_bit_pos 1 | 123 | #define USB_GAHBCFG_hburstlen_bit_pos 1 |
101 | #define USB_GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */ | 124 | #define USB_GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */ |
102 | #define USB_GAHBCFG_dma_enable (1 << 5) | 125 | #define USB_GAHBCFG_dma_enable (1 << 5) /** Enable DMA */ |
103 | 126 | ||
104 | #define USB_GINTMSK_usb_rst 0x00001000 /*!< USB Reset Mask */ | 127 | /* NOTE: USB_GINTSTS bits are the same as in USB_GINTMSK plus the following one */ |
105 | #define USB_GINTMSK_EnumDone 0x00000200 /*!< Enumeration Done Mask */ | 128 | #define USB_GINTSTS_curmode (1 << 0) /** Current mode: 1 for host, 0 for device */ |
106 | #define USB_GINTMSK_ErlySusp 0x00000400 /*!< Early Suspend Mask */ | 129 | |
107 | #define USB_GINTMSK_USBSusp 0x00000800 /*!< USB Suspend Mask */ | 130 | #define USB_GINTMSK_modemismatch (1 << 1) /** mode mismatch ? */ |
108 | #define USB_GINTMSK_SOF 0x00000008 /*!< Start of (micro)Frame Mask */ | ||
109 | #define USB_GINTMSK_NPTxFEmp 0x00000020 /*!< Non-periodic TxFIFO Empty Mask */ | ||
110 | |||
111 | #define USB_GINTMSK_wkupintr (1 << 31) | ||
112 | #define USB_GINTMSK_sessreqintr (1 << 30) | ||
113 | #define USB_GINTMSK_disconnect (1 << 29) | ||
114 | #define USB_GINTMSK_conidstschng (1 << 28) | ||
115 | #define USB_GINTMSK_ptxfempty (1 << 26) | ||
116 | #define USB_GINTMSK_hcintr (1 << 25) | ||
117 | #define USB_GINTMSK_portintr (1 << 24) | ||
118 | #define USB_GINTMSK_incomplisoout (1 << 21) | ||
119 | #define USB_GINTMSK_incomplisoin (1 << 20) | ||
120 | #define USB_GINTMSK_outepintr (1 << 19) | ||
121 | #define USB_GINTMSK_inepintr (1 << 18) | ||
122 | #define USB_GINTMSK_epmismatch (1 << 17) | ||
123 | #define USB_GINTMSK_eopframe (1 << 15) | ||
124 | #define USB_GINTMSK_isooutdrop (1 << 14) | ||
125 | #define USB_GINTMSK_enumdone (1 << 13) | ||
126 | #define USB_GINTMSK_usbreset (1 << 12) | ||
127 | #define USB_GINTMSK_usbsuspend (1 << 11) | ||
128 | #define USB_GINTMSK_erlysuspend (1 << 10) | ||
129 | #define USB_GINTMSK_i2cintr (1 << 9) | ||
130 | #define USB_GINTMSK_goutnakeff (1 << 7) | ||
131 | #define USB_GINTMSK_ginnakeff (1 << 6) | ||
132 | #define USB_GINTMSK_nptxfempty (1 << 5) | ||
133 | #define USB_GINTMSK_rxstsqlvl (1 << 4) | ||
134 | #define USB_GINTMSK_sofintr (1 << 3) | ||
135 | #define USB_GINTMSK_otgintr (1 << 2) | 131 | #define USB_GINTMSK_otgintr (1 << 2) |
136 | #define USB_GINTMSK_modemismatch (1 << 1) | 132 | #define USB_GINTMSK_sofintr (1 << 3) |
133 | #define USB_GINTMSK_rxstsqlvl (1 << 4) | ||
134 | #define USB_GINTMSK_nptxfempty (1 << 5) /** Non-periodic TX fifo empty ? */ | ||
135 | #define USB_GINTMSK_ginnakeff (1 << 6) | ||
136 | #define USB_GINTMSK_goutnakeff (1 << 7) | ||
137 | #define USB_GINTMSK_i2cintr (1 << 9) | ||
138 | #define USB_GINTMSK_erlysuspend (1 << 10) | ||
139 | #define USB_GINTMSK_usbsuspend (1 << 11) /** USB suspend */ | ||
140 | #define USB_GINTMSK_usbreset (1 << 12) /** USB reset */ | ||
141 | #define USB_GINTMSK_enumdone (1 << 13) /** Enumeration done */ | ||
142 | #define USB_GINTMSK_isooutdrop (1 << 14) | ||
143 | #define USB_GINTMSK_eopframe (1 << 15) | ||
144 | #define USB_GINTMSK_epmismatch (1 << 17) /** endpoint mismatch ? */ | ||
145 | #define USB_GINTMSK_inepintr (1 << 18) /** in pending ? */ | ||
146 | #define USB_GINTMSK_outepintr (1 << 19) /** out pending ? */ | ||
147 | #define USB_GINTMSK_incomplisoin (1 << 20) /** ISP in complete ? */ | ||
148 | #define USB_GINTMSK_incomplisoout (1 << 21) /** ISO out complete ? */ | ||
149 | #define USB_GINTMSK_portintr (1 << 24) /** Port status change ? */ | ||
150 | #define USB_GINTMSK_hcintr (1 << 25) | ||
151 | #define USB_GINTMSK_ptxfempty (1 << 26) /** Periodic TX fifof empty ? */ | ||
152 | #define USB_GINTMSK_conidstschng (1 << 28) | ||
153 | #define USB_GINTMSK_disconnect (1 << 29) /** Disconnect */ | ||
154 | #define USB_GINTMSK_sessreqintr (1 << 30) /** Session request */ | ||
155 | #define USB_GINTMSK_wkupintr (1 << 31) /** Wake up */ | ||
137 | 156 | ||
138 | /** | 157 | /** |
139 | * Device Registers Base Addresses | 158 | * Device Registers Base Addresses |
@@ -157,9 +176,25 @@ | |||
157 | #define USB_DTKNQR4 (*(volatile unsigned long *)(USB_DEVICE + 0x34)) /** Device IN Token Queue Read Register 4 (RO) */ | 176 | #define USB_DTKNQR4 (*(volatile unsigned long *)(USB_DEVICE + 0x34)) /** Device IN Token Queue Read Register 4 (RO) */ |
158 | #define USB_FFEMPTYMSK (*(volatile unsigned long *)(USB_DEVICE + 0x34)) /** Device IN EPs empty Inr. Mask Register */ | 177 | #define USB_FFEMPTYMSK (*(volatile unsigned long *)(USB_DEVICE + 0x34)) /** Device IN EPs empty Inr. Mask Register */ |
159 | 178 | ||
160 | #define USB_DCFG_devspd_bits 0x3 | 179 | #define USB_DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */ |
180 | #define USB_DCTL_sftdiscon (1 << 1) /** Soft Disconnect */ | ||
181 | #define USB_DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */ | ||
182 | #define USB_DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */ | ||
183 | #define USB_DCTL_tstctl_bit_pos 4 /** Test Control */ | ||
184 | #define USB_DCTL_tstctl_bits (0x7 << USB_DCTL_tstctl_bit_pos) | ||
185 | #define USB_DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */ | ||
186 | #define USB_DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */ | ||
187 | #define USB_DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */ | ||
188 | #define USB_DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */ | ||
189 | /* "documented" in usb_constants.h only */ | ||
190 | #define USB_DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */ | ||
191 | |||
192 | #define USB_DCFG_devspd_bits 0x3 /** Device Speed */ | ||
161 | #define USB_DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */ | 193 | #define USB_DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */ |
162 | #define USB_DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */ | 194 | #define USB_DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */ |
195 | #define USB_DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */ | ||
196 | #define USB_DCFG_devadr_bit_pos 4 /** Device Address */ | ||
197 | #define USB_DCFG_devadr_bits (0x7f << USB_DCFG_devadr_bit_pos) | ||
163 | #define USB_DCFG_perfrint_bit_pos 11 /** Periodic Frame Interval */ | 198 | #define USB_DCFG_perfrint_bit_pos 11 /** Periodic Frame Interval */ |
164 | #define USB_DCFG_perfrint_bits (0x3 << USB_DCFG_perfrint_bit_pos) | 199 | #define USB_DCFG_perfrint_bits (0x3 << USB_DCFG_perfrint_bit_pos) |
165 | #define USB_DCFG_FRAME_INTERVAL_80 0 | 200 | #define USB_DCFG_FRAME_INTERVAL_80 0 |
@@ -167,6 +202,17 @@ | |||
167 | #define USB_DCFG_FRAME_INTERVAL_90 2 | 202 | #define USB_DCFG_FRAME_INTERVAL_90 2 |
168 | #define USB_DCFG_FRAME_INTERVAL_95 3 | 203 | #define USB_DCFG_FRAME_INTERVAL_95 3 |
169 | 204 | ||
205 | #define USB_DSTS_suspsts (1 << 0) /** Suspend status */ | ||
206 | #define USB_DSTS_enumspd_bit_pos 1 /** Enumerated speed */ | ||
207 | #define USB_DSTS_enumspd_bits (0x3 << USB_DSTS_enumspd_bit_pos) | ||
208 | #define USB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 | ||
209 | #define USB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 | ||
210 | #define USB_DSTS_ENUMSPD_LS_PHY_6MHZ 2 | ||
211 | #define USB_DSTS_ENUMSPD_FS_PHY_48MHZ 3 | ||
212 | #define USB_DSTS_errticerr (1 << 3) /** Erratic errors ? */ | ||
213 | #define USB_DSTS_soffn_bit_pos 7 /** Frame or Microframe Number of the received SOF */ | ||
214 | #define USB_DSTS_soffn_bits (0x3fff << USB_DSTS_soffn_bit_pos) | ||
215 | |||
170 | #define USB_DTHRCTL_non_iso_thr_en (1 << 0) | 216 | #define USB_DTHRCTL_non_iso_thr_en (1 << 0) |
171 | #define USB_DTHRCTL_iso_thr_en (1 << 1) | 217 | #define USB_DTHRCTL_iso_thr_en (1 << 1) |
172 | #define USB_DTHRCTL_tx_thr_len_bit_pos 2 | 218 | #define USB_DTHRCTL_tx_thr_len_bit_pos 2 |
@@ -198,6 +244,13 @@ | |||
198 | #define USB_DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */ | 244 | #define USB_DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */ |
199 | #define USB_DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */ | 245 | #define USB_DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */ |
200 | 246 | ||
247 | /* the following also apply to DOEPMSK */ | ||
248 | #define USB_DOEPINT_xfercompl (1 << 0) /** Transfer complete */ | ||
249 | #define USB_DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */ | ||
250 | #define USB_DOEPINT_ahberr (1 << 2) /** AHB error */ | ||
251 | #define USB_DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/ | ||
252 | |||
253 | /* 0<=ep<=15, you can use ep=0 */ | ||
201 | /** Device OUT Endpoint (ep) Control Register */ | 254 | /** Device OUT Endpoint (ep) Control Register */ |
202 | #define USB_DOEPCTL(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20)) | 255 | #define USB_DOEPCTL(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20)) |
203 | /** Device OUT Endpoint (ep) Frame number Register */ | 256 | /** Device OUT Endpoint (ep) Frame number Register */ |
@@ -209,27 +262,106 @@ | |||
209 | /** Device Endpoint (ep) DMA Address Register */ | 262 | /** Device Endpoint (ep) DMA Address Register */ |
210 | #define USB_DOEPDMA(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20 + 0x14)) | 263 | #define USB_DOEPDMA(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20 + 0x14)) |
211 | 264 | ||
212 | #define USB_PCGCCTL (*(volatile unsigned long *)(USB_BASE + 0xE00)) /** Power and Clock Gating Control Register */ | 265 | #define USB_PCGCCTL (*(volatile unsigned long *)(USB_BASE + 0xE00)) /** Power and Clock Gating Control Register */ |
266 | |||
267 | |||
268 | /** Maximum Packet Size | ||
269 | * IN/OUT EPn | ||
270 | * IN/OUT EP0 - 2 bits | ||
271 | * 2'b00: 64 Bytes | ||
272 | * 2'b01: 32 | ||
273 | * 2'b10: 16 | ||
274 | * 2'b11: 8 */ | ||
275 | #define USB_DEPCTL_mps_bits 0x7ff | ||
276 | #define USB_DEPCTL_mps_bit_pos 0 | ||
277 | #define USB_DEPCTL_MPS_64 0 | ||
278 | #define USB_DEPCTL_MPS_32 1 | ||
279 | #define USB_DEPCTL_MPS_16 2 | ||
280 | #define USB_DEPCTL_MPS_8 3 | ||
281 | /** Next Endpoint | ||
282 | * IN EPn/IN EP0 | ||
283 | * OUT EPn/OUT EP0 - reserved */ | ||
284 | #define USB_DEPCTL_nextep_bit_pos 11 | ||
285 | #define USB_DEPCTL_nextep_bits (0xf << USB_DEPCTL_nextep_bit_pos) | ||
286 | #define USB_DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */ | ||
287 | /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) | ||
288 | * This field contains the PID of the packet going to | ||
289 | * be received or transmitted on this endpoint. The | ||
290 | * application should program the PID of the first | ||
291 | * packet going to be received or transmitted on this | ||
292 | * endpoint , after the endpoint is | ||
293 | * activated. Application use the SetD1PID and | ||
294 | * SetD0PID fields of this register to program either | ||
295 | * D0 or D1 PID. | ||
296 | * | ||
297 | * The encoding for this field is | ||
298 | * - 0: D0 | ||
299 | * - 1: D1 | ||
300 | */ | ||
301 | #define USB_DEPCTL_dpid (1 << 16) | ||
302 | #define USB_DEPCTL_naksts (1 << 17) /** NAK Status */ | ||
303 | /** Endpoint Type | ||
304 | * 2'b00: Control | ||
305 | * 2'b01: Isochronous | ||
306 | * 2'b10: Bulk | ||
307 | * 2'b11: Interrupt */ | ||
308 | #define USB_DEPCTL_eptype_bit_pos 18 | ||
309 | #define USB_DEPCTL_eptype_bits (0x3 << USB_DEPCTL_eptype_bit_pos) | ||
310 | /** Snoop Mode | ||
311 | * OUT EPn/OUT EP0 | ||
312 | * IN EPn/IN EP0 - reserved */ | ||
313 | #define USB_DEPCTL_snp (1 << 20) | ||
314 | #define USB_DEPCTL_stall (1 << 21) /** Stall Handshake */ | ||
315 | /** Tx Fifo Number | ||
316 | * IN EPn/IN EP0 | ||
317 | * OUT EPn/OUT EP0 - reserved */ | ||
318 | #define USB_DEPCTL_txfnum_bit_pos 22 | ||
319 | #define USB_DEPCTL_txfnum_bits (0xf << USB_DEPCTL_txfnum_bit_pos) | ||
320 | |||
321 | #define USB_DEPCTL_cnak (1 << 26) /** Clear NAK */ | ||
322 | #define USB_DEPCTL_snak (1 << 27) /** Set NAK */ | ||
323 | /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) | ||
324 | * Writing to this field sets the Endpoint DPID (DPID) | ||
325 | * field in this register to DATA0. Set Even | ||
326 | * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) | ||
327 | * Writing to this field sets the Even/Odd | ||
328 | * (micro)frame (EO_FrNum) field to even (micro) | ||
329 | * frame. | ||
330 | */ | ||
331 | #define USB_DEPCTL_setd0pid (1 << 28) | ||
332 | /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) | ||
333 | * Writing to this field sets the Endpoint DPID (DPID) | ||
334 | * field in this register to DATA1 Set Odd | ||
335 | * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) | ||
336 | * Writing to this field sets the Even/Odd | ||
337 | * (micro)frame (EO_FrNum) field to odd (micro) frame. | ||
338 | */ | ||
339 | #define USB_DEPCTL_setd1pid (1 << 29) | ||
340 | #define USB_DEPCTL_epdis (1 << 30) /** Endpoint disable */ | ||
341 | #define USB_DEPCTL_epena (1 << 31) /** Endpoint enable */ | ||
342 | |||
343 | |||
344 | /* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */ | ||
345 | #define USB_DEPTSIZ_xfersize_bits 0x7ffff /** Transfer Size */ | ||
346 | #define USB_DEPTSIZ_pkcnt_bit_pos 19 /** Packet Count */ | ||
347 | #define USB_DEPTSIZ_pkcnt_bits (0x3ff << USB_DEPTSIZ_pkcnt_bit_pos) | ||
348 | #define USB_DEPTSIZ_mc_bit_pos 29 /** Multi Count - Periodic IN endpoints */ | ||
349 | #define USB_DEPTSIZ_mc_bits (0x3 << USB_DEPTSIZ_mc_bit_pos) | ||
350 | |||
351 | /* idem but for i=0 */ | ||
352 | #define USB_DEPTSIZ0_xfersize_bits 0x7f /** Transfer Size */ | ||
353 | #define USB_DEPTSIZ0_pkcnt_bit_pos 19 /** Packet Count */ | ||
354 | #define USB_DEPTSIZ0_pkcnt_bits (0x1 << USB_DEPTSIZ0_pkcnt_bit_pos) | ||
355 | #define USB_DEPTSIZ0_supcnt_bit_pos 29 /** Setup Packet Count (DOEPTSIZ0 Only) */ | ||
356 | #define USB_DEPTSIZ0_supcnt_bits (0x3 << USB_DEPTSIZ0_supcnt_bit_pos) | ||
213 | 357 | ||
214 | #define USB_DEPCTL_epena (1 << 31) /** Endpoint enable */ | 358 | /* valid for USB_DAINT and USB_DAINTMSK, for 0<=ep<=15 */ |
215 | #define USB_DEPCTL_epdis (1 << 30) /** Endpoint disable */ | 359 | #define USB_DAINT_IN_EP(i) (1 << (i)) |
216 | #define USB_DEPCTL_snak (1 << 27) /** Set NAK */ | 360 | #define USB_DAINT_OUT_EP(i) (1 << ((i) + 16)) |
217 | #define USB_DEPCTL_cnak (1 << 28) /** Clear NAK */ | ||
218 | 361 | ||
219 | /** | 362 | /** |
220 | * Parameters | 363 | * Parameters |
221 | */ | 364 | */ |
222 | #ifdef USB_USE_CUSTOM_FIFO_LAYOUT | ||
223 | /* Data fifo: includes RX fifo, non period TX fifo and periodic fifos | ||
224 | * NOTE: this is a hardware parameter, it cannot be changed ! */ | ||
225 | #define USB_DATA_FIFO_DEPTH 1333u | ||
226 | /* size of the FX fifo */ | ||
227 | #define USB_RX_FIFO_SIZE 256u | ||
228 | /* size of the non periodic TX fifo */ | ||
229 | #define USB_NPTX_FIFO_SIZE 256u | ||
230 | /* size of each TX ep fifo size */ | ||
231 | #define USB_EPTX_FIFO_SIZE 256u | ||
232 | #endif /* USB_USE_CUSTOM_FIFO_LAYOUT */ | ||
233 | /* Number of IN/OUT endpoints */ | 365 | /* Number of IN/OUT endpoints */ |
234 | #define USB_NUM_IN_EP 3u | 366 | #define USB_NUM_IN_EP 3u |
235 | #define USB_NUM_OUT_EP 2u | 367 | #define USB_NUM_OUT_EP 2u |