diff options
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/system.h | 119 |
1 files changed, 8 insertions, 111 deletions
diff --git a/firmware/export/system.h b/firmware/export/system.h index ce0c795fbd..4a33d80466 100644 --- a/firmware/export/system.h +++ b/firmware/export/system.h | |||
@@ -153,6 +153,11 @@ enum { | |||
153 | MAXMEMGUARD | 153 | MAXMEMGUARD |
154 | }; | 154 | }; |
155 | 155 | ||
156 | #ifndef SIMULATOR | ||
157 | #ifdef CPU_COLDFIRE | ||
158 | #include "system-target.h" | ||
159 | #endif | ||
160 | #endif | ||
156 | 161 | ||
157 | #if CONFIG_CPU == SH7034 | 162 | #if CONFIG_CPU == SH7034 |
158 | #define or_b(mask, address) \ | 163 | #define or_b(mask, address) \ |
@@ -176,46 +181,7 @@ enum { | |||
176 | : /* %0 */ I_CONSTRAINT((char)(mask)), \ | 181 | : /* %0 */ I_CONSTRAINT((char)(mask)), \ |
177 | /* %1 */ "z"(address-GBR)) | 182 | /* %1 */ "z"(address-GBR)) |
178 | 183 | ||
179 | #elif defined(CPU_COLDFIRE) | 184 | #endif /* CONFIG_CPU == SH7034 */ |
180 | #define or_l(mask, address) \ | ||
181 | asm \ | ||
182 | ("or.l %0,(%1)" \ | ||
183 | : \ | ||
184 | : /* %0 */ "d"(mask), \ | ||
185 | /* %1 */ "a"(address)) | ||
186 | |||
187 | #define and_l(mask, address) \ | ||
188 | asm \ | ||
189 | ("and.l %0,(%1)" \ | ||
190 | : \ | ||
191 | : /* %0 */ "d"(mask), \ | ||
192 | /* %1 */ "a"(address)) | ||
193 | |||
194 | #define eor_l(mask, address) \ | ||
195 | asm \ | ||
196 | ("eor.l %0,(%1)" \ | ||
197 | : \ | ||
198 | : /* %0 */ "d"(mask), \ | ||
199 | /* %1 */ "a"(address)) | ||
200 | |||
201 | #define EMAC_ROUND 0x10 | ||
202 | #define EMAC_FRACTIONAL 0x20 | ||
203 | #define EMAC_SATURATE 0x80 | ||
204 | |||
205 | static inline void coldfire_set_macsr(unsigned long flags) | ||
206 | { | ||
207 | asm volatile ("move.l %0, %%macsr" : : "i,r" (flags)); | ||
208 | } | ||
209 | |||
210 | static inline unsigned long coldfire_get_macsr(void) | ||
211 | { | ||
212 | unsigned long m; | ||
213 | |||
214 | asm volatile ("move.l %%macsr, %0" : "=r" (m)); | ||
215 | return m; | ||
216 | } | ||
217 | |||
218 | #endif | ||
219 | 185 | ||
220 | #ifndef SIMULATOR | 186 | #ifndef SIMULATOR |
221 | 187 | ||
@@ -272,75 +238,6 @@ static inline unsigned long swap32(unsigned long value) | |||
272 | 238 | ||
273 | #define invalidate_icache() | 239 | #define invalidate_icache() |
274 | 240 | ||
275 | #elif defined(CPU_COLDFIRE) | ||
276 | #define HIGHEST_IRQ_LEVEL (7<<8) | ||
277 | static inline int set_irq_level(int level) | ||
278 | { | ||
279 | int oldlevel; | ||
280 | /* Read the old level and set the new one */ | ||
281 | asm volatile ("move.w %%sr,%0\n" | ||
282 | "or.l #0x2000,%1\n" | ||
283 | "move.w %1,%%sr\n" : "=d" (oldlevel), "+d" (level) : ); | ||
284 | return oldlevel; | ||
285 | } | ||
286 | |||
287 | static inline unsigned short swap16(unsigned short value) | ||
288 | /* | ||
289 | result[15..8] = value[ 7..0]; | ||
290 | result[ 7..0] = value[15..8]; | ||
291 | */ | ||
292 | { | ||
293 | return (value >> 8) | (value << 8); | ||
294 | } | ||
295 | |||
296 | static inline unsigned long SWAW32(unsigned long value) | ||
297 | /* | ||
298 | result[31..16] = value[15.. 0]; | ||
299 | result[15.. 0] = value[31..16]; | ||
300 | */ | ||
301 | { | ||
302 | asm ("swap %%0" : "+r"(value)); | ||
303 | return value; | ||
304 | } | ||
305 | |||
306 | static inline unsigned long swap32(unsigned long value) | ||
307 | /* | ||
308 | result[31..24] = value[ 7.. 0]; | ||
309 | result[23..16] = value[15.. 8]; | ||
310 | result[15.. 8] = value[23..16]; | ||
311 | result[ 7.. 0] = value[31..24]; | ||
312 | */ | ||
313 | { | ||
314 | unsigned long mask = 0x00FF00FF; | ||
315 | asm ( /* val = ABCD */ | ||
316 | "and.l %[val],%[mask] \n" /* mask = .B.D */ | ||
317 | "eor.l %[mask],%[val] \n" /* val = A.C. */ | ||
318 | "lsl.l #8,%[mask] \n" /* mask = B.D. */ | ||
319 | "lsr.l #8,%[val] \n" /* val = .A.C */ | ||
320 | "or.l %[mask],%[val] \n" /* val = BADC */ | ||
321 | "swap %[val] \n" /* val = DCBA */ | ||
322 | : /* outputs */ | ||
323 | [val] "+d"(value), | ||
324 | [mask]"+d"(mask) | ||
325 | ); | ||
326 | return value; | ||
327 | } | ||
328 | |||
329 | static inline void invalidate_icache(void) | ||
330 | { | ||
331 | asm volatile ("move.l #0x01000000,%d0\n" | ||
332 | "movec.l %d0,%cacr\n" | ||
333 | "move.l #0x80000000,%d0\n" | ||
334 | "movec.l %d0,%cacr"); | ||
335 | } | ||
336 | |||
337 | #define CPUFREQ_DEFAULT_MULT 1 | ||
338 | #define CPUFREQ_DEFAULT (CPUFREQ_DEFAULT_MULT * CPU_FREQ) | ||
339 | #define CPUFREQ_NORMAL_MULT 4 | ||
340 | #define CPUFREQ_NORMAL (CPUFREQ_NORMAL_MULT * CPU_FREQ) | ||
341 | #define CPUFREQ_MAX_MULT 11 | ||
342 | #define CPUFREQ_MAX (CPUFREQ_MAX_MULT * CPU_FREQ) | ||
343 | |||
344 | #elif defined(CPU_ARM) | 241 | #elif defined(CPU_ARM) |
345 | 242 | ||
346 | /* TODO: Implement set_irq_level and check CPU frequencies */ | 243 | /* TODO: Implement set_irq_level and check CPU frequencies */ |
@@ -444,8 +341,8 @@ static inline int set_irq_level(int level) | |||
444 | { | 341 | { |
445 | int result; | 342 | int result; |
446 | __asm__ ("ld %0, 0\n\t" | 343 | __asm__ ("ld %0, 0\n\t" |
447 | "tstsr ie\n\t" | 344 | "tstsr ie\n\t" |
448 | "incc %0" : "=r"(result)); | 345 | "incc %0" : "=r"(result)); |
449 | if (level > 0) | 346 | if (level > 0) |
450 | __asm__ volatile ("clrsr ie"); | 347 | __asm__ volatile ("clrsr ie"); |
451 | else | 348 | else |