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-rw-r--r--firmware/export/config-iaudio7.h163
-rw-r--r--firmware/export/config.h1
-rw-r--r--firmware/export/hd66789r.h68
-rw-r--r--firmware/export/tcc77x.h102
-rw-r--r--firmware/export/usb-tcc7xx.h104
5 files changed, 435 insertions, 3 deletions
diff --git a/firmware/export/config-iaudio7.h b/firmware/export/config-iaudio7.h
new file mode 100644
index 0000000000..8bc73fa41c
--- /dev/null
+++ b/firmware/export/config-iaudio7.h
@@ -0,0 +1,163 @@
1/*
2 * This config file is for the Iaudio7 series
3 */
4#define TARGET_TREE /* this target is using the target tree system */
5
6/* For Rolo and boot loader */
7#define MODEL_NUMBER 32
8
9/* define this if you have recording possibility */
10#define HAVE_RECORDING
11
12/* Define bitmask of input sources - recordable bitmask can be defined
13 explicitly if different */
14#define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN | SRC_CAP_FMRADIO)
15
16/* define hardware samples rate caps mask */
17#define HW_SAMPR_CAPS (/*SAMPR_CAP_88 | */SAMPR_CAP_44/* | SAMPR_CAP_22 | SAMPR_CAP_11*/)
18
19/* define the bitmask of recording sample rates */
20#define REC_SAMPR_CAPS (SAMPR_CAP_44/* | SAMPR_CAP_22 | SAMPR_CAP_11*/)
21
22/* define this if you have a bitmap LCD display */
23#define HAVE_LCD_BITMAP
24
25/* define this if you have a colour LCD */
26#define HAVE_LCD_COLOR
27
28/* define this if you can flip your LCD */
29//#define HAVE_LCD_FLIP
30
31/* define this if you can invert the colours on your LCD */
32//#define HAVE_LCD_INVERT
33
34/* define this if you have access to the quickscreen */
35#define HAVE_QUICKSCREEN
36
37/* define this if you have access to the pitchscreen */
38#define HAVE_PITCHSCREEN
39
40/* define this if you have LCD enable function */
41#define HAVE_LCD_ENABLE
42
43/* define this if you would like tagcache to build on this target */
44#define HAVE_TAGCACHE
45
46#define HAVE_FAT16SUPPORT
47
48#if 0 /* Enable for USB driver test */
49#define HAVE_USBSTACK
50#define USE_HIGH_SPEED
51#define USB_VENDOR_ID 0x0e21
52#define USB_PRODUCT_ID 0x0750
53
54#define USB_STORAGE
55#define USB_SERIAL
56#endif
57
58/* define this if you have a flash memory storage */
59#define HAVE_FLASH_STORAGE
60
61/* LCD dimensions */
62#define LCD_WIDTH 160
63#define LCD_HEIGHT 128
64/* 16bits for now... */
65#define LCD_DEPTH 16 /* 262144 colours */
66#define LCD_PIXELFORMAT RGB565 /*rgb565*/
67
68/*#define LCD_PIXELFORMAT VERTICAL_PACKING*/
69
70/* define this to indicate your device's keypad */
71#define CONFIG_KEYPAD IAUDIO67_PAD
72
73/* #define HAVE_BUTTON_DATA */
74
75/* define this if you have a real-time clock */
76#define CONFIG_RTC RTC_PCF50606
77
78/* define this if you have RTC RAM available for settings */
79//#define HAVE_RTC_RAM
80
81/* Define this if you have a software controlled poweroff */
82#define HAVE_SW_POWEROFF
83
84/* Reduce Tremor's ICODE usage */
85#define ICODE_ATTR_TREMOR_NOT_MDCT
86
87/* The number of bytes reserved for loadable codecs */
88#define CODEC_SIZE 0x80000
89
90/* The number of bytes reserved for loadable plugins */
91#define PLUGIN_BUFFER_SIZE 0x80000
92
93#define AB_REPEAT_ENABLE 1
94
95/* Define this if you do software codec */
96#define CONFIG_CODEC SWCODEC
97
98/* The iaudio7 uses built-in WM8731 codec */
99#define HAVE_WM8731
100/* Codec is slave on serial bus */
101#define CODEC_SLAVE
102
103/* Define this if you have the TLV320 audio codec */
104//#define HAVE_TLV320
105
106/* TLV320 has no tone controls, so we use the software ones */
107//#define HAVE_SW_TONE_CONTROLS
108
109/* Define this for LCD backlight available */
110#define HAVE_BACKLIGHT
111
112#define CONFIG_I2C I2C_TCC77X
113
114#define BATTERY_CAPACITY_DEFAULT 540 /* default battery capacity */
115#define BATTERY_CAPACITY_MIN 540 /* min. capacity selectable */
116#define BATTERY_CAPACITY_MAX 540 /* max. capacity selectable */
117#define BATTERY_CAPACITY_INC 50 /* capacity increment */
118#define BATTERY_TYPES_COUNT 1 /* only one type */
119
120/* define this if the unit should not shut down on low battery. */
121#define NO_LOW_BATTERY_SHUTDOWN
122#define CONFIG_CHARGING CHARGING_SIMPLE
123
124#ifndef SIMULATOR
125
126/* Define this if you have a TCC770 */
127#define CONFIG_CPU TCC770
128
129/* Define this if you have ATA power-off control */
130#define HAVE_ATA_POWER_OFF
131
132/* Define this to the CPU frequency */
133#define CPU_FREQ 120000000
134
135/* Offset ( in the firmware file's header ) to the file length */
136//#define FIRMWARE_OFFSET_FILE_LENGTH 0
137
138/* Offset ( in the firmware file's header ) to the file CRC */
139#define FIRMWARE_OFFSET_FILE_CRC 0
140
141/* Offset ( in the firmware file's header ) to the real data */
142#define FIRMWARE_OFFSET_FILE_DATA 8
143
144/* Software controlled LED */
145#define CONFIG_LED LED_VIRTUAL
146
147#define CONFIG_LCD LCD_IAUDIO67
148
149/* FM Tuner */
150#define CONFIG_TUNER LV24020LP
151#define HAVE_TUNER_PWR_CTRL
152
153/* Define this for FM radio input available */
154#define HAVE_FMRADIO_IN
155
156#define BOOTFILE_EXT "iaudio"
157#define BOOTFILE "rockbox." BOOTFILE_EXT
158#define BOOTDIR "/"
159
160#ifdef BOOTLOADER
161#define TCCBOOT
162#endif
163#endif /* SIMULATOR */
diff --git a/firmware/export/config.h b/firmware/export/config.h
index bdf8743942..fe2cff0ea6 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -481,7 +481,6 @@
481 (((CONFIG_CPU == SH7034) && !defined(PLUGIN)) || /* SH1 archos: core only */ \ 481 (((CONFIG_CPU == SH7034) && !defined(PLUGIN)) || /* SH1 archos: core only */ \
482 defined(CPU_COLDFIRE) || /* Coldfire: core, plugins, codecs */ \ 482 defined(CPU_COLDFIRE) || /* Coldfire: core, plugins, codecs */ \
483 defined(CPU_PP) || /* PortalPlayer: core, plugins, codecs */ \ 483 defined(CPU_PP) || /* PortalPlayer: core, plugins, codecs */ \
484 defined(CPU_TCC77X) || /* Telechips: core, plugins, codecs */ \
485 (CONFIG_CPU == PNX0101) || \ 484 (CONFIG_CPU == PNX0101) || \
486 (CONFIG_CPU == S5L8700)) /* Samsung S5L8700: core, plugins, codecs */ 485 (CONFIG_CPU == S5L8700)) /* Samsung S5L8700: core, plugins, codecs */
487#define ICODE_ATTR __attribute__ ((section(".icode"))) 486#define ICODE_ATTR __attribute__ ((section(".icode")))
diff --git a/firmware/export/hd66789r.h b/firmware/export/hd66789r.h
new file mode 100644
index 0000000000..464ddbab4f
--- /dev/null
+++ b/firmware/export/hd66789r.h
@@ -0,0 +1,68 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 Vitja Makarov
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22#ifndef _HD66789R_H_
23#define _HD66789R_H_
24
25/* HD66789R registers */
26#define R_START_OSC 0x00
27#define R_DRV_OUTPUT_CONTROL 0x01
28#define R_DRV_WAVEFORM_CONTROL 0x02
29#define R_ENTRY_MODE 0x03
30#define R_COMPARE_REG1 0x04
31#define R_COMPARE_REG2 0x05
32
33#define R_DISP_CONTROL1 0x07
34#define R_DISP_CONTROL2 0x08
35#define R_DISP_CONTROL3 0x09
36
37#define R_FRAME_CYCLE_CONTROL 0x0b
38#define R_EXT_DISP_IF_CONTROL 0x0c
39
40#define R_POWER_CONTROL1 0x10
41#define R_POWER_CONTROL2 0x11
42#define R_POWER_CONTROL3 0x12
43#define R_POWER_CONTROL4 0x13
44
45#define R_RAM_ADDR_SET 0x21
46#define R_WRITE_DATA_2_GRAM 0x22
47
48#define R_GAMMA_FINE_ADJ_POS1 0x30
49#define R_GAMMA_FINE_ADJ_POS2 0x31
50#define R_GAMMA_FINE_ADJ_POS3 0x32
51#define R_GAMMA_GRAD_ADJ_POS 0x33
52
53#define R_GAMMA_FINE_ADJ_NEG1 0x34
54#define R_GAMMA_FINE_ADJ_NEG2 0x35
55#define R_GAMMA_FINE_ADJ_NEG3 0x36
56#define R_GAMMA_GRAD_ADJ_NEG 0x37
57
58#define R_GAMMA_AMP_ADJ_RES_POS 0x38
59#define R_GAMMA_AMP_AVG_ADJ_RES_NEG 0x39
60
61#define R_GATE_SCAN_POS 0x40
62#define R_VERT_SCROLL_CONTROL 0x41
63#define R_1ST_SCR_DRV_POS 0x42
64#define R_2ND_SCR_DRV_POS 0x43
65#define R_HORIZ_RAM_ADDR_POS 0x44
66#define R_VERT_RAM_ADDR_POS 0x45
67
68#endif /* _HD66789R_H_ */
diff --git a/firmware/export/tcc77x.h b/firmware/export/tcc77x.h
index b17865e257..9ff8adea3e 100644
--- a/firmware/export/tcc77x.h
+++ b/firmware/export/tcc77x.h
@@ -59,8 +59,13 @@
59#define PCLKCFG5 (*(volatile unsigned long *)0x80000430) 59#define PCLKCFG5 (*(volatile unsigned long *)0x80000430)
60#define PCLKCFG6 (*(volatile unsigned long *)0x80000434) 60#define PCLKCFG6 (*(volatile unsigned long *)0x80000434)
61 61
62#define PCLK_DAI PCLKCFG6
63
62/* Device bits for SWRESET & BCLKCTR */ 64/* Device bits for SWRESET & BCLKCTR */
63 65
66#define DEV_DAI (1<<0)
67#define DEV_USBD (1<<4)
68#define DEV_ECC (1<<9)
64#define DEV_NAND (1<<16) 69#define DEV_NAND (1<<16)
65 70
66/* ADC */ 71/* ADC */
@@ -86,9 +91,23 @@
86 91
87 92
88/* IRQ Controller */ 93/* IRQ Controller */
94#define EXT0_IRQ_MASK (1<<0)
95#define EXT1_IRQ_MASK (1<<1)
96#define EXT2_IRQ_MASK (1<<2)
97#define EXT3_IRQ_MASK (1<<3)
98#define I2SR_IRQ_MASK (1<<4)
99#define I2ST_IRQ_MASK (1<<5)
100#define TIMER0_IRQ_MASK (1<<6)
101#define USBD_IRQ_MASK (1<<8) /* USB 2.0 device */
102#define USBH_IRQ_MASK (1<<10) /* USB 1.1 host */
103#define ADC_IRQ_MASK (1<<16)
104#define USB_DMA_IRQ_MASK (1<<26) /* USB DMA */
105#define ECC_IRQ_MASK (1<<27)
106
107#define DAI_RX_IRQ_MASK I2SR_IRQ_MASK
108#define DAI_TX_IRQ_MASK I2ST_IRQ_MASK
89 109
90#define TIMER0_IRQ_MASK (1<<6) 110#define USB_DMA_IRQ_MASK (1<<26) /* USB DMA */
91#define ADC_IRQ_MASK (1<<16)
92 111
93#define IEN (*(volatile unsigned long *)0x80000100) 112#define IEN (*(volatile unsigned long *)0x80000100)
94#define CREQ (*(volatile unsigned long *)0x80000104) 113#define CREQ (*(volatile unsigned long *)0x80000104)
@@ -160,4 +179,83 @@
160#define NFC_IREQ (*(volatile unsigned long *)0x90000060) 179#define NFC_IREQ (*(volatile unsigned long *)0x90000060)
161#define NFC_RST (*(volatile unsigned long *)0x90000064) 180#define NFC_RST (*(volatile unsigned long *)0x90000064)
162 181
182
183/* ECC controller */
184
185#define ECC_CTRL (*(volatile unsigned long *)0x80000900)
186 #define ECC_DMA_REQ (1<<28)
187 #define ECC_ENC (1<<27) /* MLC ECC3/4 */
188 #define ECC_FLG (1<<26)
189 #define ECC_IEN (1<<25)
190 #define ECC_MANUAL (1<<22)
191 #define ECC_WCNT (1<<12) /* [21:12] */
192 #define ECC_HOLD (1<<7)
193 #define ECC_M4EN (1<<6)
194 #define ECC_ZERO (1<<5)
195 #define ECC_M3EN (1<<4)
196 #define ECC_CNT_MASK (7<<1)
197 #define ECC_CNT (1<<1)
198 #define ECC_SLC (1<<0)
199
200#define ECC_BASE (*(volatile unsigned long *)0x80000904)
201#define ECC_MASK (*(volatile unsigned long *)0x80000908)
202#define ECC_CLR (*(volatile unsigned long *)0x8000090c)
203#define SLC_ECC0 (*(volatile unsigned long *)0x80000910)
204#define SLC_ECC1 (*(volatile unsigned long *)0x80000914)
205#define SLC_ECC2 (*(volatile unsigned long *)0x80000918)
206#define SLC_ECC3 (*(volatile unsigned long *)0x8000091c)
207#define SLC_ECC4 (*(volatile unsigned long *)0x80000920)
208#define SLC_ECC5 (*(volatile unsigned long *)0x80000924)
209#define SLC_ECC6 (*(volatile unsigned long *)0x80000928)
210#define SLC_ECC7 (*(volatile unsigned long *)0x8000092c)
211#define MLC_ECC0W (*(volatile unsigned long *)0x80000930)
212#define MLC_ECC1W (*(volatile unsigned long *)0x80000934)
213#define MLC_ECC2W (*(volatile unsigned long *)0x80000938)
214#define MLC_ECC0R (*(volatile unsigned long *)0x80000940)
215#define MLC_ECC1R (*(volatile unsigned long *)0x80000944)
216#define MLC_ECC2R (*(volatile unsigned long *)0x80000948)
217#define ECC_CORR_START (*(volatile unsigned long *)0x8000094c)
218#define ECC_ERRADDR1 (*(volatile unsigned long *)0x80000950)
219#define ECC_ERRADDR2 (*(volatile unsigned long *)0x80000954)
220#define ECC_ERRADDR3 (*(volatile unsigned long *)0x80000958)
221#define ECC_ERRADDR4 (*(volatile unsigned long *)0x8000095c)
222#define ECC_ERRDATA1 (*(volatile unsigned long *)0x80000960)
223#define ECC_ERRDATA2 (*(volatile unsigned long *)0x80000964)
224#define ECC_ERRDATA3 (*(volatile unsigned long *)0x80000968)
225#define ECC_ERRDATA4 (*(volatile unsigned long *)0x8000096c)
226#define ECC_ERR_NUM (*(volatile unsigned long *)0x80000970)
227
228#define ECC_ERRDATA(x) (*(volatile unsigned long *)(0x80000960 + (x) * 4))
229#define ECC_ERRADDR(x) (*(volatile unsigned long *)(0x80000950 + (x) * 4))
230
231/* Digital Audio Interface */
232#define DADI_L0 (*(volatile unsigned long *)0x80000000)
233#define DADI_R0 (*(volatile unsigned long *)0x80000004)
234#define DADI_L1 (*(volatile unsigned long *)0x80000008)
235#define DADI_R1 (*(volatile unsigned long *)0x8000000C)
236#define DADI_L2 (*(volatile unsigned long *)0x80000010)
237#define DADI_R2 (*(volatile unsigned long *)0x80000014)
238#define DADI_L3 (*(volatile unsigned long *)0x80000018)
239#define DADI_R3 (*(volatile unsigned long *)0x8000001c)
240
241#define DADO_L0 (*(volatile unsigned long *)0x80000020)
242#define DADO_R0 (*(volatile unsigned long *)0x80000024)
243#define DADO_L1 (*(volatile unsigned long *)0x80000028)
244#define DADO_R1 (*(volatile unsigned long *)0x8000002C)
245#define DADO_L2 (*(volatile unsigned long *)0x80000030)
246#define DADO_R2 (*(volatile unsigned long *)0x80000034)
247#define DADO_L3 (*(volatile unsigned long *)0x80000038)
248#define DADO_R3 (*(volatile unsigned long *)0x8000003c)
249
250#define DAMR (*(volatile unsigned long *)0x80000040)
251#define DAVC (*(volatile unsigned long *)0x80000044)
252
253#define DADI_L(x) (*(volatile unsigned long *)(0x80000000 + (x) * 8))
254#define DADI_R(x) (*(volatile unsigned long *)(0x80000004 + (x) * 8))
255#define DADO_L(x) (*(volatile unsigned long *)(0x80000020 + (x) * 8))
256#define DADO_R(x) (*(volatile unsigned long *)(0x80000024 + (x) * 8))
257
258/* USB 2.0 device system MMR base address */
259#define USB_BASE 0x90000b00
260
163#endif 261#endif
diff --git a/firmware/export/usb-tcc7xx.h b/firmware/export/usb-tcc7xx.h
new file mode 100644
index 0000000000..dc091ad671
--- /dev/null
+++ b/firmware/export/usb-tcc7xx.h
@@ -0,0 +1,104 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2008 Vitja Makarov
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#ifndef USB_TCC7XX_H
22#define USB_TCC7XX_H
23
24#define MMR_REG16(base, x) (*(volatile unsigned short *) ((base) + (x)))
25
26/* USB PHY registers */
27#define TCC7xx_USB_PHY_CFG MMR_REG16(USB_BASE, 0xc4)
28 #define TCC7xx_USB_PHY_CFG_XSEL (1<<13) /* FS/HS Transceiver enable */
29 #define TCC7xx_USB_PHY_CFG_DWS (1<<6) /* Host mode */
30 #define TCC7xx_USB_PHY_XO (1<<5) /* Enable XO_OUT */
31 #define TCC7xx_USB_PHY_CKSEL_12 0
32 #define TCC7xx_USB_PHY_CKSEL_24 1
33 #define TCC7xx_USB_PHY_CKSEL_48 2
34
35/* USB 2.0 device registers */
36#define TCC7xx_USB_INDEX MMR_REG16(USB_BASE, 0x00) /* Endpoint Index register */
37#define TCC7xx_USB_EPIF MMR_REG16(USB_BASE, 0x04) /* Endpoint interrupt flag register */
38#define TCC7xx_USB_EPIE MMR_REG16(USB_BASE, 0x08) /* Endpoint interrupt enable register */
39#define TCC7xx_USB_FUNC MMR_REG16(USB_BASE, 0x0c) /* Function address register */
40#define TCC7xx_USB_EP_DIR MMR_REG16(USB_BASE, 0x14) /* Endpoint direction register */
41#define TCC7xx_USB_TST MMR_REG16(USB_BASE, 0x14) /* Test registerregister */
42#define TCC7xx_USB_SYS_STAT MMR_REG16(USB_BASE, 0x1c) /* System status register */
43 #define TCC7xx_USB_SYS_STAT_RESET (1<<0) /* Host forced reced */
44 #define TCC7xx_USB_SYS_STAT_SUSPEND (1<<1) /* Host forced suspend */
45 #define TCC7xx_USB_SYS_STAT_RESUME (1<<2) /* Host forced resume */
46 #define TCC7xx_USB_SYS_STAT_HIGH (1<<4) /* High speed */
47 #define TCC7xx_USB_SYS_STAT_VBON (1<<8)
48 #define TCC7xx_USB_SYS_STAT_VBOF (1<<9)
49 #define TCC7xx_USB_SYS_STAT_EOERR (1<<10) /* overrun error */
50 #define TCC7xx_USB_SYS_STAT_DCERR (1<<11) /* Data CRC error */
51 #define TCC7xx_USB_SYS_STAT_TCERR (1<<12) /* Token CRC error */
52 #define TCC7xx_USB_SYS_STAT_BSERR (1<<13) /* Bit-stuff error */
53 #define TCC7xx_USB_SYS_STAT_TMERR (1<<14) /* Timeout error */
54 #define TCC7xx_USB_SYS_STAT_BAERR (1<<15) /* Byte align error */
55
56#define TCC7xx_USB_SYS_STAT_ERRORS (TCC7xx_USB_SYS_STAT_EOERR | \
57 TCC7xx_USB_SYS_STAT_DCERR | \
58 TCC7xx_USB_SYS_STAT_TCERR | \
59 TCC7xx_USB_SYS_STAT_BSERR | \
60 TCC7xx_USB_SYS_STAT_TMERR | \
61 TCC7xx_USB_SYS_STAT_BAERR)
62
63#define TCC7xx_USB_SYS_CTRL MMR_REG16(USB_BASE, 0x20) /* System control register */
64 #define TCC7xx_USB_SYS_CTRL_RESET (1<<0) /* Reset enable */
65 #define TCC7xx_USB_SYS_CTRL_SUSPEND (1<<1) /* Suspend enable */
66 #define TCC7xx_USB_SYS_CTRL_RESUME (1<<2) /* Resume enable */
67 #define TCC7xx_USB_SYS_CTRL_IPS (1<<4) /* Interrupt polarity */
68 #define TCC7xx_USB_SYS_CTRL_RFRE (1<<5) /* Reverse read data enable */
69 #define TCC7xx_USB_SYS_CTRL_SPDEN (1<<6) /* Speed detection interrupt enable */
70 #define TCC7xx_USB_SYS_CTRL_BUS16 (1<<7) /* Select bus width 8/16 */
71 #define TCC7xx_USB_SYS_CTRL_EIEN (1<<8) /* Error interrupt enable */
72 #define TCC7xx_USB_SYS_CTRL_RWDE (1<<9) /* Reverse write data enable */
73 #define TCC7xx_USB_SYS_CTRL_VBONE (1<<10) /* VBus On enable */
74 #define TCC7xx_USB_SYS_CTRL_VBOFE (1<<11) /* VBus Off enable */
75 #define TCC7xx_USB_SYS_CTRL_DUAL (1<<12) /* Dual interrupt enable*/
76 #define TCC7xx_USB_SYS_CTRL_DMAZ (1<<14) /* DMA total count zero int */
77
78#define TCC7xx_USB_EP0_STAT MMR_REG16(USB_BASE, 0x24) /* EP0 status register */
79#define TCC7xx_USB_EP0_CTRL MMR_REG16(USB_BASE, 0x28) /* EP0 control register */
80
81#define TCC7xx_USB_EP0_BUF MMR_REG16(USB_BASE, 0x60) /* EP0 buffer register */
82#define TCC7xx_USB_EP1_BUF MMR_REG16(USB_BASE, 0x64) /* EP1 buffer register */
83#define TCC7xx_USB_EP2_BUF MMR_REG16(USB_BASE, 0x68) /* EP2 buffer register */
84#define TCC7xx_USB_EP3_BUF MMR_REG16(USB_BASE, 0x6c) /* EP3 buffer register */
85
86/* Indexed registers, write endpoint number to TCC7xx_USB_INDEX */
87#define TCC7xx_USB_EP_STAT MMR_REG16(USB_BASE, 0x2c) /* EP status register */
88#define TCC7xx_USB_EP_CTRL MMR_REG16(USB_BASE, 0x30) /* EP control register */
89 #define TCC7xx_USB_EP_CTRL_CDP (1 << 2) /* Clear Data PID */
90 #define TCC7xx_USB_EP_CTRL_FLUSH (1 << 6) /* Flush FIFO */
91#define TCC7xx_USB_EP_BRCR MMR_REG16(USB_BASE, 0x34) /* EP byte read count register */
92#define TCC7xx_USB_EP_BWCR MMR_REG16(USB_BASE, 0x38) /* EP byte write count register */
93#define TCC7xx_USB_EP_MAXP MMR_REG16(USB_BASE, 0x3c) /* EP max packet register */
94
95#define TCC7xx_USB_EP_DMA_CTRL MMR_REG16(USB_BASE, 0x40) /* EP DMA control register */
96#define TCC7xx_USB_EP_DMA_TCNTR MMR_REG16(USB_BASE, 0x44) /* EP DMA transfer counter register */
97#define TCC7xx_USB_EP_DMA_FCNTR MMR_REG16(USB_BASE, 0x48) /* EP DMA fifo counter register */
98#define TCC7xx_USB_EP_DMA_TTCNTR1 MMR_REG16(USB_BASE, 0x4c) /* EP DMA total trasfer counter1 register */
99#define TCC7xx_USB_EP_DMA_TTCNTR2 MMR_REG16(USB_BASE, 0x50) /* EP DMA total trasfer counter2 register */
100#define TCC7xx_USB_EP_DMA_ADDR1 MMR_REG16(USB_BASE, 0xa0) /* EP DMA MCU addr1 register */
101#define TCC7xx_USB_EP_DMA_ADDR2 MMR_REG16(USB_BASE, 0xa4) /* EP DMA MCU addr2 register */
102#define TCC7xx_USB_EP_DMA_STAT MMR_REG16(USB_BASE, 0xc0) /* EP DMA Transfer Status register */
103#define TCC7xx_USB_DELAY_CTRL MMR_REG16(USB_BASE, 0x80) /* Delay control register */
104#endif /* USB_TCC7XX_H */
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-22 23:30:58 +0000