diff options
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/config-ondavx747.h | 4 | ||||
-rw-r--r-- | firmware/export/jz4740.h | 68 |
2 files changed, 38 insertions, 34 deletions
diff --git a/firmware/export/config-ondavx747.h b/firmware/export/config-ondavx747.h index 2856e7e16d..2fe0564e71 100644 --- a/firmware/export/config-ondavx747.h +++ b/firmware/export/config-ondavx747.h | |||
@@ -158,7 +158,7 @@ | |||
158 | 158 | ||
159 | #define CONFIG_USBOTG USBOTG_JZ4740 | 159 | #define CONFIG_USBOTG USBOTG_JZ4740 |
160 | #define HAVE_USBSTACK | 160 | #define HAVE_USBSTACK |
161 | #define USB_VENDOR_ID 0x041e | 161 | #define USB_VENDOR_ID 0x07C4 |
162 | #define USB_PRODUCT_ID 0x4133 | 162 | #define USB_PRODUCT_ID 0xA4A5 |
163 | 163 | ||
164 | #endif | 164 | #endif |
diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h index e63228ff70..7fbfba283f 100644 --- a/firmware/export/jz4740.h +++ b/firmware/export/jz4740.h | |||
@@ -260,28 +260,29 @@ | |||
260 | #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) | 260 | #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) |
261 | 261 | ||
262 | /* Clock Gate Register */ | 262 | /* Clock Gate Register */ |
263 | #define CPM_CLKGR_UART1 (1 << 15) | 263 | #define CPM_CLKGR_UART1 (1 << 15) |
264 | #define CPM_CLKGR_UHC (1 << 14) | 264 | #define CPM_CLKGR_UHC (1 << 14) |
265 | #define CPM_CLKGR_IPU (1 << 13) | 265 | #define CPM_CLKGR_IPU (1 << 13) |
266 | #define CPM_CLKGR_DMAC (1 << 12) | 266 | #define CPM_CLKGR_DMAC (1 << 12) |
267 | #define CPM_CLKGR_UDC (1 << 11) | 267 | #define CPM_CLKGR_UDC (1 << 11) |
268 | #define CPM_CLKGR_LCD (1 << 10) | 268 | #define CPM_CLKGR_LCD (1 << 10) |
269 | #define CPM_CLKGR_CIM (1 << 9) | 269 | #define CPM_CLKGR_CIM (1 << 9) |
270 | #define CPM_CLKGR_SADC (1 << 8) | 270 | #define CPM_CLKGR_SADC (1 << 8) |
271 | #define CPM_CLKGR_MSC (1 << 7) | 271 | #define CPM_CLKGR_MSC (1 << 7) |
272 | #define CPM_CLKGR_AIC1 (1 << 6) | 272 | #define CPM_CLKGR_AIC1 (1 << 6) |
273 | #define CPM_CLKGR_AIC2 (1 << 5) | 273 | #define CPM_CLKGR_AIC2 (1 << 5) |
274 | #define CPM_CLKGR_SSI (1 << 4) | 274 | #define CPM_CLKGR_SSI (1 << 4) |
275 | #define CPM_CLKGR_I2C (1 << 3) | 275 | #define CPM_CLKGR_I2C (1 << 3) |
276 | #define CPM_CLKGR_RTC (1 << 2) | 276 | #define CPM_CLKGR_RTC (1 << 2) |
277 | #define CPM_CLKGR_TCU (1 << 1) | 277 | #define CPM_CLKGR_TCU (1 << 1) |
278 | #define CPM_CLKGR_UART0 (1 << 0) | 278 | #define CPM_CLKGR_UART0 (1 << 0) |
279 | 279 | ||
280 | /* Sleep Control Register */ | 280 | /* Sleep Control Register */ |
281 | #define CPM_SCR_O1ST_BIT 8 | 281 | #define CPM_SCR_O1ST_BIT 8 |
282 | #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) | 282 | #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) |
283 | #define CPM_SCR_USBHOST_SUSPEND (1 << 7) | ||
283 | #define CPM_SCR_USBPHY_ENABLE (1 << 6) | 284 | #define CPM_SCR_USBPHY_ENABLE (1 << 6) |
284 | #define CPM_SCR_OSC_ENABLE (1 << 4) | 285 | #define CPM_SCR_OSC_ENABLE (1 << 4) |
285 | 286 | ||
286 | /* Hibernate Control Register */ | 287 | /* Hibernate Control Register */ |
287 | #define CPM_HCR_PD (1 << 0) | 288 | #define CPM_HCR_PD (1 << 0) |
@@ -2419,7 +2420,7 @@ | |||
2419 | #define USB_INTR_OUTEP1 0x0002 | 2420 | #define USB_INTR_OUTEP1 0x0002 |
2420 | #define USB_INTR_OUTEP2 0x0004 | 2421 | #define USB_INTR_OUTEP2 0x0004 |
2421 | 2422 | ||
2422 | #define USB_INTR_EP(n) (n*2) | 2423 | #define USB_INTR_EP(n) ((n)==0 ? 1 : ((n)*2)) |
2423 | 2424 | ||
2424 | /* CSR0 bit masks */ | 2425 | /* CSR0 bit masks */ |
2425 | #define USB_CSR0_OUTPKTRDY 0x01 | 2426 | #define USB_CSR0_OUTPKTRDY 0x01 |
@@ -3282,56 +3283,59 @@ do { \ | |||
3282 | #define __cpm_sleep_mode() \ | 3283 | #define __cpm_sleep_mode() \ |
3283 | (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP) | 3284 | (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP) |
3284 | 3285 | ||
3285 | #define __cpm_stop_all() (REG_CPM_CLKGR = 0xffff) | 3286 | #define __cpm_stop_all() (REG_CPM_CLKGR = 0xffff) |
3286 | #define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1) | 3287 | #define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1) |
3287 | #define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC) | 3288 | #define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC) |
3288 | #define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU) | 3289 | #define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU) |
3289 | #define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC) | 3290 | #define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC) |
3290 | #define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC) | 3291 | #define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC) |
3291 | #define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD) | 3292 | #define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD) |
3292 | #define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM) | 3293 | #define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM) |
3293 | #define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC) | 3294 | #define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC) |
3294 | #define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC) | 3295 | #define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC) |
3295 | #define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1) | 3296 | #define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1) |
3296 | #define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2) | 3297 | #define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2) |
3297 | #define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI) | 3298 | #define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI) |
3298 | #define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C) | 3299 | #define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C) |
3299 | #define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC) | 3300 | #define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC) |
3300 | #define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU) | 3301 | #define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU) |
3301 | #define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0) | 3302 | #define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0) |
3302 | 3303 | ||
3303 | #define __cpm_start_all() (REG_CPM_CLKGR = 0x0) | 3304 | #define __cpm_start_all() (REG_CPM_CLKGR = 0x0) |
3304 | #define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1) | 3305 | #define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1) |
3305 | #define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC) | 3306 | #define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC) |
3306 | #define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU) | 3307 | #define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU) |
3307 | #define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC) | 3308 | #define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC) |
3308 | #define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC) | 3309 | #define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC) |
3309 | #define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD) | 3310 | #define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD) |
3310 | #define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM) | 3311 | #define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM) |
3311 | #define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC) | 3312 | #define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC) |
3312 | #define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC) | 3313 | #define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC) |
3313 | #define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1) | 3314 | #define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1) |
3314 | #define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2) | 3315 | #define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2) |
3315 | #define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI) | 3316 | #define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI) |
3316 | #define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C) | 3317 | #define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C) |
3317 | #define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC) | 3318 | #define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC) |
3318 | #define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU) | 3319 | #define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU) |
3319 | #define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0) | 3320 | #define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0) |
3320 | 3321 | ||
3321 | #define __cpm_get_o1st() \ | 3322 | #define __cpm_get_o1st() \ |
3322 | ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT) | 3323 | ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT) |
3323 | #define __cpm_set_o1st(v) \ | 3324 | #define __cpm_set_o1st(v) \ |
3324 | (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT))) | 3325 | (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT))) |
3325 | #define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND) | 3326 | #define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND) |
3327 | #define __cpm_suspend_usbhost() (REG_CPM_SCR |= CPM_SCR_USBHOST_SUSPEND) | ||
3326 | #define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE) | 3328 | #define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE) |
3327 | 3329 | ||
3328 | 3330 | ||
3331 | #define CFG_EXTAL 12000000 | ||
3332 | |||
3329 | #ifdef CFG_EXTAL | 3333 | #ifdef CFG_EXTAL |
3330 | #define JZ_EXTAL CFG_EXTAL | 3334 | #define JZ_EXTAL CFG_EXTAL |
3331 | #else | 3335 | #else |
3332 | #define JZ_EXTAL 3686400 | 3336 | #define JZ_EXTAL 3686400 |
3333 | #endif | 3337 | #endif |
3334 | #define JZ_EXTAL2 32768 /* RTC clock */ | 3338 | #define JZ_EXTAL2 32768 /* RTC clock */ |
3335 | 3339 | ||
3336 | /* PLL output frequency */ | 3340 | /* PLL output frequency */ |
3337 | static __inline__ unsigned int __cpm_get_pllout(void) | 3341 | static __inline__ unsigned int __cpm_get_pllout(void) |