diff options
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/config-h300.h | 3 | ||||
-rw-r--r-- | firmware/export/config.h | 4 | ||||
-rwxr-xr-x | firmware/export/isp1362.h | 134 |
3 files changed, 140 insertions, 1 deletions
diff --git a/firmware/export/config-h300.h b/firmware/export/config-h300.h index 7ed54958ca..30cca21253 100644 --- a/firmware/export/config-h300.h +++ b/firmware/export/config-h300.h | |||
@@ -110,6 +110,9 @@ | |||
110 | 110 | ||
111 | #define USB_IRIVERSTYLE | 111 | #define USB_IRIVERSTYLE |
112 | 112 | ||
113 | /* USB On-the-go */ | ||
114 | #define CONFIG_USBOTG USBOTG_ISP1362 | ||
115 | |||
113 | /* Define this if you have adjustable CPU frequency */ | 116 | /* Define this if you have adjustable CPU frequency */ |
114 | #define HAVE_ADJUSTABLE_CPU_FREQ | 117 | #define HAVE_ADJUSTABLE_CPU_FREQ |
115 | 118 | ||
diff --git a/firmware/export/config.h b/firmware/export/config.h index 910aeca4eb..a1327558ed 100644 --- a/firmware/export/config.h +++ b/firmware/export/config.h | |||
@@ -122,6 +122,7 @@ | |||
122 | /* CONFIG_LED */ | 122 | /* CONFIG_LED */ |
123 | #define LED_REAL 1 /* SW controlled LED (Archos recorders, player, Gmini) */ | 123 | #define LED_REAL 1 /* SW controlled LED (Archos recorders, player, Gmini) */ |
124 | #define LED_VIRTUAL 2 /* Virtual LED (icon) (Archos Ondio) */ | 124 | #define LED_VIRTUAL 2 /* Virtual LED (icon) (Archos Ondio) */ |
125 | /* else HW controlled LED (iRiver H1x0) */ | ||
125 | 126 | ||
126 | /* CONFIG_FLASH */ | 127 | /* CONFIG_FLASH */ |
127 | #define FLASH_IFP7XX 1 | 128 | #define FLASH_IFP7XX 1 |
@@ -132,7 +133,8 @@ | |||
132 | #define RTC_PCF50606 3 /* iriver H300 */ | 133 | #define RTC_PCF50606 3 /* iriver H300 */ |
133 | #define RTC_S3C2440 4 | 134 | #define RTC_S3C2440 4 |
134 | 135 | ||
135 | /* else HW controlled LED (iRiver H1x0) */ | 136 | /* USB On-the-go */ |
137 | #define USBOTG_ISP1362 1362 | ||
136 | 138 | ||
137 | /* now go and pick yours */ | 139 | /* now go and pick yours */ |
138 | #if defined(ARCHOS_PLAYER) | 140 | #if defined(ARCHOS_PLAYER) |
diff --git a/firmware/export/isp1362.h b/firmware/export/isp1362.h new file mode 100755 index 0000000000..cba693e4f0 --- /dev/null +++ b/firmware/export/isp1362.h | |||
@@ -0,0 +1,134 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2006 Jens Arnold | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | |||
20 | unsigned isp1362_read_hc_reg16(unsigned reg); | ||
21 | unsigned isp1362_read_hc_reg32(unsigned reg); | ||
22 | void isp1362_write_hc_reg16(unsigned reg, unsigned data); | ||
23 | void isp1362_write_hc_reg32(unsigned reg, unsigned data); | ||
24 | |||
25 | #define ISP1362_OTG_CONTROL 0x62 | ||
26 | #define ISP1362_OTG_STATUS 0x67 /* read only */ | ||
27 | #define ISP1362_OTG_INTERRUPT 0x68 | ||
28 | #define ISP1362_OTG_INT_ENABLE 0x69 | ||
29 | #define ISP1362_OTG_TIMER 0x6a | ||
30 | #define ISP1362_OTG_ALT_TIMER 0x6c | ||
31 | |||
32 | #define ISP1362_HC_REVISION 0x00 /* read only */ | ||
33 | #define ISP1362_HC_CONTROL 0x01 | ||
34 | #define ISP1362_HC_COMMAND_STATUS 0x02 | ||
35 | #define ISP1362_HC_INT_STATUS 0x03 | ||
36 | #define ISP1362_HC_INT_ENABLE 0x04 | ||
37 | #define ISP1362_HC_INT_DISABLE 0x05 | ||
38 | #define ISP1362_HC_FM_INTERVAL 0x0d | ||
39 | #define ISP1362_HC_FM_REMAINING 0x0e | ||
40 | #define ISP1362_HC_FM_NUMBER 0x0f | ||
41 | #define ISP1362_HC_LS_THRESHOLD 0x11 | ||
42 | #define ISP1362_HC_RH_DESCRIPTOR_A 0x12 | ||
43 | #define ISP1362_HC_RH_DESCRIPTOR_B 0x13 | ||
44 | #define ISP1362_HC_RH_STATUS 0x14 | ||
45 | #define ISP1362_HC_RH_PORT_STATUS1 0x15 | ||
46 | #define ISP1362_HC_RH_PORT_STATUS2 0x16 | ||
47 | #define ISP1362_HC_HARDWARE_CONFIG 0x20 | ||
48 | #define ISP1362_HC_DMA_CONFIG 0x21 | ||
49 | #define ISP1362_HC_TRANSFER_COUNTER 0x22 | ||
50 | #define ISP1362_HC_UP_INTERRUPT 0x24 | ||
51 | #define ISP1362_HC_UP_INT_ENABLE 0x25 | ||
52 | #define ISP1362_HC_CHIP_ID 0x27 /* read only */ | ||
53 | #define ISP1362_HC_SCRATCH 0x28 | ||
54 | #define ISP1362_HC_SOFTWARE_RESET 0x29 /* write only */ | ||
55 | #define ISP1362_HC_BUFFER_STATUS 0x2c | ||
56 | #define ISP1362_HC_DIRECT_ADDR_LEN 0x32 | ||
57 | #define ISP1362_HC_DIRECT_ADDR_DATA 0x45 | ||
58 | #define ISP1362_HC_ISTL_BUF_SIZE 0x30 | ||
59 | #define ISP1362_HC_ISTL0_BUF_PORT 0x40 | ||
60 | #define ISP1362_HC_ISTL1_BUF_PORT 0x42 | ||
61 | #define ISP1362_HC_ISTL_TOGGLE_RATE 0x47 | ||
62 | #define ISP1362_HC_INTL_BUF_SIZE 0x33 | ||
63 | #define ISP1362_HC_INTL_BUF_PORT 0x43 | ||
64 | #define ISP1362_HC_INTL_BLK_SIZE 0x53 | ||
65 | #define ISP1362_HC_INTL_PRD_DONE_MAP 0x17 /* read only */ | ||
66 | #define ISP1362_HC_INTL_PTD_SKIP_MAP 0x18 | ||
67 | #define ISP1362_HC_INTL_LAST_PTD 0x19 | ||
68 | #define ISP1362_HC_INTL_CUR_ACT_PTD 0x1a /* read only */ | ||
69 | #define ISP1362_HC_ATL_BUF_SIZE 0x34 | ||
70 | #define ISP1362_HC_ATL_BUF_PORT 0x44 | ||
71 | #define ISP1362_HC_ATL_BLK_SIZE 0x54 | ||
72 | #define ISP1362_HC_ATL_PTD_DONE_MAP 0x1b /* read only */ | ||
73 | #define ISP1362_HC_ATL_PTD_SKIP_MAP 0x1c | ||
74 | #define ISP1362_HC_ATL_LAST_PTD 0x1d | ||
75 | #define ISP1362_HC_ATL_CUR_ACT_PTD 0x1e /* read only */ | ||
76 | #define ISP1362_HC_ATL_PTD_DONE_THR_CNT 0x51 | ||
77 | #define ISP1362_HC_ATL_PTD_DONE_THR_TMO 0x52 | ||
78 | |||
79 | unsigned isp1362_read_dc_reg16(unsigned reg); | ||
80 | unsigned isp1362_read_dc_reg32(unsigned reg); | ||
81 | void isp1362_write_dc_reg16(unsigned reg, unsigned data); | ||
82 | void isp1362_write_dc_reg32(unsigned reg, unsigned data); | ||
83 | |||
84 | #define ISP1362_DC_CTRL_OUT_CFG_W 0x20 | ||
85 | #define ISP1362_DC_CTRL_IN_CFG_W 0x21 | ||
86 | #define ISP1362_DC_ENDPOINT_CFG_BASE_W 0x22 | ||
87 | #define ISP1362_DC_CTRL_OUT_CFG_R 0x30 | ||
88 | #define ISP1362_DC_CTRL_IN_CFG_R 0x31 | ||
89 | #define ISP1362_DC_ENDPOINT_CFG_BASE_R 0x32 | ||
90 | #define ISP1362_DC_ADDRESS_W 0xb6 | ||
91 | #define ISP1362_DC_ADDRESS_R 0xb7 | ||
92 | #define ISP1362_DC_MODE_W 0xb8 | ||
93 | #define ISP1362_DC_MODE_R 0xb9 | ||
94 | #define ISP1362_DC_HARDWARE_CONFIG_W 0xba | ||
95 | #define ISP1362_DC_HARDWARE_CONFIG_R 0xbb | ||
96 | #define ISP1362_DC_INT_ENABLE_W 0xc2 | ||
97 | #define ISP1362_DC_INT_ENABLE_R 0xc3 | ||
98 | #define ISP1362_DC_DMA_CONFIG_W 0xf0 | ||
99 | #define ISP1362_DC_DMA_CONFIG_R 0xf1 | ||
100 | #define ISP1362_DC_DMA_COUNTER_W 0xf2 | ||
101 | #define ISP1362_DC_DMA_COUNTER_R 0xf3 | ||
102 | #define ISP1362_DC_RESET 0xf6 | ||
103 | #define ISP1362_DC_CTRL_IN_BUF_W 0x01 | ||
104 | #define ISP1362_DC_ENDPOINT_BUF_BASE_W 0x02 | ||
105 | #define ISP1362_DC_CTRL_OUT_BUF_R 0x10 | ||
106 | #define ISP1362_DC_ENDPOINT_BUF_BASE_R 0x12 | ||
107 | #define ISP1362_DC_CTRL_OUT_STALL 0x40 | ||
108 | #define ISP1362_DC_CTRL_IN_STALL 0x41 | ||
109 | #define ISP1362_DC_ENDPOINT_STALL_BASE 0x42 | ||
110 | #define ISP1362_DC_CTRL_OUT_STATUS_R 0x50 | ||
111 | #define ISP1362_DC_CTRL_IN_STATUS_R 0x51 | ||
112 | #define ISP1362_DC_ENDPOINT_STATUS_BASE_R 0x52 | ||
113 | #define ISP1362_DC_CTRL_IN_VALIDATE 0x61 | ||
114 | #define ISP1362_DC_ENDPOINT_VALIDATE_BASE 0x62 | ||
115 | #define ISP1362_DC_CTRL_OUT_CLEAR 0x70 | ||
116 | #define ISP1362_DC_ENDPOINT_CLEAR_BASE 0x72 | ||
117 | #define ISP1362_DC_CTRL_OUT_UNSTALL 0x80 | ||
118 | #define ISP1362_DC_CTRL_IN_UNSTALL 0x81 | ||
119 | #define ISP1362_DC_ENDPOINT_UNSTALL_BASE 0x82 | ||
120 | #define ISP1362_DC_CTRL_OUT_STAT_IMG_R 0xd0 | ||
121 | #define ISP1362_DC_CTRL_IN_STAT_IMG_R 0xd1 | ||
122 | #define ISP1362_DC_ENDPOINT_STAT_IMG_BASE_R 0xd2 | ||
123 | #define ISP1362_DC_SETUP_ACK 0xf4 | ||
124 | #define ISP1362_DC_CTRL_OUT_ERROR_R 0xa0 | ||
125 | #define ISP1362_DC_CTRL_IN_ERROR_R 0xa1 | ||
126 | #define ISP1362_DC_ENDPOINT_ERROR_BASE_R 0xa2 | ||
127 | #define ISP1362_DC_UNLOCK_DEVICE 0xb0 | ||
128 | #define ISP1362_DC_SCRATCH_W 0xb2 | ||
129 | #define ISP1362_DC_SCRATCH_R 0xb3 | ||
130 | #define ISP1362_DC_FRAME_NUMBER_R 0xb4 | ||
131 | #define ISP1362_DC_CHIP_ID_R 0xb5 | ||
132 | #define ISP1362_DC_INTERRUPT_R 0xc0 | ||
133 | |||
134 | void isp1362_init(void); | ||