diff options
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/imx31l.h | 305 |
1 files changed, 46 insertions, 259 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index 6ad50f0a16..3f94156650 100644 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
@@ -135,269 +135,56 @@ | |||
135 | #define IIM_SREV_2_0_1L 0x29 /* i.MX31L 2.0/2.0.1, M91E */ | 135 | #define IIM_SREV_2_0_1L 0x29 /* i.MX31L 2.0/2.0.1, M91E */ |
136 | 136 | ||
137 | /* IOMUXC */ | 137 | /* IOMUXC */ |
138 | #define IOMUXC_(o) (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+(o))) | 138 | #define IOMUXC_GPR (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+0x008)) |
139 | 139 | ||
140 | /* GPR */ | 140 | /* SW_MUX_CTL_* */ |
141 | #define IOMUXC_GPR IOMUXC_(0x008) | 141 | #define IOMUXC_MUX_OUT (0x7 << 4) |
142 | 142 | #define IOMUXC_MUX_OUT_POS (4) | |
143 | /* SW_MUX_CTL */ | 143 | #define IOMUXC_MUX_IN (0xf << 0) |
144 | #define SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD IOMUXC_(0x00C) | 144 | #define IOMUXC_MUX_IN_POS (0) |
145 | #define SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI IOMUXC_(0x010) | 145 | #define IOMUXC_MUX_MASK (0x7f) |
146 | #define SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK IOMUXC_(0x014) | 146 | |
147 | #define SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0 IOMUXC_(0x018) | 147 | #define IOMUXC_MUX_OUT_GPIO (0x0 << IOMUXC_MUX_OUT_POS) |
148 | #define SW_MUX_CTL_D3_SPL_SD1_CMD_SD1_CLK_SD1_DATA0 IOMUXC_(0x01C) | 148 | #define IOMUXC_MUX_OUT_FUNCTIONAL (0x1 << IOMUXC_MUX_OUT_POS) |
149 | #define SW_MUX_CTL_VSYNC3_CONTRAST_D3_REV_D3_CLS IOMUXC_(0x020) | 149 | #define IOMUXC_MUX_OUT_ALT1 (0x2 << IOMUXC_MUX_OUT_POS) |
150 | #define SW_MUX_CTL_SER_RS_PAR_RS_WRITE_READ IOMUXC_(0x024) | 150 | #define IOMUXC_MUX_OUT_ALT2 (0x3 << IOMUXC_MUX_OUT_POS) |
151 | #define SW_MUX_CTL_SD_D_IO_SD_D_CLK_LCS0_LCS1 IOMUXC_(0x028) | 151 | #define IOMUXC_MUX_OUT_ALT3 (0x4 << IOMUXC_MUX_OUT_POS) |
152 | #define SW_MUX_CTL_HSYNC_FPSHIFT_DRDY0_SD_D_I IOMUXC_(0x02C) | 152 | #define IOMUXC_MUX_OUT_ALT4 (0x5 << IOMUXC_MUX_OUT_POS) |
153 | #define SW_MUX_CTL_LD15_LD16_LD17_VSYNC0 IOMUXC_(0x030) | 153 | #define IOMUXC_MUX_OUT_ALT5 (0x6 << IOMUXC_MUX_OUT_POS) |
154 | #define SW_MUX_CTL_LD11_LD12_LD13_LD14 IOMUXC_(0x034) | 154 | #define IOMUXC_MUX_OUT_ALT6 (0x7 << IOMUXC_MUX_OUT_POS) |
155 | #define SW_MUX_CTL_LD7_LD8_LD9_LD10 IOMUXC_(0x038) | 155 | |
156 | #define SW_MUX_CTL_LD3_LD4_LD5_LD6 IOMUXC_(0x03C) | 156 | #define IOMUXC_MUX_IN_NONE (0x0 << IOMUXC_MUX_IN_POS) |
157 | #define SW_MUX_CTL_USBH2_DATA1_LD0_LD1_LD2 IOMUXC_(0x040) | 157 | #define IOMUXC_MUX_IN_GPIO (0x1 << IOMUXC_MUX_IN_POS) |
158 | #define SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0 IOMUXC_(0x044) | 158 | #define IOMUXC_MUX_IN_FUNCTIONAL (0x2 << IOMUXC_MUX_IN_POS) |
159 | #define SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK IOMUXC_(0x048) | 159 | #define IOMUXC_MUX_IN_ALT1 (0x4 << IOMUXC_MUX_IN_POS) |
160 | #define SW_MUX_CTL_USBOTG_DATA1_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 IOMUXC_(0x04C) | 160 | #define IOMUXC_MUX_IN_ALT2 (0x8 << IOMUXC_MUX_IN_POS) |
161 | #define SW_MUX_CTL_USBOTG_DIR_USBOTG_STP_USBOTG_NXT_USBOTG_DATA0 IOMUXC_(0x050) | 161 | |
162 | #define SW_MUX_CTL_USB_PWR_USB_OC_USB_BYP_USBOTG_CLK IOMUXC_(0x054) | 162 | /* SW_PAD_CTL_* */ |
163 | #define SW_MUX_CTL_TDO_TRSTB_DE_B_SJC_MOD IOMUXC_(0x058) | 163 | #define IOMUXC_PAD_LOOPBACK (0x1 << 9) /* Route output to input */ |
164 | #define SW_MUX_CTL_RTCK_TCK_TMS_TDI IOMUXC_(0x05C) | ||
165 | #define SW_MUX_CTL_KEY_COL4_KEY_COL5_KEY_COL6_KEY_COL7 IOMUXC_(0x060) | ||
166 | #define SW_MUX_CTL_KEY_COL0_KEY_COL1_KEY_COL2_KEY_COL3 IOMUXC_(0x064) | ||
167 | #define SW_MUX_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6_KEY_ROW7 IOMUXC_(0x068) | ||
168 | #define SW_MUX_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2_KEY_ROW3 IOMUXC_(0x06C) | ||
169 | #define SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE IOMUXC_(0x070) | ||
170 | #define SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2 IOMUXC_(0x074) | ||
171 | #define SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1 IOMUXC_(0x078) | ||
172 | #define SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1 IOMUXC_(0x07C) | ||
173 | #define SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1 IOMUXC_(0x080) | ||
174 | #define SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2 IOMUXC_(0x084) | ||
175 | #define SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI IOMUXC_(0x088) | ||
176 | #define SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1 IOMUXC_(0x08C) | ||
177 | #define SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6 IOMUXC_(0x090) | ||
178 | #define SW_MUX_CTL_STXD5_SRXD5_SCK5_SFS5 IOMUXC_(0x094) | ||
179 | #define SW_MUX_CTL_STXD4_SRXD4_SCK4_SFS4 IOMUXC_(0x098) | ||
180 | #define SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3 IOMUXC_(0x09C) | ||
181 | #define SW_MUX_CTL_CSI_HSYNC_CSI_PIXCLK_I2C_CLK_I2C_DAT IOMUXC_(0x0A0) | ||
182 | #define SW_MUX_CTL_CSI_D14_CSI_D15_CSI_MCLK_CSI_VSYNC IOMUXC_(0x0A4) | ||
183 | #define SW_MUX_CTL_CSI_D10_CSI_D11_CSI_D12_CSI_D13 IOMUXC_(0x0A8) | ||
184 | #define SW_MUX_CTL_CSI_D6_CSI_D7_CSI_D8_CSI_D9 IOMUXC_(0x0AC) | ||
185 | #define SW_MUX_CTL_M_REQUEST_M_GRANT_CSI_D4_CSI_D5 IOMUXC_(0x0B0) | ||
186 | #define SW_MUX_CTL_PC_RST_IOIS16_PC_RW_B_PC_POE IOMUXC_(0x0B4) | ||
187 | #define SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2 IOMUXC_(0x0B8) | ||
188 | #define SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON IOMUXC_(0x0BC) | ||
189 | #define SW_MUX_CTL_D2_D1_D0_PC_CD1_B IOMUXC_(0x0C0) | ||
190 | #define SW_MUX_CTL_D6_D5_D4_D3 IOMUXC_(0x0C4) | ||
191 | #define SW_MUX_CTL_D10_D9_D8_D7 IOMUXC_(0x0C8) | ||
192 | #define SW_MUX_CTL_D14_D13_D12_D11 IOMUXC_(0x0CC) | ||
193 | #define SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15 IOMUXC_(0x0D0) | ||
194 | #define SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE IOMUXC_(0x0D4) | ||
195 | #define SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3 IOMUXC_(0x0D8) | ||
196 | #define SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B IOMUXC_(0x0DC) | ||
197 | #define SW_MUX_CTL_RW_RAS_CAS_SDWE IOMUXC_(0x0E0) | ||
198 | #define SW_MUX_CTL_CS5_ECB_LBA_BCLK IOMUXC_(0x0E4) | ||
199 | #define SW_MUX_CTL_CS1_CS2_CS3_CS4 IOMUXC_(0x0E8) | ||
200 | #define SW_MUX_CTL_EB0_EB1_OE_CS0 IOMUXC_(0x0EC) | ||
201 | #define SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3 IOMUXC_(0x0F0) | ||
202 | #define SW_MUX_CTL_SD28_SD29_SD30_SD31 IOMUXC_(0x0F4) | ||
203 | #define SW_MUX_CTL_SD24_SD25_SD26_SD27 IOMUXC_(0x0F8) | ||
204 | #define SW_MUX_CTL_SD20_SD21_SD22_SD23 IOMUXC_(0x0FC) | ||
205 | #define SW_MUX_CTL_SD16_SD17_SD18_SD19 IOMUXC_(0x100) | ||
206 | #define SW_MUX_CTL_SD12_SD13_SD14_SD15 IOMUXC_(0x104) | ||
207 | #define SW_MUX_CTL_SD8_SD9_SD10_SD11 IOMUXC_(0x108) | ||
208 | #define SW_MUX_CTL_SD4_SD5_SD6_SD7 IOMUXC_(0x10C) | ||
209 | #define SW_MUX_CTL_SD0_SD1_SD2_SD3 IOMUXC_(0x110) | ||
210 | #define SW_MUX_CTL_A24_A25_SDBA1_SDBA0 IOMUXC_(0x114) | ||
211 | #define SW_MUX_CTL_A20_A21_A22_A23 IOMUXC_(0x118) | ||
212 | #define SW_MUX_CTL_A16_A17_A18_A19 IOMUXC_(0x11C) | ||
213 | #define SW_MUX_CTL_A12_A13_A14_A15 IOMUXC_(0x120) | ||
214 | #define SW_MUX_CTL_A9_A10_MA10_A11 IOMUXC_(0x124) | ||
215 | #define SW_MUX_CTL_A5_A6_A7_A8 IOMUXC_(0x128) | ||
216 | #define SW_MUX_CTL_A1_A2_A3_A4 IOMUXC_(0x12C) | ||
217 | #define SW_MUX_CTL_DVFS1_VPG0_VPG1_A0 IOMUXC_(0x130) | ||
218 | #define SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0 IOMUXC_(0x134) | ||
219 | #define SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4 IOMUXC_(0x138) | ||
220 | #define SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0 IOMUXC_(0x13C) | ||
221 | #define SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH IOMUXC_(0x140) | ||
222 | #define SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0 IOMUXC_(0x144) | ||
223 | #define SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0 IOMUXC_(0x148) | ||
224 | #define SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3 IOMUXC_(0x14C) | ||
225 | #define SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO IOMUXC_(0x150) | ||
226 | |||
227 | #define SW_MUX_OUT (0x7 << 4) | ||
228 | #define SW_MUX_OUT_GPIO_DR (0x0 << 4) | ||
229 | #define SW_MUX_OUT_FUNCTIONAL (0x1 << 4) | ||
230 | #define SW_MUX_OUT_ALT1 (0x2 << 4) | ||
231 | #define SW_MUX_OUT_ALT2 (0x3 << 4) | ||
232 | #define SW_MUX_OUT_ALT3 (0x4 << 4) | ||
233 | #define SW_MUX_OUT_ALT4 (0x5 << 4) | ||
234 | #define SW_MUX_OUT_ALT5 (0x6 << 4) | ||
235 | #define SW_MUX_OUT_ALT6 (0x7 << 4) | ||
236 | |||
237 | #define SW_MUX_IN (0xf << 0) | ||
238 | #define SW_MUX_IN_NO_INPUTS (0x0 << 0) | ||
239 | #define SW_MUX_IN_GPIO_PSR_ISR (0x1 << 0) | ||
240 | #define SW_MUX_IN_FUNCTIONAL (0x2 << 0) | ||
241 | #define SW_MUX_IN_ALT1 (0x4 << 0) | ||
242 | #define SW_MUX_IN_ALT2 (0x8 << 0) | ||
243 | |||
244 | /* Masks for each signal field */ | ||
245 | #define SW_MUX_CTL_SIG1 (0x7f << 0) | ||
246 | #define SW_MUX_CTL_SIG2 (0x7f << 8) | ||
247 | #define SW_MUX_CTL_SIG3 (0x7f << 16) | ||
248 | #define SW_MUX_CTL_SIG4 (0x7f << 24) | ||
249 | /* Shift above flags into one of the four fields in each register */ | ||
250 | #define SW_MUX_CTL_SIG1_POS (0) | ||
251 | #define SW_MUX_CTL_SIG2_POS (8) | ||
252 | #define SW_MUX_CTL_SIG3_POS (16) | ||
253 | #define SW_MUX_CTL_SIG4_POS (24) | ||
254 | |||
255 | /* SW_PAD_CTL */ | ||
256 | #define SW_PAD_CTL_TTM_PAD__X__X IOMUXC_(0x154) | ||
257 | #define SW_PAD_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY IOMUXC_(0x158) | ||
258 | #define SW_PAD_CTL_CE_CONTROL_CLKSS_CSPI3_MOSI IOMUXC_(0x15C) | ||
259 | #define SW_PAD_CTL_ATA_DIOW_ATA_DMACK_ATA_RESET_B IOMUXC_(0x160) | ||
260 | #define SW_PAD_CTL_ATA_CS0_ATA_CS1_ATA_DIOR IOMUXC_(0x164) | ||
261 | #define SW_PAD_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3 IOMUXC_(0x168) | ||
262 | #define SW_PAD_CTL_SD1_CMD_SD1_CLK_SD1_DATA0 IOMUXC_(0x16C) | ||
263 | #define SW_PAD_CTL_D3_REV_D3_CLS_D3_SPL IOMUXC_(0x170) | ||
264 | #define SW_PAD_CTL_READ_VSYNC3_CONTRAST IOMUXC_(0x174) | ||
265 | #define SW_PAD_CTL_SER_RS_PAR_RS_WRITE IOMUXC_(0x178) | ||
266 | #define SW_PAD_CTL_SD_D_CLK_LCS0_LCS1 IOMUXC_(0x17C) | ||
267 | #define SW_PAD_CTL_DRDY0_SD_D_I_SD_D_IO IOMUXC_(0x180) | ||
268 | #define SW_PAD_CTL_VSYNC0_HSYNC_FPSHIFT IOMUXC_(0x184) | ||
269 | #define SW_PAD_CTL_LD15_LD16_LD17 IOMUXC_(0x188) | ||
270 | #define SW_PAD_CTL_LD12_LD13_LD14 IOMUXC_(0x18C) | ||
271 | #define SW_PAD_CTL_LD9_LD10_LD11 IOMUXC_(0x190) | ||
272 | #define SW_PAD_CTL_LD6_LD7_LD8 IOMUXC_(0x194) | ||
273 | #define SW_PAD_CTL_LD3_LD4_LD5 IOMUXC_(0x198) | ||
274 | #define SW_PAD_CTL_LD0_LD1_LD2 IOMUXC_(0x19C) | ||
275 | #define SW_PAD_CTL_USBH2_NXT_USBH2_DATA0_USBH2_DATA1 IOMUXC_(0x1A0) | ||
276 | #define SW_PAD_CTL_USBH2_CLK_USBH2_DIR_USBH2_STP IOMUXC_(0x1A4) | ||
277 | #define SW_PAD_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7 IOMUXC_(0x1A8) | ||
278 | #define SW_PAD_CTL_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 IOMUXC_(0x1AC) | ||
279 | #define SW_PAD_CTL_USBOTG_NXT_USBOTG_DATA0_USBOTG_DATA1 IOMUXC_(0x1B0) | ||
280 | #define SW_PAD_CTL_USBOTG_CLK_USBOTG_DIR_USBOTG_STP IOMUXC_(0x1B4) | ||
281 | #define SW_PAD_CTL_USB_PWR_USB_OC_USB_BYP IOMUXC_(0x1B8) | ||
282 | #define SW_PAD_CTL_TRSTB_DE_B_SJC_MOD IOMUXC_(0x1BC) | ||
283 | #define SW_PAD_CTL_TMS_TDI_TDO IOMUXC_(0x1C0) | ||
284 | #define SW_PAD_CTL_KEY_COL7_RTCK_TCK IOMUXC_(0x1C4) | ||
285 | #define SW_PAD_CTL_KEY_COL4_KEY_COL5_KEY_COL6 IOMUXC_(0x1C8) | ||
286 | #define SW_PAD_CTL_KEY_COL1_KEY_COL2_KEY_COL3 IOMUXC_(0x1CC) | ||
287 | #define SW_PAD_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0 IOMUXC_(0x1D0) | ||
288 | #define SW_PAD_CTL_KEY_ROW3_KEY_ROW4_KEY_ROW5 IOMUXC_(0x1D4) | ||
289 | #define SW_PAD_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2 IOMUXC_(0x1D8) | ||
290 | #define SW_PAD_CTL_RTS2_CTS2_BATT_LINE IOMUXC_(0x1DC) | ||
291 | #define SW_PAD_CTL_DTR_DCE2_RXD2_TXD2 IOMUXC_(0x1E0) | ||
292 | #define SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1 IOMUXC_(0x1E4) | ||
293 | #define SW_PAD_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1 IOMUXC_(0x1E8) | ||
294 | #define SW_PAD_CTL_CTS1_DTR_DCE1_DSR_DCE1 IOMUXC_(0x1EC) | ||
295 | #define SW_PAD_CTL_RXD1_TXD1_RTS1 IOMUXC_(0x1F0) | ||
296 | #define SW_PAD_CTL_CSPI2_SS2_CSPI2_SCLK_CSPI2_SPI_RDY IOMUXC_(0x1F4) | ||
297 | #define SW_PAD_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1 IOMUXC_(0x1F8) | ||
298 | #define SW_PAD_CTL_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI IOMUXC_(0x1FC) | ||
299 | #define SW_PAD_CTL_CSPI1_SS0_CSPI1_SS1_CSPI1_SS IOMUXC_(0x200) | ||
300 | #define SW_PAD_CTL_SFS6_CSPI1_MOSI_CSPI1_MISO IOMUXC_(0x204) | ||
301 | #define SW_PAD_CTL_STXD6_SRXD6_SCK6 IOMUXC_(0x208) | ||
302 | #define SW_PAD_CTL_SRXD5_SCK5_SFS5 IOMUXC_(0x20C) | ||
303 | #define SW_PAD_CTL_SCK4_SFS4_STXD5 IOMUXC_(0x210) | ||
304 | #define SW_PAD_CTL_SFS3_STXD4_SRXD4 IOMUXC_(0x214) | ||
305 | #define SW_PAD_CTL_STXD3_SRXD3_SCK3 IOMUXC_(0x218) | ||
306 | #define SW_PAD_CTL_CSI_PIXCLK_I2C_CLK_I2C_DAT IOMUXC_(0x21C) | ||
307 | #define SW_PAD_CTL_CSI_MCLK_CSI_VSYNC_CSI_HSYNC IOMUXC_(0x220) | ||
308 | #define SW_PAD_CTL_CSI_D13_CSI_D14_CSI_D15 IOMUXC_(0x224) | ||
309 | #define SW_PAD_CTL_CSI_D10_CSI_D11_CSI_D12 IOMUXC_(0x228) | ||
310 | #define SW_PAD_CTL_CSI_D7_CSI_D8_CSI_D9 IOMUXC_(0x22C) | ||
311 | #define SW_PAD_CTL_CSI_D4_CSI_D5_CSI_D6 IOMUXC_(0x230) | ||
312 | #define SW_PAD_CTL_PC_POE_M_REQUEST_M_GRANT IOMUXC_(0x234) | ||
313 | #define SW_PAD_CTL_PC_RST_IOIS16_PC_RW_B IOMUXC_(0x238) | ||
314 | #define SW_PAD_CTL_PC_VS2_PC_BVD1_PC_BVD2 IOMUXC_(0x23C) | ||
315 | #define SW_PAD_CTL_PC_READY_PC_PWRON_PC_VS1 IOMUXC_(0x240) | ||
316 | #define SW_PAD_CTL_PC_CD1_B_PC_CD2_B_PC_WAIT_B IOMUXC_(0x244) | ||
317 | #define SW_PAD_CTL_D2_D1_D0 IOMUXC_(0x248) | ||
318 | #define SW_PAD_CTL_D5_D4_D3 IOMUXC_(0x24C) | ||
319 | #define SW_PAD_CTL_D8_D7_D6 IOMUXC_(0x250) | ||
320 | #define SW_PAD_CTL_D11_D10_D9 IOMUXC_(0x254) | ||
321 | #define SW_PAD_CTL_D14_D13_D12 IOMUXC_(0x258) | ||
322 | #define SW_PAD_CTL_NFCE_B_NFRB_D15 IOMUXC_(0x25C) | ||
323 | #define SW_PAD_CTL_NFALE_NFCLE_NFWP_B IOMUXC_(0x260) | ||
324 | #define SW_PAD_CTL_SDQS3_NFWE_B_NFRE_B IOMUXC_(0x264) | ||
325 | #define SW_PAD_CTL_SDQS0_SDQS1_SDQS2 IOMUXC_(0x268) | ||
326 | #define SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B IOMUXC_(0x26C) | ||
327 | #define SW_PAD_CTL_CAS_SDWE_SDCKE0 IOMUXC_(0x270) | ||
328 | #define SW_PAD_CTL_BCLK_RW_RAS IOMUXC_(0x274) | ||
329 | #define SW_PAD_CTL_CS5_ECB_LBA IOMUXC_(0x278) | ||
330 | #define SW_PAD_CTL_CS2_CS3_CS4 IOMUXC_(0x27C) | ||
331 | #define SW_PAD_CTL_OE_CS0_CS1 IOMUXC_(0x280) | ||
332 | #define SW_PAD_CTL_DQM3_EB0_EB1 IOMUXC_(0x284) | ||
333 | #define SW_PAD_CTL_DQM0_DQM1_DQM2 IOMUXC_(0x288) | ||
334 | #define SW_PAD_CTL_SD29_SD30_SD31 IOMUXC_(0x28C) | ||
335 | #define SW_PAD_CTL_SD26_SD27_SD28 IOMUXC_(0x290) | ||
336 | #define SW_PAD_CTL_SD23_SD24_SD25 IOMUXC_(0x294) | ||
337 | #define SW_PAD_CTL_SD20_SD21_SD22 IOMUXC_(0x298) | ||
338 | #define SW_PAD_CTL_SD17_SD18_SD19 IOMUXC_(0x29C) | ||
339 | #define SW_PAD_CTL_SD14_SD15_SD16 IOMUXC_(0x2A0) | ||
340 | #define SW_PAD_CTL_SD11_SD12_SD13 IOMUXC_(0x2A4) | ||
341 | #define SW_PAD_CTL_SD8_SD9_SD10 IOMUXC_(0x2A8) | ||
342 | #define SW_PAD_CTL_SD5_SD6_SD7 IOMUXC_(0x2AC) | ||
343 | #define SW_PAD_CTL_SD2_SD3_SD4 IOMUXC_(0x2B0) | ||
344 | #define SW_PAD_CTL_SDBA0_SD0_SD1 IOMUXC_(0x2B4) | ||
345 | #define SW_PAD_CTL_A24_A25_SDBA1 IOMUXC_(0x2B8) | ||
346 | #define SW_PAD_CTL_A21_A22_A23 IOMUXC_(0x2BC) | ||
347 | #define SW_PAD_CTL_A18_A19_A20 IOMUXC_(0x2C0) | ||
348 | #define SW_PAD_CTL_A15_A16_A17 IOMUXC_(0x2C4) | ||
349 | #define SW_PAD_CTL_A12_A13_A14 IOMUXC_(0x2C8) | ||
350 | #define SW_PAD_CTL_A10_MA10_A11 IOMUXC_(0x2CC) | ||
351 | #define SW_PAD_CTL_A7_A8_A9 IOMUXC_(0x2D0) | ||
352 | #define SW_PAD_CTL_A4_A5_A6 IOMUXC_(0x2D4) | ||
353 | #define SW_PAD_CTL_A1_A2_A3 IOMUXC_(0x2D8) | ||
354 | #define SW_PAD_CTL_VPG0_VPG1_A0 IOMUXC_(0x2DC) | ||
355 | #define SW_PAD_CTL_VSTBY_DVFS0_DVFS1 IOMUXC_(0x2E0) | ||
356 | #define SW_PAD_CTL_BOOT_MODE4_CKIL_POWER_FAIL IOMUXC_(0x2E4) | ||
357 | #define SW_PAD_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3 IOMUXC_(0x2E8) | ||
358 | #define SW_PAD_CTL_POR_B_CLKO_BOOT_MODE0 IOMUXC_(0x2EC) | ||
359 | #define SW_PAD_CTL_SIMPD0_CKIH_RESET_IN_B IOMUXC_(0x2F0) | ||
360 | #define SW_PAD_CTL_SVEN0_STX0_SRX0 IOMUXC_(0x2F4) | ||
361 | #define SW_PAD_CTL_GPIO3_1_SCLK0_SRST0 IOMUXC_(0x2F8) | ||
362 | #define SW_PAD_CTL_GPIO1_5_GPIO1_6_GPIO3_0 IOMUXC_(0x2FC) | ||
363 | #define SW_PAD_CTL_GPIO1_2_GPIO1_3_GPIO1_4 IOMUXC_(0x300) | ||
364 | #define SW_PAD_CTL_PWMO_GPIO1_0_GPIO1_1 IOMUXC_(0x304) | ||
365 | #define SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST IOMUXC_(0x308) | ||
366 | |||
367 | /* SW_PAD_CTL flags */ | ||
368 | #define SW_PAD_CTL_LOOPBACK (0x1 << 9) /* Route output to input */ | ||
369 | /* Pullup, pulldown and keeper enable */ | 164 | /* Pullup, pulldown and keeper enable */ |
370 | #define SW_PAD_CTL_PUE_PKE (0x3 << 7) | 165 | #define IOMUXC_PAD_PUE_PKE (0x3 << 7) |
371 | #define SW_PAD_CTL_PUE_PKE_DISABLE (0x0 << 7) | 166 | #define IOMUXC_PAD_PUE_PKE_DISABLE (0x0 << 7) |
372 | #define SW_PAD_CTL_PUE_PKE_DISABLE_2 (0x1 << 7) /* Same as 0x0 */ | 167 | #define IOMUXC_PAD_PUE_PKE_DISABLE_2 (0x1 << 7) /* Same as 0x0 */ |
373 | #define SW_PAD_CTL_PUE_PKE_KEEPER (0x2 << 7) | 168 | #define IOMUXC_PAD_PUE_PKE_KEEPER (0x2 << 7) |
374 | #define SW_PAD_CTL_PUE_PKE_PULLUPDOWN (0x3 << 7) /* Enb. Pull up or down */ | 169 | #define IOMUXC_PAD_PUE_PKE_PULLUPDOWN (0x3 << 7) /* Enb. Pull up or down */ |
375 | /* Pullup/down resistance */ | 170 | /* Pullup/down resistance */ |
376 | #define SW_PAD_CTL_PUS (0x3 << 5) | 171 | #define IOMUXC_PAD_PUS (0x3 << 5) |
377 | #define SW_PAD_CTL_PUS_DOWN_100K (0x0 << 5) | 172 | #define IOMUXC_PAD_PUS_DOWN_100K (0x0 << 5) |
378 | #define SW_PAD_CTL_PUS_UP_100K (0x1 << 5) | 173 | #define IOMUXC_PAD_PUS_UP_100K (0x1 << 5) |
379 | #if 0 /* Completeness */ | 174 | #if 0 /* Completeness */ |
380 | #define SW_PAD_CTL_PUS_UP_47K (0x2 << 5) /* Not in IMX31/L */ | 175 | #define IOMUXC_PAD_PUS_UP_47K (0x2 << 5) /* Not in IMX31/L */ |
381 | #define SW_PAD_CTL_PUS_UP_22K (0x3 << 5) /* Not in IMX31/L */ | 176 | #define IOMUXC_PAD_PUS_UP_22K (0x3 << 5) /* Not in IMX31/L */ |
382 | #endif | 177 | #endif |
383 | #define SW_PAD_CTL_HYS (0x1 << 4) /* Schmitt trigger input */ | 178 | #define IOMUXC_PAD_HYS (0x1 << 4) /* Schmitt trigger input */ |
384 | #define SW_PAD_CTL_ODE (0x1 << 3) /* Open drain output 0=CMOS pushpull*/ | 179 | #define IOMUXC_PAD_ODE (0x1 << 3) /* Open drain output 0=CMOS pushpull*/ |
385 | #define SW_PAD_CTL_DSE (0x3 << 1) | 180 | #define IOMUXC_PAD_DSE (0x3 << 1) |
386 | #define SW_PAD_CTL_DSE_STD (0x0 << 1) /* Drive strength */ | 181 | #define IOMUXC_PAD_DSE_STD (0x0 << 1) /* Drive strength */ |
387 | #define SW_PAD_CTL_DSE_HIGH (0x1 << 1) | 182 | #define IOMUXC_PAD_DSE_HIGH (0x1 << 1) |
388 | #define SW_PAD_CTL_DSE_MAX (0x2 << 1) | 183 | #define IOMUXC_PAD_DSE_MAX (0x2 << 1) |
389 | #define SW_PAD_CTL_DSE_MAX_2 (0x3 << 1) /* Same as 0x2 */ | 184 | #define IOMUXC_PAD_DSE_MAX_2 (0x3 << 1) /* Same as 0x2 */ |
390 | #define SW_PAD_CTL_SRE (0x1 << 0) /* Slew rate, 1=fast */ | 185 | #define IOMUXC_PAD_SRE (0x1 << 0) /* Slew rate, 1=fast */ |
391 | 186 | ||
392 | /* Masks for each IO field */ | 187 | #define IOMUXC_PAD_MASK (0x3ff) |
393 | #define SW_PAD_CTL_IO1 (0x3ff << 0) | ||
394 | #define SW_PAD_CTL_IO2 (0x3ff << 10) | ||
395 | #define SW_PAD_CTL_IO3 (0x3ff << 20) | ||
396 | |||
397 | /* Shift above flags into one of the three fields in each register */ | ||
398 | #define SW_PAD_CTL_IO1_POS (0) | ||
399 | #define SW_PAD_CTL_IO2_POS (10) | ||
400 | #define SW_PAD_CTL_IO3_POS (20) | ||
401 | 188 | ||
402 | /* RNGA */ | 189 | /* RNGA */ |
403 | #define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00)) | 190 | #define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00)) |