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-rw-r--r--firmware/export/s5l8702.h174
1 files changed, 2 insertions, 172 deletions
diff --git a/firmware/export/s5l8702.h b/firmware/export/s5l8702.h
index 701dcabeb4..34b6da874b 100644
--- a/firmware/export/s5l8702.h
+++ b/firmware/export/s5l8702.h
@@ -419,178 +419,6 @@
419#define SHA1DATAIN ((uint32_t volatile*)(0x38000040)) 419#define SHA1DATAIN ((uint32_t volatile*)(0x38000040))
420 420
421 421
422/////DMA/////
423#ifndef ASM
424struct dma_lli
425{
426 const void* srcaddr;
427 void* dstaddr;
428 const struct dma_lli* nextlli;
429 uint32_t control;
430};
431#endif
432/* currently these definitions are not used, temporarily
433 removed to avoid conflicts with pl080.h */
434#if 0
435#define DMACINTSTS(d) (*((uint32_t volatile*)(0x38200000 + 0x1700000 * (d))))
436#define DMACINTTCSTS(d) (*((uint32_t volatile*)(0x38200004 + 0x1700000 * (d))))
437#define DMACINTTCCLR(d) (*((uint32_t volatile*)(0x38200008 + 0x1700000 * (d))))
438#define DMACINTERRSTS(d) (*((uint32_t volatile*)(0x3820000c + 0x1700000 * (d))))
439#define DMACINTERRCLR(d) (*((uint32_t volatile*)(0x38200010 + 0x1700000 * (d))))
440#define DMACRAWINTTCSTS(d) (*((uint32_t volatile*)(0x38200014 + 0x1700000 * (d))))
441#define DMACRAWINTERRSTS(d) (*((uint32_t volatile*)(0x38200018 + 0x1700000 * (d))))
442#define DMACENABLEDCHANS(d) (*((uint32_t volatile*)(0x3820001c + 0x1700000 * (d))))
443#define DMACSOFTBREQ(d) (*((uint32_t volatile*)(0x38200020 + 0x1700000 * (d))))
444#define DMACSOFTSREQ(d) (*((uint32_t volatile*)(0x38200024 + 0x1700000 * (d))))
445#define DMACSOFTLBREQ(d) (*((uint32_t volatile*)(0x38200028 + 0x1700000 * (d))))
446#define DMACSOFTLSREQ(d) (*((uint32_t volatile*)(0x3820002c + 0x1700000 * (d))))
447#define DMACCONFIG(d) (*((uint32_t volatile*)(0x38200030 + 0x1700000 * (d))))
448#define DMACSYNC(d) (*((uint32_t volatile*)(0x38200034 + 0x1700000 * (d))))
449#endif
450#define DMACCLLI(d, c) (*((struct dma_lli volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
451#define DMACCSRCADDR(d, c) (*((const void* volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
452#define DMACCDESTADDR(d, c) (*((void* volatile*)(0x38200104 + 0x1700000 * (d) + 0x20 * (c))))
453#define DMACCNEXTLLI(d, c) (*((const void* volatile*)(0x38200108 + 0x1700000 * (d) + 0x20 * (c))))
454#define DMACCCONTROL(d, c) (*((uint32_t volatile*)(0x3820010c + 0x1700000 * (d) + 0x20 * (c))))
455#define DMACCCONFIG(d, c) (*((uint32_t volatile*)(0x38200110 + 0x1700000 * (d) + 0x20 * (c))))
456#define DMAC0INTSTS (*((uint32_t volatile*)(0x38200000)))
457#define DMAC0INTTCSTS (*((uint32_t volatile*)(0x38200004)))
458#define DMAC0INTTCCLR (*((uint32_t volatile*)(0x38200008)))
459#define DMAC0INTERRSTS (*((uint32_t volatile*)(0x3820000c)))
460#define DMAC0INTERRCLR (*((uint32_t volatile*)(0x38200010)))
461#define DMAC0RAWINTTCSTS (*((uint32_t volatile*)(0x38200014)))
462#define DMAC0RAWINTERRSTS (*((uint32_t volatile*)(0x38200018)))
463#define DMAC0ENABLEDCHANS (*((uint32_t volatile*)(0x3820001c)))
464#define DMAC0SOFTBREQ (*((uint32_t volatile*)(0x38200020)))
465#define DMAC0SOFTSREQ (*((uint32_t volatile*)(0x38200024)))
466#define DMAC0SOFTLBREQ (*((uint32_t volatile*)(0x38200028)))
467#define DMAC0SOFTLSREQ (*((uint32_t volatile*)(0x3820002c)))
468#define DMAC0CONFIG (*((uint32_t volatile*)(0x38200030)))
469#define DMAC0SYNC (*((uint32_t volatile*)(0x38200034)))
470#define DMAC0CLLI(c) (*((struct dma_lli volatile*)(0x38200100 + 0x20 * (c))))
471#define DMAC0CSRCADDR(c) (*((const void* volatile*)(0x38200100 + 0x20 * (c))))
472#define DMAC0CDESTADDR(c) (*((void* volatile*)(0x38200104 + 0x20 * (c))))
473#define DMAC0CNEXTLLI(c) (*((const void* volatile*)(0x38200108 + 0x20 * (c))))
474#define DMAC0CCONTROL(c) (*((uint32_t volatile*)(0x3820010c + 0x20 * (c))))
475#define DMAC0CCONFIG(c) (*((uint32_t volatile*)(0x38200110 + 0x20 * (c))))
476#define DMAC0C0LLI (*((struct dma_lli volatile*)(0x38200100)))
477#define DMAC0C0SRCADDR (*((const void* volatile*)(0x38200100)))
478#define DMAC0C0DESTADDR (*((void* volatile*)(0x38200104)))
479#define DMAC0C0NEXTLLI (*((const struct dma_lli* volatile*)(0x38200108)))
480#define DMAC0C0CONTROL (*((uint32_t volatile*)(0x3820010c)))
481#define DMAC0C0CONFIG (*((uint32_t volatile*)(0x38200110)))
482#define DMAC0C1LLI (*((struct dma_lli volatile*)(0x38200120)))
483#define DMAC0C1SRCADDR (*((const void* volatile*)(0x38200120)))
484#define DMAC0C1DESTADDR (*((void* volatile*)(0x38200124)))
485#define DMAC0C1NEXTLLI (*((const struct dma_lli* volatile*)(0x38200128)))
486#define DMAC0C1CONTROL (*((uint32_t volatile*)(0x3820012c)))
487#define DMAC0C1CONFIG (*((uint32_t volatile*)(0x38200130)))
488#define DMAC0C2LLI (*((struct dma_lli volatile*)(0x38200140)))
489#define DMAC0C2SRCADDR (*((const void* volatile*)(0x38200140)))
490#define DMAC0C2DESTADDR (*((void* volatile*)(0x38200144)))
491#define DMAC0C2NEXTLLI (*((const struct dma_lli* volatile*)(0x38200148)))
492#define DMAC0C2CONTROL (*((uint32_t volatile*)(0x3820014c)))
493#define DMAC0C2CONFIG (*((uint32_t volatile*)(0x38200150)))
494#define DMAC0C3LLI (*((struct dma_lli volatile*)(0x38200160)))
495#define DMAC0C3SRCADDR (*((const void* volatile*)(0x38200160)))
496#define DMAC0C3DESTADDR (*((void* volatile*)(0x38200164)))
497#define DMAC0C3NEXTLLI (*((const struct dma_lli* volatile*)(0x38200168)))
498#define DMAC0C3CONTROL (*((uint32_t volatile*)(0x3820016c)))
499#define DMAC0C3CONFIG (*((uint32_t volatile*)(0x38200170)))
500#define DMAC0C4LLI (*((struct dma_lli volatile*)(0x38200180)))
501#define DMAC0C4SRCADDR (*((const void* volatile*)(0x38200180)))
502#define DMAC0C4DESTADDR (*((void* volatile*)(0x38200184)))
503#define DMAC0C4NEXTLLI (*((const struct dma_lli* volatile*)(0x38200188)))
504#define DMAC0C4CONTROL (*((uint32_t volatile*)(0x3820018c)))
505#define DMAC0C4CONFIG (*((uint32_t volatile*)(0x38200190)))
506#define DMAC0C5LLI (*((struct dma_lli volatile*)(0x382001a0)))
507#define DMAC0C5SRCADDR (*((const void* volatile*)(0x382001a0)))
508#define DMAC0C5DESTADDR (*((void* volatile*)(0x382001a4)))
509#define DMAC0C5NEXTLLI (*((const struct dma_lli* volatile*)(0x382001a8)))
510#define DMAC0C5CONTROL (*((uint32_t volatile*)(0x382001ac)))
511#define DMAC0C5CONFIG (*((uint32_t volatile*)(0x382001b0)))
512#define DMAC0C6LLI (*((struct dma_lli volatile*)(0x382001c0)))
513#define DMAC0C6SRCADDR (*((const void* volatile*)(0x382001c0)))
514#define DMAC0C6DESTADDR (*((void* volatile*)(0x382001c4)))
515#define DMAC0C6NEXTLLI (*((const struct dma_lli* volatile*)(0x382001c8)))
516#define DMAC0C6CONTROL (*((uint32_t volatile*)(0x382001cc)))
517#define DMAC0C6CONFIG (*((uint32_t volatile*)(0x382001d0)))
518#define DMAC0C7LLI (*((struct dma_lli volatile*)(0x382001e0)))
519#define DMAC0C7SRCADDR (*((const void* volatile*)(0x382001e0)))
520#define DMAC0C7DESTADDR (*((void* volatile*)(0x382001e4)))
521#define DMAC0C7NEXTLLI (*((const struct dma_lli* volatile*)(0x382001e8)))
522#define DMAC0C7CONTROL (*((uint32_t volatile*)(0x382001ec)))
523#define DMAC0C7CONFIG (*((uint32_t volatile*)(0x382001f0)))
524#define DMAC1INTSTS (*((uint32_t volatile*)(0x39900000)))
525#define DMAC1INTTCSTS (*((uint32_t volatile*)(0x39900004)))
526#define DMAC1INTTCCLR (*((uint32_t volatile*)(0x39900008)))
527#define DMAC1INTERRSTS (*((uint32_t volatile*)(0x3990000c)))
528#define DMAC1INTERRCLR (*((uint32_t volatile*)(0x39900010)))
529#define DMAC1RAWINTTCSTS (*((uint32_t volatile*)(0x39900014)))
530#define DMAC1RAWINTERRSTS (*((uint32_t volatile*)(0x39900018)))
531#define DMAC1ENABLEDCHANS (*((uint32_t volatile*)(0x3990001c)))
532#define DMAC1SOFTBREQ (*((uint32_t volatile*)(0x39900020)))
533#define DMAC1SOFTSREQ (*((uint32_t volatile*)(0x39900024)))
534#define DMAC1SOFTLBREQ (*((uint32_t volatile*)(0x39900028)))
535#define DMAC1SOFTLSREQ (*((uint32_t volatile*)(0x3990002c)))
536#define DMAC1CONFIG (*((uint32_t volatile*)(0x39900030)))
537#define DMAC1SYNC (*((uint32_t volatile*)(0x39900034)))
538#define DMAC1CLLI(c) (*((struct dma_lli volatile*)(0x39900100 + 0x20 * (c))))
539#define DMAC1CSRCADDR(c) (*((const void* volatile*)(0x39900100 + 0x20 * (c))))
540#define DMAC1CDESTADDR(c) (*((void* volatile*)(0x39900104 + 0x20 * (c))))
541#define DMAC1CNEXTLLI(c) (*((const void* volatile*)(0x39900108 + 0x20 * (c))))
542#define DMAC1CCONTROL(c) (*((uint32_t volatile*)(0x3990010c + 0x20 * (c))))
543#define DMAC1CCONFIG(c) (*((uint32_t volatile*)(0x39900110 + 0x20 * (c))))
544#define DMAC1C0LLI (*((struct dma_lli volatile*)(0x39900100)))
545#define DMAC1C0SRCADDR (*((const void* volatile*)(0x39900100)))
546#define DMAC1C0DESTADDR (*((void* volatile*)(0x39900104)))
547#define DMAC1C0NEXTLLI (*((const struct dma_lli* volatile*)(0x39900108)))
548#define DMAC1C0CONTROL (*((uint32_t volatile*)(0x3990010c)))
549#define DMAC1C0CONFIG (*((uint32_t volatile*)(0x39900110)))
550#define DMAC1C1LLI (*((struct dma_lli volatile*)(0x39900120)))
551#define DMAC1C1SRCADDR (*((const void* volatile*)(0x39900120)))
552#define DMAC1C1DESTADDR (*((void* volatile*)(0x39900124)))
553#define DMAC1C1NEXTLLI (*((const struct dma_lli* volatile*)(0x39900128)))
554#define DMAC1C1CONTROL (*((uint32_t volatile*)(0x3990012c)))
555#define DMAC1C1CONFIG (*((uint32_t volatile*)(0x39900130)))
556#define DMAC1C2LLI (*((struct dma_lli volatile*)(0x39900140)))
557#define DMAC1C2SRCADDR (*((const void* volatile*)(0x39900140)))
558#define DMAC1C2DESTADDR (*((void* volatile*)(0x39900144)))
559#define DMAC1C2NEXTLLI (*((const struct dma_lli* volatile*)(0x39900148)))
560#define DMAC1C2CONTROL (*((uint32_t volatile*)(0x3990014c)))
561#define DMAC1C2CONFIG (*((uint32_t volatile*)(0x39900150)))
562#define DMAC1C3LLI (*((struct dma_lli volatile*)(0x39900160)))
563#define DMAC1C3SRCADDR (*((const void* volatile*)(0x39900160)))
564#define DMAC1C3DESTADDR (*((void* volatile*)(0x39900164)))
565#define DMAC1C3NEXTLLI (*((volatile void**)(0x39900168)))
566#define DMAC1C3CONTROL (*((uint32_t volatile*)(0x3990016c)))
567#define DMAC1C3CONFIG (*((uint32_t volatile*)(0x39900170)))
568#define DMAC1C4LLI (*((struct dma_lli volatile*)(0x39900180)))
569#define DMAC1C4SRCADDR (*((const void* volatile*)(0x39900180)))
570#define DMAC1C4DESTADDR (*((void* volatile*)(0x39900184)))
571#define DMAC1C4NEXTLLI (*((const struct dma_lli* volatile*)(0x39900188)))
572#define DMAC1C4CONTROL (*((uint32_t volatile*)(0x3990018c)))
573#define DMAC1C4CONFIG (*((uint32_t volatile*)(0x39900190)))
574#define DMAC1C5LLI (*((struct dma_lli volatile*)(0x399001a0)))
575#define DMAC1C5SRCADDR (*((const void* volatile*)(0x399001a0)))
576#define DMAC1C5DESTADDR (*((void* volatile*)(0x399001a4)))
577#define DMAC1C5NEXTLLI (*((const struct dma_lli* volatile*)(0x399001a8)))
578#define DMAC1C5CONTROL (*((uint32_t volatile*)(0x399001ac)))
579#define DMAC1C5CONFIG (*((uint32_t volatile*)(0x399001b0)))
580#define DMAC1C6LLI (*((struct dma_lli volatile*)(0x399001c0)))
581#define DMAC1C6SRCADDR (*((const void* volatile*)(0x399001c0)))
582#define DMAC1C6DESTADDR (*((void* volatile*)(0x399001c4)))
583#define DMAC1C6NEXTLLI (*((const struct dma_lli* volatile*)(0x399001c8)))
584#define DMAC1C6CONTROL (*((uint32_t volatile*)(0x399001cc)))
585#define DMAC1C6CONFIG (*((uint32_t volatile*)(0x399001d0)))
586#define DMAC1C7LLI (*((struct dma_lli volatile*)(0x399001e0)))
587#define DMAC1C7SRCADDR (*((const void* volatile*)(0x399001e0)))
588#define DMAC1C7DESTADDR (*((void* volatile*)(0x399001e4)))
589#define DMAC1C7NEXTLLI (*((const struct dma_lli* volatile*)(0x399001e8)))
590#define DMAC1C7CONTROL (*((uint32_t volatile*)(0x399001ec)))
591#define DMAC1C7CONFIG (*((uint32_t volatile*)(0x399001f0)))
592
593
594/////LCD///// 422/////LCD/////
595#define LCD_BASE (0x38300000) 423#define LCD_BASE (0x38300000)
596#define LCD_CONFIG (*((uint32_t volatile*)(0x38300000))) 424#define LCD_CONFIG (*((uint32_t volatile*)(0x38300000)))
@@ -844,6 +672,8 @@ struct dma_lli
844/////CLOCK GATES///// 672/////CLOCK GATES/////
845#define CLOCKGATE_USB_1 2 673#define CLOCKGATE_USB_1 2
846#define CLOCKGATE_USB_2 35 674#define CLOCKGATE_USB_2 35
675#define CLOCKGATE_DMAC0 25
676#define CLOCKGATE_DMAC1 26
847 677
848 678
849/////INTERRUPTS///// 679/////INTERRUPTS/////
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-22 16:22:44 +0000