diff options
Diffstat (limited to 'firmware/export/s5l8700.h')
-rw-r--r-- | firmware/export/s5l8700.h | 52 |
1 files changed, 40 insertions, 12 deletions
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h index e8497ff337..3444919bc3 100644 --- a/firmware/export/s5l8700.h +++ b/firmware/export/s5l8700.h | |||
@@ -133,33 +133,61 @@ | |||
133 | #define PWRCONEXT (*(REG32_PTR_T)(0x3C500040)) /* Clock power control register 2 */ | 133 | #define PWRCONEXT (*(REG32_PTR_T)(0x3C500040)) /* Clock power control register 2 */ |
134 | 134 | ||
135 | /* 06. INTERRUPT CONTROLLER UNIT */ | 135 | /* 06. INTERRUPT CONTROLLER UNIT */ |
136 | #if CONFIG_CPU==S5L8700 | ||
136 | #define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */ | 137 | #define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */ |
137 | #define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */ | 138 | #define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */ |
138 | #define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */ | 139 | #define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */ |
139 | #if CONFIG_CPU==S5L8701 | ||
140 | #define INTMSK_TIMERA (1<<5) | ||
141 | #define INTMSK_TIMERB (1<<5) | ||
142 | #define INTMSK_TIMERC (1<<5) | ||
143 | #define INTMSK_TIMERD (1<<5) | ||
144 | #define INTMSK_ECC (1<<19) | ||
145 | #define INTMSK_USB_OTG (1<<16) | ||
146 | #define INTMSK_UART0 (0) /* Unknown */ | ||
147 | #define INTMSK_UART1 (1<<12) | ||
148 | #define INTMSK_UART2 (1<<7) | ||
149 | #else | ||
150 | #define INTMSK_TIMERA (1<<5) | 140 | #define INTMSK_TIMERA (1<<5) |
151 | #define INTMSK_TIMERB (1<<7) | 141 | #define INTMSK_TIMERB (1<<7) |
152 | #define INTMSK_TIMERC (1<<8) | 142 | #define INTMSK_TIMERC (1<<8) |
153 | #define INTMSK_TIMERD (1<<9) | 143 | #define INTMSK_TIMERD (1<<9) |
154 | #define INTMSK_UART0 (1<<22) | 144 | #define INTMSK_UART0 (1<<22) |
155 | #define INTMSK_UART1 (1<<14) | 145 | #define INTMSK_UART1 (1<<14) |
156 | #endif | ||
157 | #define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */ | 146 | #define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */ |
158 | #define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */ | 147 | #define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */ |
159 | #define INTOFFSET (*(REG32_PTR_T)(0x39C00014)) /* Indicates the IRQ interrupt request source */ | 148 | #define INTOFFSET (*(REG32_PTR_T)(0x39C00014)) /* Indicates the IRQ interrupt request source */ |
160 | #define EINTPOL (*(REG32_PTR_T)(0x39C00018)) /* Indicates external interrupt polarity */ | 149 | #define EINTPOL (*(REG32_PTR_T)(0x39C00018)) /* Indicates external interrupt polarity */ |
161 | #define EINTPEND (*(REG32_PTR_T)(0x39C0001C)) /* Indicates whether external interrupts are pending. */ | 150 | #define EINTPEND (*(REG32_PTR_T)(0x39C0001C)) /* Indicates whether external interrupts are pending. */ |
162 | #define EINTMSK (*(REG32_PTR_T)(0x39C00020)) /* Indicates whether external interrupts are masked */ | 151 | #define EINTMSK (*(REG32_PTR_T)(0x39C00020)) /* Indicates whether external interrupts are masked */ |
152 | #else /* S5L8701 */ | ||
153 | #define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */ | ||
154 | #define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */ | ||
155 | #define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */ | ||
156 | #define INTMSK_EINTG0 (1<<1) | ||
157 | #define INTMSK_EINTG1 (1<<2) | ||
158 | #define INTMSK_EINTG2 (1<<3) | ||
159 | #define INTMSK_EINTG3 (1<<4) | ||
160 | #define INTMSK_TIMERA (1<<5) | ||
161 | #define INTMSK_TIMERB (1<<5) | ||
162 | #define INTMSK_TIMERC (1<<5) | ||
163 | #define INTMSK_TIMERD (1<<5) | ||
164 | #define INTMSK_ECC (1<<19) | ||
165 | #define INTMSK_USB_OTG (1<<16) | ||
166 | #define INTMSK_UART0 (0) /* (AFAIK) no IRQ to ICU, uses EINTG0 */ | ||
167 | #define INTMSK_UART1 (1<<12) | ||
168 | #define INTMSK_UART2 (1<<7) | ||
169 | #define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */ | ||
170 | #define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */ | ||
171 | #define INTOFFSET (*(REG32_PTR_T)(0x39C00014)) /* Indicates the IRQ interrupt request source */ | ||
172 | /* | ||
173 | * s5l8701 GPIO (External) Interrupt Controller. | ||
174 | * | ||
175 | * At first glance it looks very similar to gpio-s5l8702, but | ||
176 | * not fully tested, so this information could be wrong. | ||
177 | * | ||
178 | * Group0[31:10] Not used | ||
179 | * [9] UART0 IRQ | ||
180 | * [8] VBUS | ||
181 | * [7:0] PDAT1 | ||
182 | * Group1[31:0] PDAT5:PDAT4:PDAT3:PDAT2 | ||
183 | * Group2[31:0] PDAT11:PDAT10:PDAT7:PDAT6 | ||
184 | * Group3[31:0] PDAT15:PDAT14:PDAT13:PDAT12 | ||
185 | */ | ||
186 | #define GPIOIC_INTLEVEL(g) (*(REG32_PTR_T)(0x39C00018 + 4*(g))) | ||
187 | #define GPIOIC_INTSTAT(g) (*(REG32_PTR_T)(0x39C00028 + 4*(g))) | ||
188 | #define GPIOIC_INTEN(g) (*(REG32_PTR_T)(0x39C00038 + 4*(g))) | ||
189 | #define GPIOIC_INTTYPE(g) (*(REG32_PTR_T)(0x39C00048 + 4*(g))) | ||
190 | #endif | ||
163 | 191 | ||
164 | /* 07. MEMORY INTERFACE UNIT (MIU) */ | 192 | /* 07. MEMORY INTERFACE UNIT (MIU) */ |
165 | 193 | ||