diff options
Diffstat (limited to 'firmware/export/s5l8700.h')
| -rw-r--r-- | firmware/export/s5l8700.h | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h index 71ba071365..98021099d8 100644 --- a/firmware/export/s5l8700.h +++ b/firmware/export/s5l8700.h | |||
| @@ -107,10 +107,11 @@ | |||
| 107 | #define ADM_S1BASE (*(REG32_PTR_T)(0x39000064)) /* Start Address for Sequential Block 1 Area */ | 107 | #define ADM_S1BASE (*(REG32_PTR_T)(0x39000064)) /* Start Address for Sequential Block 1 Area */ |
| 108 | 108 | ||
| 109 | /* 05. CLOCK & POWER MANAGEMENT */ | 109 | /* 05. CLOCK & POWER MANAGEMENT */ |
| 110 | #define CLKCON (*(REG32_PTR_T)(0x3C500000)) /* Clock control Register */ | 110 | #define CLKCON (*(REG32_PTR_T)(0x3C500000)) /* Clock control register */ |
| 111 | #define PLL0PMS (*(REG32_PTR_T)(0x3C500004)) /* PLL PMS value Register */ | 111 | #define PLL0PMS (*(REG32_PTR_T)(0x3C500004)) /* PLL PMS value register */ |
| 112 | #define PLL1PMS (*(REG32_PTR_T)(0x3C500008)) /* PLL PMS value Register */ | 112 | #define PLL1PMS (*(REG32_PTR_T)(0x3C500008)) /* PLL PMS value register */ |
| 113 | #define PLL2PMS (*(REG32_PTR_T)(0x3C50000C)) /* PLL PMS value Register - S5L8701 only? */ | 113 | #define PLL2PMS (*(REG32_PTR_T)(0x3C50000C)) /* PLL PMS value register - S5L8701 only? */ |
| 114 | #define CLKCON3 (*(REG32_PTR_T)(0x3C500010)) /* Clock control register 3 */ | ||
| 114 | #define PLL0LCNT (*(REG32_PTR_T)(0x3C500014)) /* PLL0 lock count register */ | 115 | #define PLL0LCNT (*(REG32_PTR_T)(0x3C500014)) /* PLL0 lock count register */ |
| 115 | #define PLL1LCNT (*(REG32_PTR_T)(0x3C500018)) /* PLL1 lock count register */ | 116 | #define PLL1LCNT (*(REG32_PTR_T)(0x3C500018)) /* PLL1 lock count register */ |
| 116 | #define PLL2LCNT (*(REG32_PTR_T)(0x3C50001C)) /* PLL2 lock count register - S5L8701 only? */ | 117 | #define PLL2LCNT (*(REG32_PTR_T)(0x3C50001C)) /* PLL2 lock count register - S5L8701 only? */ |
| @@ -121,8 +122,8 @@ | |||
| 121 | #define SWRCON (*(REG32_PTR_T)(0x3C500030)) /* Software reset control register */ | 122 | #define SWRCON (*(REG32_PTR_T)(0x3C500030)) /* Software reset control register */ |
| 122 | #define RSTSR (*(REG32_PTR_T)(0x3C500034)) /* Reset status register */ | 123 | #define RSTSR (*(REG32_PTR_T)(0x3C500034)) /* Reset status register */ |
| 123 | #define DSPCLKMD (*(REG32_PTR_T)(0x3C500038)) /* DSP clock mode register */ | 124 | #define DSPCLKMD (*(REG32_PTR_T)(0x3C500038)) /* DSP clock mode register */ |
| 124 | #define CLKCON2 (*(REG32_PTR_T)(0x3C50003C)) /* clock control register 2 */ | 125 | #define CLKCON2 (*(REG32_PTR_T)(0x3C50003C)) /* Clock control register 2 */ |
| 125 | #define PWRCONEXT (*(REG32_PTR_T)(0x3C500040)) | 126 | #define PWRCONEXT (*(REG32_PTR_T)(0x3C500040)) /* Clock power control register 2 */ |
| 126 | 127 | ||
| 127 | /* 06. INTERRUPT CONTROLLER UNIT */ | 128 | /* 06. INTERRUPT CONTROLLER UNIT */ |
| 128 | #define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */ | 129 | #define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */ |