diff options
Diffstat (limited to 'firmware/export/jz4760b.h')
-rw-r--r-- | firmware/export/jz4760b.h | 148 |
1 files changed, 77 insertions, 71 deletions
diff --git a/firmware/export/jz4760b.h b/firmware/export/jz4760b.h index c523cc64c9..c35e26767f 100644 --- a/firmware/export/jz4760b.h +++ b/firmware/export/jz4760b.h | |||
@@ -1332,7 +1332,7 @@ do { \ | |||
1332 | #define DMAC_DCCSR_CT (1 << 1) /* count terminated */ | 1332 | #define DMAC_DCCSR_CT (1 << 1) /* count terminated */ |
1333 | #define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */ | 1333 | #define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */ |
1334 | 1334 | ||
1335 | // DMA channel command register | 1335 | // DMA channel command register |
1336 | #define DMAC_DCMD_EACKS_LOW (1 << 31) /* External DACK Output Level Select, active low */ | 1336 | #define DMAC_DCMD_EACKS_LOW (1 << 31) /* External DACK Output Level Select, active low */ |
1337 | #define DMAC_DCMD_EACKS_HIGH (0 << 31) /* External DACK Output Level Select, active high */ | 1337 | #define DMAC_DCMD_EACKS_HIGH (0 << 31) /* External DACK Output Level Select, active high */ |
1338 | #define DMAC_DCMD_EACKM_WRITE (1 << 30) /* External DACK Output Mode Select, output in write cycle */ | 1338 | #define DMAC_DCMD_EACKM_WRITE (1 << 30) /* External DACK Output Mode Select, output in write cycle */ |
@@ -3090,7 +3090,7 @@ static __inline__ int __bdmac_get_irq(void) | |||
3090 | #define CIM_CTRL_RXF_TRIGM (1 << 9) | 3090 | #define CIM_CTRL_RXF_TRIGM (1 << 9) |
3091 | #define CIM_CTRL_RXF_OFM (1 << 8) | 3091 | #define CIM_CTRL_RXF_OFM (1 << 8) |
3092 | #define CIM_CTRL_DMA_SYNC (1 << 7) /*when change DA, do frame sync */ | 3092 | #define CIM_CTRL_DMA_SYNC (1 << 7) /*when change DA, do frame sync */ |
3093 | #define CIM_CTRL_H_SYNC (1 << 6) /*Enable horizental sync when CIMCFG.SEP is 1*/ | 3093 | #define CIM_CTRL_H_SYNC (1 << 6) /*Enable horizental sync when CIMCFG.SEP is 1*/ |
3094 | 3094 | ||
3095 | #define CIM_CTRL_PPW_BIT 3 | 3095 | #define CIM_CTRL_PPW_BIT 3 |
3096 | #define CIM_CTRL_PPW_MASK (0x3 << CIM_CTRL_PPW_BIT) | 3096 | #define CIM_CTRL_PPW_MASK (0x3 << CIM_CTRL_PPW_BIT) |
@@ -3632,7 +3632,7 @@ static __inline__ int __bdmac_get_irq(void) | |||
3632 | #define USBCDR_OTGDIV_LSB 0 /* USBCDR bit */ | 3632 | #define USBCDR_OTGDIV_LSB 0 /* USBCDR bit */ |
3633 | #define USBCDR_OTGDIV_MASK BITS_H2L(5, USBCDR_OTGDIV_LSB) | 3633 | #define USBCDR_OTGDIV_MASK BITS_H2L(5, USBCDR_OTGDIV_LSB) |
3634 | 3634 | ||
3635 | /* I2S device clock divider register(I2SCDR) */ | 3635 | /* I2S device clock divider register(I2SCDR) */ |
3636 | #define I2SCDR_I2CS BIT31 | 3636 | #define I2SCDR_I2CS BIT31 |
3637 | #define I2SCDR_I2PCS BIT30 | 3637 | #define I2SCDR_I2PCS BIT30 |
3638 | 3638 | ||
@@ -4114,6 +4114,12 @@ static inline void __cpm_select_msc_clk(int sd) | |||
4114 | REG_CPM_CPCCR |= CPCCR_CE; | 4114 | REG_CPM_CPCCR |= CPCCR_CE; |
4115 | } | 4115 | } |
4116 | 4116 | ||
4117 | /* MSC clock */ | ||
4118 | static __inline__ unsigned int __cpm_get_mscclk(void) | ||
4119 | { | ||
4120 | return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1); | ||
4121 | } | ||
4122 | |||
4117 | #endif /* __MIPS_ASSEMBLER */ | 4123 | #endif /* __MIPS_ASSEMBLER */ |
4118 | 4124 | ||
4119 | #define DDRC_BASE 0xB3020000 | 4125 | #define DDRC_BASE 0xB3020000 |
@@ -4163,7 +4169,7 @@ static inline void __cpm_select_msc_clk(int sd) | |||
4163 | /* DDRC Status Register */ | 4169 | /* DDRC Status Register */ |
4164 | #define DDRC_ST_ENDIAN (1 << 7) /* 0 Little data endian | 4170 | #define DDRC_ST_ENDIAN (1 << 7) /* 0 Little data endian |
4165 | 1 Big data endian */ | 4171 | 1 Big data endian */ |
4166 | #define DDRC_ST_MISS (1 << 6) | 4172 | #define DDRC_ST_MISS (1 << 6) |
4167 | 4173 | ||
4168 | #define DDRC_ST_DPDN (1 << 5) /* 0 DDR memory is NOT in deep-power-down state | 4174 | #define DDRC_ST_DPDN (1 << 5) /* 0 DDR memory is NOT in deep-power-down state |
4169 | 1 DDR memory is in deep-power-down state */ | 4175 | 1 DDR memory is in deep-power-down state */ |
@@ -4289,14 +4295,14 @@ static inline void __cpm_select_msc_clk(int sd) | |||
4289 | defined by CMD field */ | 4295 | defined by CMD field */ |
4290 | /* DDRC Mode Register Set */ | 4296 | /* DDRC Mode Register Set */ |
4291 | #define DDR_MRS_PD_BIT (1 << 10) /* Active power down exit time */ | 4297 | #define DDR_MRS_PD_BIT (1 << 10) /* Active power down exit time */ |
4292 | #define DDR_MRS_PD_MASK (1 << DDR_MRS_PD_BIT) | 4298 | #define DDR_MRS_PD_MASK (1 << DDR_MRS_PD_BIT) |
4293 | #define DDR_MRS_PD_FAST_EXIT (0 << 10) | 4299 | #define DDR_MRS_PD_FAST_EXIT (0 << 10) |
4294 | #define DDR_MRS_PD_SLOW_EXIT (1 << 10) | 4300 | #define DDR_MRS_PD_SLOW_EXIT (1 << 10) |
4295 | #define DDR_MRS_WR_BIT (1 << 9) /* Write Recovery for autoprecharge */ | 4301 | #define DDR_MRS_WR_BIT (1 << 9) /* Write Recovery for autoprecharge */ |
4296 | #define DDR_MRS_WR_MASK (7 << DDR_MRS_WR_BIT) | 4302 | #define DDR_MRS_WR_MASK (7 << DDR_MRS_WR_BIT) |
4297 | #define DDR_MRS_DLL_RST (1 << 8) /* DLL Reset */ | 4303 | #define DDR_MRS_DLL_RST (1 << 8) /* DLL Reset */ |
4298 | #define DDR_MRS_TM_BIT 7 /* Operating Mode */ | 4304 | #define DDR_MRS_TM_BIT 7 /* Operating Mode */ |
4299 | #define DDR_MRS_TM_MASK (1 << DDR_MRS_OM_BIT) | 4305 | #define DDR_MRS_TM_MASK (1 << DDR_MRS_OM_BIT) |
4300 | #define DDR_MRS_TM_NORMAL (0 << DDR_MRS_OM_BIT) | 4306 | #define DDR_MRS_TM_NORMAL (0 << DDR_MRS_OM_BIT) |
4301 | #define DDR_MRS_TM_TEST (1 << DDR_MRS_OM_BIT) | 4307 | #define DDR_MRS_TM_TEST (1 << DDR_MRS_OM_BIT) |
4302 | #define DDR_MRS_CAS_BIT 4 /* CAS Latency */ | 4308 | #define DDR_MRS_CAS_BIT 4 /* CAS Latency */ |
@@ -4423,11 +4429,11 @@ static inline void __cpm_select_msc_clk(int sd) | |||
4423 | #define DDRC_DQS_DET (1 << 24) /* Start delay detecting. */ | 4429 | #define DDRC_DQS_DET (1 << 24) /* Start delay detecting. */ |
4424 | #define DDRC_DQS_AUTO (1 << 23) /* Hardware auto-detect & set delay line */ | 4430 | #define DDRC_DQS_AUTO (1 << 23) /* Hardware auto-detect & set delay line */ |
4425 | #define DDRC_DQS_CLKD_BIT 16 /* CLKD is reference value for setting WDQS and RDQS.*/ | 4431 | #define DDRC_DQS_CLKD_BIT 16 /* CLKD is reference value for setting WDQS and RDQS.*/ |
4426 | #define DDRC_DQS_CLKD_MASK (0x3f << DDRC_DQS_CLKD_BIT) | 4432 | #define DDRC_DQS_CLKD_MASK (0x3f << DDRC_DQS_CLKD_BIT) |
4427 | #define DDRC_DQS_WDQS_BIT 8 /* Set delay element number to write DQS delay-line. */ | 4433 | #define DDRC_DQS_WDQS_BIT 8 /* Set delay element number to write DQS delay-line. */ |
4428 | #define DDRC_DQS_WDQS_MASK (0x3f << DDRC_DQS_WDQS_BIT) | 4434 | #define DDRC_DQS_WDQS_MASK (0x3f << DDRC_DQS_WDQS_BIT) |
4429 | #define DDRC_DQS_RDQS_BIT 0 /* Set delay element number to read DQS delay-line. */ | 4435 | #define DDRC_DQS_RDQS_BIT 0 /* Set delay element number to read DQS delay-line. */ |
4430 | #define DDRC_DQS_RDQS_MASK (0x3f << DDRC_DQS_RDQS_BIT) | 4436 | #define DDRC_DQS_RDQS_MASK (0x3f << DDRC_DQS_RDQS_BIT) |
4431 | 4437 | ||
4432 | /* DDRC DQS Delay Adjust Register */ | 4438 | /* DDRC DQS Delay Adjust Register */ |
4433 | #define DDRC_DQS_ADJDQSCON_BIT 16 | 4439 | #define DDRC_DQS_ADJDQSCON_BIT 16 |
@@ -4443,7 +4449,7 @@ static inline void __cpm_select_msc_clk(int sd) | |||
4443 | #define DDRC_MMAP_BASE_BIT 8 /* base address */ | 4449 | #define DDRC_MMAP_BASE_BIT 8 /* base address */ |
4444 | #define DDRC_MMAP_BASE_MASK (0xff << DDRC_MMAP_BASE_BIT) | 4450 | #define DDRC_MMAP_BASE_MASK (0xff << DDRC_MMAP_BASE_BIT) |
4445 | #define DDRC_MMAP_MASK_BIT 0 /* address mask */ | 4451 | #define DDRC_MMAP_MASK_BIT 0 /* address mask */ |
4446 | #define DDRC_MMAP_MASK_MASK (0xff << DDRC_MMAP_MASK_BIT) | 4452 | #define DDRC_MMAP_MASK_MASK (0xff << DDRC_MMAP_MASK_BIT) |
4447 | 4453 | ||
4448 | #define DDRC_MMAP0_BASE (0x20 << DDRC_MMAP_BASE_BIT) | 4454 | #define DDRC_MMAP0_BASE (0x20 << DDRC_MMAP_BASE_BIT) |
4449 | #define DDRC_MMAP1_BASE_64M (0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/ | 4455 | #define DDRC_MMAP1_BASE_64M (0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/ |
@@ -4609,8 +4615,8 @@ static inline void __cpm_select_msc_clk(int sd) | |||
4609 | * EMC (External Memory Controller) | 4615 | * EMC (External Memory Controller) |
4610 | *************************************************************************/ | 4616 | *************************************************************************/ |
4611 | #define EMC_BCR (EMC_BASE + 0x00) /* Bus Control Register */ | 4617 | #define EMC_BCR (EMC_BASE + 0x00) /* Bus Control Register */ |
4612 | #define EMC_PMEMBS1 (EMC_BASE + 0x6004) | 4618 | #define EMC_PMEMBS1 (EMC_BASE + 0x6004) |
4613 | #define EMC_PMEMBS0 (EMC_BASE + 0x6008) | 4619 | #define EMC_PMEMBS0 (EMC_BASE + 0x6008) |
4614 | #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 ??? */ | 4620 | #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 ??? */ |
4615 | #define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ | 4621 | #define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ |
4616 | #define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ | 4622 | #define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ |
@@ -4874,7 +4880,7 @@ static inline void __cpm_select_msc_clk(int sd) | |||
4874 | 4880 | ||
4875 | #define I2C_CTRL_STPHLD (1 << 7) /* Stop Hold Enable bit: when tx fifo empty, 0: send stop 1: never send stop*/ | 4881 | #define I2C_CTRL_STPHLD (1 << 7) /* Stop Hold Enable bit: when tx fifo empty, 0: send stop 1: never send stop*/ |
4876 | #define I2C_CTRL_SLVDIS (1 << 6) /* after reset slave is disabled*/ | 4882 | #define I2C_CTRL_SLVDIS (1 << 6) /* after reset slave is disabled*/ |
4877 | #define I2C_CTRL_REST (1 << 5) | 4883 | #define I2C_CTRL_REST (1 << 5) |
4878 | #define I2C_CTRL_MATP (1 << 4) /* 1: 10bit address 0: 7bit addressing*/ | 4884 | #define I2C_CTRL_MATP (1 << 4) /* 1: 10bit address 0: 7bit addressing*/ |
4879 | #define I2C_CTRL_SATP (1 << 3) /* 1: 10bit address 0: 7bit address*/ | 4885 | #define I2C_CTRL_SATP (1 << 3) /* 1: 10bit address 0: 7bit address*/ |
4880 | #define I2C_CTRL_SPDF (2 << 1) /* fast mode 400kbps */ | 4886 | #define I2C_CTRL_SPDF (2 << 1) /* fast mode 400kbps */ |
@@ -4906,7 +4912,7 @@ static inline void __cpm_select_msc_clk(int sd) | |||
4906 | #define I2C_INTST_ISTP (1 << 9) | 4912 | #define I2C_INTST_ISTP (1 << 9) |
4907 | #define I2C_INTST_IACT (1 << 8) | 4913 | #define I2C_INTST_IACT (1 << 8) |
4908 | #define I2C_INTST_RXDN (1 << 7) | 4914 | #define I2C_INTST_RXDN (1 << 7) |
4909 | #define I2C_INTST_TXABT (1 << 6) | 4915 | #define I2C_INTST_TXABT (1 << 6) |
4910 | #define I2C_INTST_RDREQ (1 << 5) | 4916 | #define I2C_INTST_RDREQ (1 << 5) |
4911 | #define I2C_INTST_TXEMP (1 << 4) | 4917 | #define I2C_INTST_TXEMP (1 << 4) |
4912 | #define I2C_INTST_TXOF (1 << 3) | 4918 | #define I2C_INTST_TXOF (1 << 3) |
@@ -4944,7 +4950,7 @@ static inline void __cpm_select_msc_clk(int sd) | |||
4944 | 4950 | ||
4945 | /* I2C Enable (I2C_ENB) */ | 4951 | /* I2C Enable (I2C_ENB) */ |
4946 | 4952 | ||
4947 | #define I2C_ENB_I2CENB (1 << 0) /* Enable the i2c */ | 4953 | #define I2C_ENB_I2CENB (1 << 0) /* Enable the i2c */ |
4948 | 4954 | ||
4949 | /* I2C Status Register (I2C_STA) */ | 4955 | /* I2C Status Register (I2C_STA) */ |
4950 | 4956 | ||
@@ -4992,8 +4998,8 @@ static inline void __cpm_select_msc_clk(int sd) | |||
4992 | #define I2C_ENSTA_SLVRDLST (1 << 2) | 4998 | #define I2C_ENSTA_SLVRDLST (1 << 2) |
4993 | #define I2C_ENSTA_SLVDISB (1 << 1) | 4999 | #define I2C_ENSTA_SLVDISB (1 << 1) |
4994 | #define I2C_ENSTA_I2CEN (1 << 0) /* when read as 1, i2c is deemed to be in an enabled state | 5000 | #define I2C_ENSTA_I2CEN (1 << 0) /* when read as 1, i2c is deemed to be in an enabled state |
4995 | when read as 0, i2c is deemed completely inactive. The cpu can | 5001 | when read as 0, i2c is deemed completely inactive. The cpu can |
4996 | safely read this bit anytime .When this bit is read as 0 ,the cpu can | 5002 | safely read this bit anytime .When this bit is read as 0 ,the cpu can |
4997 | safely read SLVRDLST and SLVDISB */ | 5003 | safely read SLVRDLST and SLVDISB */ |
4998 | 5004 | ||
4999 | /* I2C standard mode high count register(I2CSHCNT) */ | 5005 | /* I2C standard mode high count register(I2CSHCNT) */ |
@@ -5036,7 +5042,7 @@ static inline void __cpm_select_msc_clk(int sd) | |||
5036 | #define __i2c_nsend_stop(n) SETREG8(I2C_CTRL(n), I2C_CTRL_STPHLD) | 5042 | #define __i2c_nsend_stop(n) SETREG8(I2C_CTRL(n), I2C_CTRL_STPHLD) |
5037 | 5043 | ||
5038 | #define __i2c_set_dma_td_level(n,data) OUTREG8(I2C_DMATDLR(n),data) | 5044 | #define __i2c_set_dma_td_level(n,data) OUTREG8(I2C_DMATDLR(n),data) |
5039 | #define __i2c_set_dma_rd_level(n,data) OUTREG8(I2C_DMARDLR(n),data) | 5045 | #define __i2c_set_dma_rd_level(n,data) OUTREG8(I2C_DMARDLR(n),data) |
5040 | 5046 | ||
5041 | /* | 5047 | /* |
5042 | #define __i2c_set_clk(dev_clk, i2c_clk) \ | 5048 | #define __i2c_set_clk(dev_clk, i2c_clk) \ |
@@ -5498,9 +5504,9 @@ do { \ | |||
5498 | #define REG_LCD_SIZE0 REG32(LCD_SIZE0) | 5504 | #define REG_LCD_SIZE0 REG32(LCD_SIZE0) |
5499 | #define REG_LCD_SIZE0_PART2 REG32(LCD_SIZE0_PART2) | 5505 | #define REG_LCD_SIZE0_PART2 REG32(LCD_SIZE0_PART2) |
5500 | #define REG_LCD_SIZE1 REG32(LCD_SIZE1) | 5506 | #define REG_LCD_SIZE1 REG32(LCD_SIZE1) |
5501 | 5507 | ||
5502 | #define REG_LCD_RGBC REG16(LCD_RGBC) | 5508 | #define REG_LCD_RGBC REG16(LCD_RGBC) |
5503 | 5509 | ||
5504 | #define REG_LCD_VSYNC REG32(LCD_VSYNC) | 5510 | #define REG_LCD_VSYNC REG32(LCD_VSYNC) |
5505 | #define REG_LCD_HSYNC REG32(LCD_HSYNC) | 5511 | #define REG_LCD_HSYNC REG32(LCD_HSYNC) |
5506 | #define REG_LCD_PS REG32(LCD_PS) | 5512 | #define REG_LCD_PS REG32(LCD_PS) |
@@ -5946,8 +5952,8 @@ do { \ | |||
5946 | 5952 | ||
5947 | #define __lcd_set_24_tftpnl() ( REG_LCD_CFG |= LCD_CFG_MODE_TFT_24BIT ) | 5953 | #define __lcd_set_24_tftpnl() ( REG_LCD_CFG |= LCD_CFG_MODE_TFT_24BIT ) |
5948 | 5954 | ||
5949 | /* | 5955 | /* |
5950 | * n=1,2,4,8 for single mono-STN | 5956 | * n=1,2,4,8 for single mono-STN |
5951 | * n=4,8 for dual mono-STN | 5957 | * n=4,8 for dual mono-STN |
5952 | */ | 5958 | */ |
5953 | #define __lcd_set_panel_datawidth(n) \ | 5959 | #define __lcd_set_panel_datawidth(n) \ |
@@ -6706,12 +6712,12 @@ static __inline__ int __mdmac_get_irq(void) | |||
6706 | #define MSC_CMDAT_SEND_AS_STOP (1 << 16) | 6712 | #define MSC_CMDAT_SEND_AS_STOP (1 << 16) |
6707 | #define MSC_CMDAT_RTRG_BIT 14 | 6713 | #define MSC_CMDAT_RTRG_BIT 14 |
6708 | #define MSC_CMDAT_RTRG_EQUALT_8 (0x0 << MSC_CMDAT_RTRG_BIT) /*reset value*/ | 6714 | #define MSC_CMDAT_RTRG_EQUALT_8 (0x0 << MSC_CMDAT_RTRG_BIT) /*reset value*/ |
6709 | #define MSC_CMDAT_RTRG_EQUALT_16 (0x1 << MSC_CMDAT_RTRG_BIT) | 6715 | #define MSC_CMDAT_RTRG_EQUALT_16 (0x1 << MSC_CMDAT_RTRG_BIT) |
6710 | #define MSC_CMDAT_RTRG_EQUALT_24 (0x2 << MSC_CMDAT_RTRG_BIT) | 6716 | #define MSC_CMDAT_RTRG_EQUALT_24 (0x2 << MSC_CMDAT_RTRG_BIT) |
6711 | 6717 | ||
6712 | #define MSC_CMDAT_TTRG_BIT 12 | 6718 | #define MSC_CMDAT_TTRG_BIT 12 |
6713 | #define MSC_CMDAT_TTRG_LESS_8 (0x0 << MSC_CMDAT_TTRG_BIT) /*reset value*/ | 6719 | #define MSC_CMDAT_TTRG_LESS_8 (0x0 << MSC_CMDAT_TTRG_BIT) /*reset value*/ |
6714 | #define MSC_CMDAT_TTRG_LESS_16 (0x1 << MSC_CMDAT_TTRG_BIT) | 6720 | #define MSC_CMDAT_TTRG_LESS_16 (0x1 << MSC_CMDAT_TTRG_BIT) |
6715 | #define MSC_CMDAT_TTRG_LESS_24 (0x2 << MSC_CMDAT_TTRG_BIT) | 6721 | #define MSC_CMDAT_TTRG_LESS_24 (0x2 << MSC_CMDAT_TTRG_BIT) |
6716 | #define MSC_CMDAT_STOP_ABORT (1 << 11) | 6722 | #define MSC_CMDAT_STOP_ABORT (1 << 11) |
6717 | #define MSC_CMDAT_BUS_WIDTH_BIT 9 | 6723 | #define MSC_CMDAT_BUS_WIDTH_BIT 9 |
@@ -7487,7 +7493,7 @@ do { \ | |||
7487 | #define WENR_WENPAT_WRITABLE (0xa55a) | 7493 | #define WENR_WENPAT_WRITABLE (0xa55a) |
7488 | 7494 | ||
7489 | /* Hibernate scratch pattern register(HSPR) */ | 7495 | /* Hibernate scratch pattern register(HSPR) */ |
7490 | #define HSPR_RTCV 0x52544356 /* The value is 'RTCV', means rtc is valid */ | 7496 | #define HSPR_RTCV 0x52544356 /* The value is 'RTCV', means rtc is valid */ |
7491 | 7497 | ||
7492 | #ifndef __MIPS_ASSEMBLER | 7498 | #ifndef __MIPS_ASSEMBLER |
7493 | 7499 | ||
@@ -7926,7 +7932,7 @@ do { \ | |||
7926 | #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ | 7932 | #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ |
7927 | #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ | 7933 | #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ |
7928 | #define SSI_CR1_TTRG_BIT 16 /* SSI1 TX trigger */ | 7934 | #define SSI_CR1_TTRG_BIT 16 /* SSI1 TX trigger */ |
7929 | #define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT) | 7935 | #define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT) |
7930 | #define SSI_CR1_MCOM_BIT 12 | 7936 | #define SSI_CR1_MCOM_BIT 12 |
7931 | #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) | 7937 | #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) |
7932 | #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ | 7938 | #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ |
@@ -8112,7 +8118,7 @@ do { \ | |||
8112 | /* frmhl,endian,mcom,flen,pha,pol MASK */ | 8118 | /* frmhl,endian,mcom,flen,pha,pol MASK */ |
8113 | #define SSICR1_MISC_MASK \ | 8119 | #define SSICR1_MISC_MASK \ |
8114 | ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ | 8120 | ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ |
8115 | | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) | 8121 | | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) |
8116 | 8122 | ||
8117 | #define __ssi_spi_set_misc(n,frmhl,endian,flen,mcom,pha,pol) \ | 8123 | #define __ssi_spi_set_misc(n,frmhl,endian,flen,mcom,pha,pol) \ |
8118 | do { \ | 8124 | do { \ |
@@ -8127,7 +8133,7 @@ do { \ | |||
8127 | #define __ssi_set_lsb(n) ( REG_SSI_CR1(n) |= SSI_CR1_LFST ) | 8133 | #define __ssi_set_lsb(n) ( REG_SSI_CR1(n) |= SSI_CR1_LFST ) |
8128 | 8134 | ||
8129 | #define __ssi_set_frame_length(n, m) \ | 8135 | #define __ssi_set_frame_length(n, m) \ |
8130 | REG_SSI_CR1(n) = (REG_SSI_CR1(n) & ~SSI_CR1_FLEN_MASK) | (((m) - 2) << 4) | 8136 | REG_SSI_CR1(n) = (REG_SSI_CR1(n) & ~SSI_CR1_FLEN_MASK) | (((m) - 2) << 4) |
8131 | 8137 | ||
8132 | /* m = 1 - 16 */ | 8138 | /* m = 1 - 16 */ |
8133 | #define __ssi_set_microwire_command_length(n,m) \ | 8139 | #define __ssi_set_microwire_command_length(n,m) \ |
@@ -8510,7 +8516,7 @@ do { \ | |||
8510 | #define TSSI_DCMD ( TSSI0_BASE + 0x6c ) | 8516 | #define TSSI_DCMD ( TSSI0_BASE + 0x6c ) |
8511 | #define TSSI_DST ( TSSI0_BASE + 0x70 ) | 8517 | #define TSSI_DST ( TSSI0_BASE + 0x70 ) |
8512 | #define TSSI_TC ( TSSI0_BASE + 0x74 ) | 8518 | #define TSSI_TC ( TSSI0_BASE + 0x74 ) |
8513 | 8519 | ||
8514 | #define REG_TSSI_ENA REG8( TSSI_ENA ) | 8520 | #define REG_TSSI_ENA REG8( TSSI_ENA ) |
8515 | #define REG_TSSI_CFG REG16( TSSI_CFG ) | 8521 | #define REG_TSSI_CFG REG16( TSSI_CFG ) |
8516 | #define REG_TSSI_CTRL REG8( TSSI_CTRL ) | 8522 | #define REG_TSSI_CTRL REG8( TSSI_CTRL ) |
@@ -8559,7 +8565,7 @@ do { \ | |||
8559 | 8565 | ||
8560 | /* mode of adding data 0 select bit */ | 8566 | /* mode of adding data 0 select bit */ |
8561 | #define TSSI_CFG_TRANS_MD_BIT 10 | 8567 | #define TSSI_CFG_TRANS_MD_BIT 10 |
8562 | #define TSSI_CFG_TRANS_MD_MASK ( 0x3 << TSSI_CFG_TRANS_MD_BIT) | 8568 | #define TSSI_CFG_TRANS_MD_MASK ( 0x3 << TSSI_CFG_TRANS_MD_BIT) |
8563 | #define TSSI_CFG_TRANS_MD_0 (0 << TSSI_CFG_TRANS_MD_BIT) | 8569 | #define TSSI_CFG_TRANS_MD_0 (0 << TSSI_CFG_TRANS_MD_BIT) |
8564 | #define TSSI_CFG_TRANS_MD_1 (1 << TSSI_CFG_TRANS_MD_BIT) | 8570 | #define TSSI_CFG_TRANS_MD_1 (1 << TSSI_CFG_TRANS_MD_BIT) |
8565 | #define TSSI_CFG_TRANS_MD_2 (2 << TSSI_CFG_TRANS_MD_BIT) | 8571 | #define TSSI_CFG_TRANS_MD_2 (2 << TSSI_CFG_TRANS_MD_BIT) |
@@ -8592,37 +8598,37 @@ do { \ | |||
8592 | 8598 | ||
8593 | /* TSSI PID enable register */ | 8599 | /* TSSI PID enable register */ |
8594 | #define TSSI_PEN_EN00 ( 1 << 0 ) /* enable PID n */ | 8600 | #define TSSI_PEN_EN00 ( 1 << 0 ) /* enable PID n */ |
8595 | #define TSSI_PEN_EN10 ( 1 << 1 ) | 8601 | #define TSSI_PEN_EN10 ( 1 << 1 ) |
8596 | #define TSSI_PEN_EN20 ( 1 << 2 ) | 8602 | #define TSSI_PEN_EN20 ( 1 << 2 ) |
8597 | #define TSSI_PEN_EN30 ( 1 << 3 ) | 8603 | #define TSSI_PEN_EN30 ( 1 << 3 ) |
8598 | #define TSSI_PEN_EN40 ( 1 << 4 ) | 8604 | #define TSSI_PEN_EN40 ( 1 << 4 ) |
8599 | #define TSSI_PEN_EN50 ( 1 << 5 ) | 8605 | #define TSSI_PEN_EN50 ( 1 << 5 ) |
8600 | #define TSSI_PEN_EN60 ( 1 << 6 ) | 8606 | #define TSSI_PEN_EN60 ( 1 << 6 ) |
8601 | #define TSSI_PEN_EN70 ( 1 << 7 ) | 8607 | #define TSSI_PEN_EN70 ( 1 << 7 ) |
8602 | #define TSSI_PEN_EN80 ( 1 << 8 ) | 8608 | #define TSSI_PEN_EN80 ( 1 << 8 ) |
8603 | #define TSSI_PEN_EN90 ( 1 << 9 ) | 8609 | #define TSSI_PEN_EN90 ( 1 << 9 ) |
8604 | #define TSSI_PEN_EN100 ( 1 << 10 ) | 8610 | #define TSSI_PEN_EN100 ( 1 << 10 ) |
8605 | #define TSSI_PEN_EN110 ( 1 << 11 ) | 8611 | #define TSSI_PEN_EN110 ( 1 << 11 ) |
8606 | #define TSSI_PEN_EN120 ( 1 << 12 ) | 8612 | #define TSSI_PEN_EN120 ( 1 << 12 ) |
8607 | #define TSSI_PEN_EN130 ( 1 << 13 ) | 8613 | #define TSSI_PEN_EN130 ( 1 << 13 ) |
8608 | #define TSSI_PEN_EN140 ( 1 << 14 ) | 8614 | #define TSSI_PEN_EN140 ( 1 << 14 ) |
8609 | #define TSSI_PEN_EN150 ( 1 << 15 ) | 8615 | #define TSSI_PEN_EN150 ( 1 << 15 ) |
8610 | #define TSSI_PEN_EN01 ( 1 << 16 ) | 8616 | #define TSSI_PEN_EN01 ( 1 << 16 ) |
8611 | #define TSSI_PEN_EN11 ( 1 << 17 ) | 8617 | #define TSSI_PEN_EN11 ( 1 << 17 ) |
8612 | #define TSSI_PEN_EN21 ( 1 << 18 ) | 8618 | #define TSSI_PEN_EN21 ( 1 << 18 ) |
8613 | #define TSSI_PEN_EN31 ( 1 << 19 ) | 8619 | #define TSSI_PEN_EN31 ( 1 << 19 ) |
8614 | #define TSSI_PEN_EN41 ( 1 << 20 ) | 8620 | #define TSSI_PEN_EN41 ( 1 << 20 ) |
8615 | #define TSSI_PEN_EN51 ( 1 << 21 ) | 8621 | #define TSSI_PEN_EN51 ( 1 << 21 ) |
8616 | #define TSSI_PEN_EN61 ( 1 << 22 ) | 8622 | #define TSSI_PEN_EN61 ( 1 << 22 ) |
8617 | #define TSSI_PEN_EN71 ( 1 << 23 ) | 8623 | #define TSSI_PEN_EN71 ( 1 << 23 ) |
8618 | #define TSSI_PEN_EN81 ( 1 << 24 ) | 8624 | #define TSSI_PEN_EN81 ( 1 << 24 ) |
8619 | #define TSSI_PEN_EN91 ( 1 << 25 ) | 8625 | #define TSSI_PEN_EN91 ( 1 << 25 ) |
8620 | #define TSSI_PEN_EN101 ( 1 << 26 ) | 8626 | #define TSSI_PEN_EN101 ( 1 << 26 ) |
8621 | #define TSSI_PEN_EN111 ( 1 << 27 ) | 8627 | #define TSSI_PEN_EN111 ( 1 << 27 ) |
8622 | #define TSSI_PEN_EN121 ( 1 << 28 ) | 8628 | #define TSSI_PEN_EN121 ( 1 << 28 ) |
8623 | #define TSSI_PEN_EN131 ( 1 << 29 ) | 8629 | #define TSSI_PEN_EN131 ( 1 << 29 ) |
8624 | #define TSSI_PEN_EN141 ( 1 << 30 ) | 8630 | #define TSSI_PEN_EN141 ( 1 << 30 ) |
8625 | #define TSSI_PEN_EN151 ( 1 << 31 ) | 8631 | #define TSSI_PEN_EN151 ( 1 << 31 ) |
8626 | //#define TSSI_PEN_PID0 ( 1 << 31 ) /* PID filter enable PID0 */ | 8632 | //#define TSSI_PEN_PID0 ( 1 << 31 ) /* PID filter enable PID0 */ |
8627 | 8633 | ||
8628 | /* TSSI Data Number Registers */ | 8634 | /* TSSI Data Number Registers */ |
@@ -8664,7 +8670,7 @@ do { \ | |||
8664 | /* TSSI Transfer Control Registers */ | 8670 | /* TSSI Transfer Control Registers */ |
8665 | #define TSSI_TC_OP_BIT 4 | 8671 | #define TSSI_TC_OP_BIT 4 |
8666 | #define TSSI_TC_OP_MASK (0x3 << TSSI_TC_OP_BIT) | 8672 | #define TSSI_TC_OP_MASK (0x3 << TSSI_TC_OP_BIT) |
8667 | //////////////////#define TSSI_TC_OP_0 ( | 8673 | //////////////////#define TSSI_TC_OP_0 ( |
8668 | #define TSSI_TC_OPE (1 << 2) | 8674 | #define TSSI_TC_OPE (1 << 2) |
8669 | #define TSSI_TC_EME (1 << 1) | 8675 | #define TSSI_TC_EME (1 << 1) |
8670 | #define TSSI_TC_APM (1 << 0) | 8676 | #define TSSI_TC_APM (1 << 0) |
@@ -8733,7 +8739,7 @@ do { \ | |||
8733 | #define __tssi_disable_ovrn_irq() ( REG_TSSI_CTRL |= TSSI_CTRL_OVRNM ) | 8739 | #define __tssi_disable_ovrn_irq() ( REG_TSSI_CTRL |= TSSI_CTRL_OVRNM ) |
8734 | 8740 | ||
8735 | #define __tssi_enable_trig_irq() ( REG_TSSI_CTRL &= ~TSSI_CTRL_TRIGM ) | 8741 | #define __tssi_enable_trig_irq() ( REG_TSSI_CTRL &= ~TSSI_CTRL_TRIGM ) |
8736 | #define __tssi_disable_trig_irq() ( REG_TSSI_CTRL |= TSSI_CTRL_TRIGM ) | 8742 | #define __tssi_disable_trig_irq() ( REG_TSSI_CTRL |= TSSI_CTRL_TRIGM ) |
8737 | 8743 | ||
8738 | #define __tssi_state_is_dtr() ( REG_TSSI_STAT & TSSI_STAT_DTR ) | 8744 | #define __tssi_state_is_dtr() ( REG_TSSI_STAT & TSSI_STAT_DTR ) |
8739 | #define __tssi_state_is_overrun() ( REG_TSSI_STAT & TSSI_STAT_OVRN ) | 8745 | #define __tssi_state_is_overrun() ( REG_TSSI_STAT & TSSI_STAT_OVRN ) |
@@ -8790,7 +8796,7 @@ do { \ | |||
8790 | 8796 | ||
8791 | #endif /* __MIPS_ASSEMBLER */ | 8797 | #endif /* __MIPS_ASSEMBLER */ |
8792 | 8798 | ||
8793 | #define TVE_BASE 0xB3050100 | 8799 | #define TVE_BASE 0xB3050100 |
8794 | 8800 | ||
8795 | /************************************************************************* | 8801 | /************************************************************************* |
8796 | * TVE (TV Encoder Controller) | 8802 | * TVE (TV Encoder Controller) |
@@ -8829,8 +8835,8 @@ do { \ | |||
8829 | #define TVE_CTRL_EYCBCR (1 << 25) /* YCbCr_enable */ | 8835 | #define TVE_CTRL_EYCBCR (1 << 25) /* YCbCr_enable */ |
8830 | #define TVE_CTRL_ECVBS (1 << 24) /* 1: cvbs_enable 0: s-video*/ | 8836 | #define TVE_CTRL_ECVBS (1 << 24) /* 1: cvbs_enable 0: s-video*/ |
8831 | #define TVE_CTRL_DAPD3 (1 << 23) /* DAC 3 power down */ | 8837 | #define TVE_CTRL_DAPD3 (1 << 23) /* DAC 3 power down */ |
8832 | #define TVE_CTRL_DAPD2 (1 << 22) /* DAC 2 power down */ | 8838 | #define TVE_CTRL_DAPD2 (1 << 22) /* DAC 2 power down */ |
8833 | #define TVE_CTRL_DAPD1 (1 << 21) /* DAC 1 power down */ | 8839 | #define TVE_CTRL_DAPD1 (1 << 21) /* DAC 1 power down */ |
8834 | #define TVE_CTRL_DAPD (1 << 20) /* power down all DACs */ | 8840 | #define TVE_CTRL_DAPD (1 << 20) /* power down all DACs */ |
8835 | #define TVE_CTRL_YCDLY_BIT 16 | 8841 | #define TVE_CTRL_YCDLY_BIT 16 |
8836 | #define TVE_CTRL_YCDLY_MASK (0x7 << TVE_CTRL_YCDLY_BIT) | 8842 | #define TVE_CTRL_YCDLY_MASK (0x7 << TVE_CTRL_YCDLY_BIT) |
@@ -9591,7 +9597,7 @@ do { \ | |||
9591 | #define AOSD_INT_AOSD_END (1 << 0) | 9597 | #define AOSD_INT_AOSD_END (1 << 0) |
9592 | 9598 | ||
9593 | #define __osd_enable_alpha() (REG_AOSD_CTRL |= AOSD_ALPHA_ENABLE) | 9599 | #define __osd_enable_alpha() (REG_AOSD_CTRL |= AOSD_ALPHA_ENABLE) |
9594 | #define __osd_alpha_start() (REG_AOSD_CTRL |= AOSD_CTRL_ALPHA_START) | 9600 | #define __osd_alpha_start() (REG_AOSD_CTRL |= AOSD_CTRL_ALPHA_START) |
9595 | 9601 | ||
9596 | /************************************************************************* | 9602 | /************************************************************************* |
9597 | * COMPRESS | 9603 | * COMPRESS |
@@ -9603,7 +9609,7 @@ do { \ | |||
9603 | #define COMPRESS_CTRL (AOSD_BASE + 0x3C) | 9609 | #define COMPRESS_CTRL (AOSD_BASE + 0x3C) |
9604 | #define COMPRESS_RATIO (AOSD_BASE + 0x40) | 9610 | #define COMPRESS_RATIO (AOSD_BASE + 0x40) |
9605 | #define COMPRESS_SRC_OFFSET (AOSD_BASE + 0x44) | 9611 | #define COMPRESS_SRC_OFFSET (AOSD_BASE + 0x44) |
9606 | 9612 | ||
9607 | #define REG_COMPRESS_SCR_ADDR REG32(COMPRESS_SCR_ADDR) | 9613 | #define REG_COMPRESS_SCR_ADDR REG32(COMPRESS_SCR_ADDR) |
9608 | #define REG_COMPRESS_DES_ADDR REG32(COMPRESS_DES_ADDR) | 9614 | #define REG_COMPRESS_DES_ADDR REG32(COMPRESS_DES_ADDR) |
9609 | #define REG_COMPRESS_DST_OFFSET REG32(COMPRESS_DST_OFFSET) | 9615 | #define REG_COMPRESS_DST_OFFSET REG32(COMPRESS_DST_OFFSET) |
@@ -9627,9 +9633,9 @@ do { \ | |||
9627 | #define COMPRESS_CTRL_ALIGNED_16_WORD (0 << COMPRESS_CTRL_ALIGNED_MODE_BIT) | 9633 | #define COMPRESS_CTRL_ALIGNED_16_WORD (0 << COMPRESS_CTRL_ALIGNED_MODE_BIT) |
9628 | #define COMPRESS_CTRL_ALIGNED_64_WORD (1 << COMPRESS_CTRL_ALIGNED_MODE_BIT) | 9634 | #define COMPRESS_CTRL_ALIGNED_64_WORD (1 << COMPRESS_CTRL_ALIGNED_MODE_BIT) |
9629 | 9635 | ||
9630 | #define __compress_enable() (REG_COMPRESS_CTRL |= COMPRESS_INT_AOSD_END) | 9636 | #define __compress_enable() (REG_COMPRESS_CTRL |= COMPRESS_INT_AOSD_END) |
9631 | #define __compress_start() (REG_COMPRESS_CTRL |= COMPRESS_CTRL_COMP_START) | 9637 | #define __compress_start() (REG_COMPRESS_CTRL |= COMPRESS_CTRL_COMP_START) |
9632 | #define __compress_with_alpha() (REG_COMPRESS_CTRL |= COMPRESS_CTRL_ALPHA_EN) | 9638 | #define __compress_with_alpha() (REG_COMPRESS_CTRL |= COMPRESS_CTRL_ALPHA_EN) |
9633 | 9639 | ||
9634 | /* Rockbox defines */ | 9640 | /* Rockbox defines */ |
9635 | 9641 | ||