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Diffstat (limited to 'firmware/export/jz4740.h')
-rw-r--r--firmware/export/jz4740.h18
1 files changed, 9 insertions, 9 deletions
diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h
index 45767b26cc..55c0ac7b1d 100644
--- a/firmware/export/jz4740.h
+++ b/firmware/export/jz4740.h
@@ -383,7 +383,7 @@
383#define REG_TCU_TCNT4 REG16(TCU_TCNT4) 383#define REG_TCU_TCNT4 REG16(TCU_TCNT4)
384#define REG_TCU_TCSR4 REG16(TCU_TCSR4) 384#define REG_TCU_TCSR4 REG16(TCU_TCSR4)
385 385
386// n = 0,1,2,3,4,5 386// n = 0,1,2,3,4,5,6,7
387#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */ 387#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
388#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */ 388#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
389#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */ 389#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
@@ -2903,11 +2903,11 @@ do { \
2903/* 2903/*
2904 * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 2904 * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3
2905 */ 2905 */
2906#define __gpio_as_msc() \ 2906#define __gpio_as_msc() \
2907do { \ 2907do { \
2908 REG_GPIO_PXFUNS(3) = 0x00003f00; \ 2908 REG_GPIO_PXFUNS(3) = 0x00003f00; \
2909 REG_GPIO_PXSELC(3) = 0x00003f00; \ 2909 REG_GPIO_PXSELC(3) = 0x00003f00; \
2910 REG_GPIO_PXPES(3) = 0x00003f00; \ 2910 REG_GPIO_PXPES(3) = 0x00003f00; \
2911} while (0) 2911} while (0)
2912 2912
2913/* 2913/*
@@ -3027,8 +3027,8 @@ do { \
3027 REG_GPIO_PXDIRS(p) = (1 << (o)); \ 3027 REG_GPIO_PXDIRS(p) = (1 << (o)); \
3028} while (0) 3028} while (0)
3029 3029
3030#define __gpio_port_as_input(p, o) \ 3030#define __gpio_port_as_input(p, o) \
3031do { \ 3031do { \
3032 REG_GPIO_PXFUNC(p) = (1 << (o)); \ 3032 REG_GPIO_PXFUNC(p) = (1 << (o)); \
3033 REG_GPIO_PXSELC(p) = (1 << (o)); \ 3033 REG_GPIO_PXSELC(p) = (1 << (o)); \
3034 REG_GPIO_PXDIRC(p) = (1 << (o)); \ 3034 REG_GPIO_PXDIRC(p) = (1 << (o)); \
@@ -4168,9 +4168,9 @@ do { \
4168#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) 4168#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO )
4169#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) 4169#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v )
4170 4170
4171#define __msc_reset() \ 4171#define __msc_reset() \
4172do { \ 4172do { \
4173 REG_MSC_STRPCL = MSC_STRPCL_RESET; \ 4173 REG_MSC_STRPCL = MSC_STRPCL_RESET; \
4174 while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ 4174 while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
4175} while (0) 4175} while (0)
4176 4176