diff options
Diffstat (limited to 'firmware/export/imx31l.h')
-rwxr-xr-x | firmware/export/imx31l.h | 54 |
1 files changed, 31 insertions, 23 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index 7dc2659b33..3e7abe344b 100755 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
@@ -491,29 +491,37 @@ | |||
491 | #define EPITSR_OCIF (1 << 0) | 491 | #define EPITSR_OCIF (1 << 0) |
492 | 492 | ||
493 | /* GPIO */ | 493 | /* GPIO */ |
494 | #define GPIO1_DR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00)) | 494 | #define GPIO_DR_I 0x00 /* Offset - 0x00 */ |
495 | #define GPIO1_GDIR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04)) | 495 | #define GPIO_GDIR_I 0x01 /* Offset - 0x04 */ |
496 | #define GPIO1_PSR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x08)) | 496 | #define GPIO_PSR_I 0x02 /* Offset - 0x08 */ |
497 | #define GPIO1_ICR1 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x0C)) | 497 | #define GPIO_ICR1_I 0x03 /* Offset - 0x0C */ |
498 | #define GPIO1_ICR2 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x10)) | 498 | #define GPIO_ICR2_I 0x04 /* Offset - 0x10 */ |
499 | #define GPIO1_IMR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x14)) | 499 | #define GPIO_IMR_I 0x05 /* Offset - 0x14 */ |
500 | #define GPIO1_ISR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x18)) | 500 | #define GPIO_ISR_I 0x06 /* Offset - 0x18 */ |
501 | 501 | ||
502 | #define GPIO2_DR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x00)) | 502 | #define GPIO1_DR (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_DR_I]) |
503 | #define GPIO2_GDIR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x04)) | 503 | #define GPIO1_GDIR (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_GDIR_I]) |
504 | #define GPIO2_PSR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x08)) | 504 | #define GPIO1_PSR (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_PSR_I]) |
505 | #define GPIO2_ICR1 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x0C)) | 505 | #define GPIO1_ICR1 (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_ICR1_I]) |
506 | #define GPIO2_ICR2 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x10)) | 506 | #define GPIO1_ICR2 (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_ICR2_I]) |
507 | #define GPIO2_IMR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x14)) | 507 | #define GPIO1_IMR (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_IMR_I]) |
508 | #define GPIO2_ISR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x18)) | 508 | #define GPIO1_ISR (((REG32_PTR_T)GPIO1_BASE_ADDR)[GPIO_ISR_I]) |
509 | 509 | ||
510 | #define GPIO3_DR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x00)) | 510 | #define GPIO2_DR (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_DR_I]) |
511 | #define GPIO3_GDIR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x04)) | 511 | #define GPIO2_GDIR (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_GDIR_I]) |
512 | #define GPIO3_PSR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x08)) | 512 | #define GPIO2_PSR (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_PSR_I]) |
513 | #define GPIO3_ICR1 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x0C)) | 513 | #define GPIO2_ICR1 (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_ICR1_I]) |
514 | #define GPIO3_ICR2 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x10)) | 514 | #define GPIO2_ICR2 (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_ICR2_I]) |
515 | #define GPIO3_IMR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x14)) | 515 | #define GPIO2_IMR (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_IMR_I]) |
516 | #define GPIO3_ISR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18)) | 516 | #define GPIO2_ISR (((REG32_PTR_T)GPIO2_BASE_ADDR)[GPIO_ISR_I]) |
517 | |||
518 | #define GPIO3_DR (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_DR_I]) | ||
519 | #define GPIO3_GDIR (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_GDIR_I]) | ||
520 | #define GPIO3_PSR (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_PSR_I]) | ||
521 | #define GPIO3_ICR1 (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_ICR1_I]) | ||
522 | #define GPIO3_ICR2 (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_ICR2_I]) | ||
523 | #define GPIO3_IMR (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_IMR_I]) | ||
524 | #define GPIO3_ISR (((REG32_PTR_T)GPIO3_BASE_ADDR)[GPIO_ISR_I]) | ||
517 | 525 | ||
518 | /* CSPI */ | 526 | /* CSPI */ |
519 | #define CSPI_RXDATA_I 0x00 /* Offset - 0x00 */ | 527 | #define CSPI_RXDATA_I 0x00 /* Offset - 0x00 */ |