1 files changed, 123 insertions, 31 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h
index 3f3a0140c8..7cb452d3cb 100644
--- a/firmware/export/imx31l.h
+++ b/firmware/export/imx31l.h
@@ -197,36 +197,128 @@
 #define RNGA_CONTROL_SLEEP                          (1 << 4)
 /* IPU */
-#define IPU_CONF                (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00))
+#define IPU_IPU_CONF                (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x000))
-#define IPU_CHA_BUF0_RDY        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04))
+#define IPU_IPU_CHA_BUF0_RDY        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x004))
-#define IPU_CHA_BUF1_RDY        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x08))
+#define IPU_IPU_CHA_BUF1_RDY        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x008))
-#define IPU_CHA_DB_MODE_SEL     (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C))
+#define IPU_IPU_CHA_DB_MODE_SEL     (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00C))
-#define IPU_CHA_CUR_BUF         (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x10))
+#define IPU_IPU_CHA_CUR_BUF         (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x010))
-#define IPU_FS_PROC_FLOW        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x14))
+#define IPU_IPU_FS_PROC_FLOW        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x014))
-#define IPU_FS_DISP_FLOW        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x18))
+#define IPU_IPU_FS_DISP_FLOW        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x018))
-#define IPU_TASKS_STAT          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1C))
+#define IPU_IPU_TASKS_STAT          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x01C))
-#define IPU_IMA_ADDR            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x20))
+#define IPU_IPU_IMA_ADDR            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x020))
-#define IPU_IMA_DATA            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x24))
+#define IPU_IPU_IMA_DATA            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x024))
-#define IPU_INT_CTRL_1          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x28))
+#define IPU_IPU_INT_CTRL_1          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x028))
-#define IPU_INT_CTRL_2          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x2C))
+#define IPU_IPU_INT_CTRL_2          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x02C))
-#define IPU_INT_CTRL_3          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x30))
+#define IPU_IPU_INT_CTRL_3          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x030))
-#define IPU_INT_CTRL_4          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x34))
+#define IPU_IPU_INT_CTRL_4          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x034))
-#define IPU_INT_CTRL_5          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x38))
+#define IPU_IPU_INT_CTRL_5          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x038))
-#define IPU_INT_STAT_1          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x3C))
+#define IPU_IPU_INT_STAT_1          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x03C))
-#define IPU_INT_STAT_2          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x40))
+#define IPU_IPU_INT_STAT_2          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x040))
-#define IPU_INT_STAT_3          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x44))
+#define IPU_IPU_INT_STAT_3          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x044))
-#define IPU_INT_STAT_4          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x48))
+#define IPU_IPU_INT_STAT_4          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x048))
-#define IPU_INT_STAT_5          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x4C))
+#define IPU_IPU_INT_STAT_5          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04C))
-#define IPU_BRK_CTRL_1          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x50))
+#define IPU_IPU_BRK_CTRL_1          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x050))
-#define IPU_BRK_CTRL_2          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54))
+#define IPU_IPU_BRK_CTRL_2          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x054))
-#define IPU_BRK_STAT            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58))
+#define IPU_IPU_BRK_STAT            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x058))
-#define IPU_DIAGB_CTRL          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60))
+#define IPU_IPU_DIAGB_CTRL          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x060))
-#define IPU_IDMAC_CONF          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA4))
+#define IPU_CSI_SENS_FRM_SIZE       (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x064))
-#define IPU_IDMAC_CHA_EN        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA8))
+#define IPU_CSI_ACT_FRM_SIZE        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x068))
-#define IPU_IDMAC_CHA_PRI       (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xAC))
+#define IPU_CSI_OUT_FRM_CTRL        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x06C))
-#define IPU_IDMAC_CHA_BUSY      (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xB0))
+#define IPU_CSI_TST_CTRL            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x070))
+#define IPU_CSI_CCIR_CODE_1         (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x074))
+#define IPU_CSI_CCIR_CODE_2         (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x078))
+#define IPU_CSI_CCIR_CODE_3         (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x07C))
+#define IPU_CSI_FLASH_STROBE_1      (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x080))
+#define IPU_CSI_FLASH_STROBE_2      (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x084))
+#define IPU_IC_CONF                 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x088))
+#define IPU_IC_PRP_ENC_RSC          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x08C))
+#define IPU_IC_PRP_VF_RSC           (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x090))
+#define IPU_IC_PP_RSC               (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x094))
+#define IPU_IC_CMBP_1               (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x098))
+#define IPU_IC_CMBP_2               (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x09C))
+#define IPU_PF_CONF                 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0A0))
+#define IPU_IDMAC_CONF              (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0A4))
+#define IPU_IDMAC_CHA_EN            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0A8))
+#define IPU_IDMAC_CHA_PRI           (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0AC))
+#define IPU_IDMAC_CHA_BUSY          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0B0))
+#define IPU_SDC_COM_CONF            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0B4))
+#define IPU_SDC_GRAPH_WIND_CTRL     (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0B8))
+#define IPU_SDC_FG_POS              (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0BC))
+#define IPU_SDC_BG_POS              (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C0))
+#define IPU_SDC_CUR_POS             (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C4))
+#define IPU_SDC_CUR_BLINK_PWM_CTRL  (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C8))
+#define IPU_SDC_CUR_MAP             (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0CC))
+#define IPU_SDC_HOR_CONF            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0D0))
+#define IPU_SDC_VER_CONF            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0D4))
+#define IPU_SDC_SHARP_CONF_1        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0D8))
+#define IPU_SDC_SHARP_CONF_2        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0DC))
+#define IPU_SDC_ADC_CONF            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0E0))
+#define IPU_ADC_SYSCHA1_SA          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0E4))
+#define IPU_ADC_SYSCHA2_SA          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0E8))
+#define IPU_ADC_PRPCHAN_SA          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0EC))
+#define IPU_ADC_PPCHAN_SA           (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0F0))
+#define IPU_ADC_DISP0_CONF          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0F4))
+#define IPU_ADC_DISP0_RD_AP         (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0F8))
+#define IPU_ADC_DISP0_RDM           (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0FC))
+#define IPU_ADC_DISP0_SS            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x100))
+#define IPU_ADC_DISP1_CONF          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x104))
+#define IPU_ADC_DISP1_RD_AP         (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x108))
+#define IPU_ADC_DISP1_RDM           (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x10C))
+#define IPU_ADC_DISP2_SS            (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x110))
+#define IPU_ADC_DISP2_CONF          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x114))
+#define IPU_ADC_DISP2_RD_AP         (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x118))
+#define IPU_ADC_DISP2_RDM           (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x11C))
+#define IPU_ADC_DISP_VSYNC          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x120))
+#define IPU_ADC_DISP_IF_CONF        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x124))
+#define IPU_ADC_DISP_SIG_POL        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x128))
+#define IPU_DI_SER_DISP1_CONF       (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x12C))
+#define IPU_DI_SER_DISP2_CONF       (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x130))
+#define IPU_DI_HSP_CLK_PER          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x134))
+#define IPU_DI_DISP0_TIME_CONF_1    (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x138))
+#define IPU_DI_DISP0_TIME_CONF_2    (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x13C))
+#define IPU_DI_DISP0_TIME_CONF_3    (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x140))
+#define IPU_DI_DISP1_TIME_CONF_1    (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x144))
+#define IPU_DI_DISP1_TIME_CONF_2    (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x148))
+#define IPU_DI_DISP1_TIME_CONF_3    (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x14C))
+#define IPU_DI_DISP2_TIME_CONF_1    (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x150))
+#define IPU_DI_DISP2_TIME_CONF_2    (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x154))
+#define IPU_DI_DISP2_TIME_CONF_3    (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x158))
+#define IPU_DI_DISP3_TIME_CONF      (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x15C))
+#define IPU_DI_DISP0_DB0_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x160))
+#define IPU_DI_DISP0_DB1_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x164))
+#define IPU_DI_DISP0_DB2_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x168))
+#define IPU_DI_DISP0_CB0_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x16C))
+#define IPU_DI_DISP0_CB1_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x170))
+#define IPU_DI_DISP0_CB2_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x174))
+#define IPU_DI_DISP1_DB0_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x178))
+#define IPU_DI_DISP1_DB1_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x17C))
+#define IPU_DI_DISP1_DB2_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x180))
+#define IPU_DI_DISP1_CB0_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x184))
+#define IPU_DI_DISP1_CB1_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x188))
+#define IPU_DI_DISP1_CB2_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x18C))
+#define IPU_DI_DISP2_DB0_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x190))
+#define IPU_DI_DISP2_DB1_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x194))
+#define IPU_DI_DISP2_DB2_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x198))
+#define IPU_DI_DISP2_CB0_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x19C))
+#define IPU_DI_DISP2_CB1_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1A0))
+#define IPU_DI_DISP2_CB2_MAP        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1A4))
+#define IPU_DI_DISP3_B0_MAP         (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1A8))
+#define IPU_DI_DISP3_B1_MAP         (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1AC))
+#define IPU_DI_DISP3_B2_MAP         (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1B0))
+#define IPU_DI_DISP_ACC_CC          (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1B4))
+#define IPU_DI_DISP_LLA_CONF        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1B8))
+#define IPU_DI_DISP_LLA_DATA        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1BC))
+/* IPU_CONF */
+#define IPU_IPU_CONF_PXL_ENDIAN     (1 << 8)
+#define IPU_IPU_CONF_DU_EN          (1 << 7)
+#define IPU_IPU_CONF_DI_EN          (1 << 6)
+#define IPU_IPU_CONF_ADC_EN         (1 << 5)
+#define IPU_IPU_CONF_SDC_EN         (1 << 4)
+#define IPU_IPU_CONF_PF_EN          (1 << 3)
+#define IPU_IPU_CONF_ROT_EN         (1 << 2)
+#define IPU_IPU_CONF_IC_EN          (1 << 1)
+#define IPU_IPU_CONF_CSI_EN         (1 << 0)
 /* ATA */
 #define ATA_TIME_OFF            (*(REG8_PTR_T)(ATA_BASE_ADDR+0x00))
@@ -493,7 +585,7 @@
 #define CSPI_BITCOUNT(n)                ((n) << 8)
 #define CSPI_CONREG_SSPOL               (1 << 7)
 #define CSPI_CONREG_SSCTL               (1 << 6)
-#define CSPI_CONREG_PHA                 (1 << 6)
+#define CSPI_CONREG_PHA                 (1 << 5)
 #define CSPI_CONREG_POL                 (1 << 4)
 #define CSPI_CONREG_SMC                 (1 << 3)
 #define CSPI_CONREG_XCH                 (1 << 2)

diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index 3f3a0140c8..7cb452d3cb 100644 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h
@@ -197,36 +197,128 @@
197	#define RNGA_CONTROL_SLEEP (1 << 4)	197	#define RNGA_CONTROL_SLEEP (1 << 4)
198		198
199	/* IPU */	199	/* IPU */
200	#define IPU_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00))	200	#define IPU_IPU_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x000))
201	#define IPU_CHA_BUF0_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04))	201	#define IPU_IPU_CHA_BUF0_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x004))
202	#define IPU_CHA_BUF1_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x08))	202	#define IPU_IPU_CHA_BUF1_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x008))
203	#define IPU_CHA_DB_MODE_SEL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C))	203	#define IPU_IPU_CHA_DB_MODE_SEL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00C))
204	#define IPU_CHA_CUR_BUF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x10))	204	#define IPU_IPU_CHA_CUR_BUF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x010))
205	#define IPU_FS_PROC_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x14))	205	#define IPU_IPU_FS_PROC_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x014))
206	#define IPU_FS_DISP_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x18))	206	#define IPU_IPU_FS_DISP_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x018))
207	#define IPU_TASKS_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1C))	207	#define IPU_IPU_TASKS_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x01C))
208	#define IPU_IMA_ADDR (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x20))	208	#define IPU_IPU_IMA_ADDR (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x020))
209	#define IPU_IMA_DATA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x24))	209	#define IPU_IPU_IMA_DATA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x024))
210	#define IPU_INT_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x28))	210	#define IPU_IPU_INT_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x028))
211	#define IPU_INT_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x2C))	211	#define IPU_IPU_INT_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x02C))
212	#define IPU_INT_CTRL_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x30))	212	#define IPU_IPU_INT_CTRL_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x030))
213	#define IPU_INT_CTRL_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x34))	213	#define IPU_IPU_INT_CTRL_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x034))
214	#define IPU_INT_CTRL_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x38))	214	#define IPU_IPU_INT_CTRL_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x038))
215	#define IPU_INT_STAT_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x3C))	215	#define IPU_IPU_INT_STAT_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x03C))
216	#define IPU_INT_STAT_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x40))	216	#define IPU_IPU_INT_STAT_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x040))
217	#define IPU_INT_STAT_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x44))	217	#define IPU_IPU_INT_STAT_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x044))
218	#define IPU_INT_STAT_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x48))	218	#define IPU_IPU_INT_STAT_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x048))
219	#define IPU_INT_STAT_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x4C))	219	#define IPU_IPU_INT_STAT_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04C))
220	#define IPU_BRK_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x50))	220	#define IPU_IPU_BRK_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x050))
221	#define IPU_BRK_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54))	221	#define IPU_IPU_BRK_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x054))
222	#define IPU_BRK_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58))	222	#define IPU_IPU_BRK_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x058))
223	#define IPU_DIAGB_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60))	223	#define IPU_IPU_DIAGB_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x060))
224	#define IPU_IDMAC_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA4))	224	#define IPU_CSI_SENS_FRM_SIZE (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x064))
225	#define IPU_IDMAC_CHA_EN (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xA8))	225	#define IPU_CSI_ACT_FRM_SIZE (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x068))
226	#define IPU_IDMAC_CHA_PRI (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xAC))	226	#define IPU_CSI_OUT_FRM_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x06C))
227	#define IPU_IDMAC_CHA_BUSY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0xB0))	227	#define IPU_CSI_TST_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x070))
228		228	#define IPU_CSI_CCIR_CODE_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x074))
229		229	#define IPU_CSI_CCIR_CODE_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x078))
		230	#define IPU_CSI_CCIR_CODE_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x07C))
		231	#define IPU_CSI_FLASH_STROBE_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x080))
		232	#define IPU_CSI_FLASH_STROBE_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x084))
		233	#define IPU_IC_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x088))
		234	#define IPU_IC_PRP_ENC_RSC (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x08C))
		235	#define IPU_IC_PRP_VF_RSC (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x090))
		236	#define IPU_IC_PP_RSC (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x094))
		237	#define IPU_IC_CMBP_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x098))
		238	#define IPU_IC_CMBP_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x09C))
		239	#define IPU_PF_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0A0))
		240	#define IPU_IDMAC_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0A4))
		241	#define IPU_IDMAC_CHA_EN (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0A8))
		242	#define IPU_IDMAC_CHA_PRI (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0AC))
		243	#define IPU_IDMAC_CHA_BUSY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0B0))
		244	#define IPU_SDC_COM_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0B4))
		245	#define IPU_SDC_GRAPH_WIND_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0B8))
		246	#define IPU_SDC_FG_POS (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0BC))
		247	#define IPU_SDC_BG_POS (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C0))
		248	#define IPU_SDC_CUR_POS (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C4))
		249	#define IPU_SDC_CUR_BLINK_PWM_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C8))
		250	#define IPU_SDC_CUR_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0CC))
		251	#define IPU_SDC_HOR_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0D0))
		252	#define IPU_SDC_VER_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0D4))
		253	#define IPU_SDC_SHARP_CONF_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0D8))
		254	#define IPU_SDC_SHARP_CONF_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0DC))
		255	#define IPU_SDC_ADC_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0E0))
		256	#define IPU_ADC_SYSCHA1_SA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0E4))
		257	#define IPU_ADC_SYSCHA2_SA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0E8))
		258	#define IPU_ADC_PRPCHAN_SA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0EC))
		259	#define IPU_ADC_PPCHAN_SA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0F0))
		260	#define IPU_ADC_DISP0_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0F4))
		261	#define IPU_ADC_DISP0_RD_AP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0F8))
		262	#define IPU_ADC_DISP0_RDM (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0FC))
		263	#define IPU_ADC_DISP0_SS (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x100))
		264	#define IPU_ADC_DISP1_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x104))
		265	#define IPU_ADC_DISP1_RD_AP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x108))
		266	#define IPU_ADC_DISP1_RDM (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x10C))
		267	#define IPU_ADC_DISP2_SS (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x110))
		268	#define IPU_ADC_DISP2_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x114))
		269	#define IPU_ADC_DISP2_RD_AP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x118))
		270	#define IPU_ADC_DISP2_RDM (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x11C))
		271	#define IPU_ADC_DISP_VSYNC (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x120))
		272	#define IPU_ADC_DISP_IF_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x124))
		273	#define IPU_ADC_DISP_SIG_POL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x128))
		274	#define IPU_DI_SER_DISP1_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x12C))
		275	#define IPU_DI_SER_DISP2_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x130))
		276	#define IPU_DI_HSP_CLK_PER (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x134))
		277	#define IPU_DI_DISP0_TIME_CONF_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x138))
		278	#define IPU_DI_DISP0_TIME_CONF_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x13C))
		279	#define IPU_DI_DISP0_TIME_CONF_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x140))
		280	#define IPU_DI_DISP1_TIME_CONF_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x144))
		281	#define IPU_DI_DISP1_TIME_CONF_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x148))
		282	#define IPU_DI_DISP1_TIME_CONF_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x14C))
		283	#define IPU_DI_DISP2_TIME_CONF_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x150))
		284	#define IPU_DI_DISP2_TIME_CONF_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x154))
		285	#define IPU_DI_DISP2_TIME_CONF_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x158))
		286	#define IPU_DI_DISP3_TIME_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x15C))
		287	#define IPU_DI_DISP0_DB0_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x160))
		288	#define IPU_DI_DISP0_DB1_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x164))
		289	#define IPU_DI_DISP0_DB2_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x168))
		290	#define IPU_DI_DISP0_CB0_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x16C))
		291	#define IPU_DI_DISP0_CB1_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x170))
		292	#define IPU_DI_DISP0_CB2_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x174))
		293	#define IPU_DI_DISP1_DB0_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x178))
		294	#define IPU_DI_DISP1_DB1_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x17C))
		295	#define IPU_DI_DISP1_DB2_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x180))
		296	#define IPU_DI_DISP1_CB0_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x184))
		297	#define IPU_DI_DISP1_CB1_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x188))
		298	#define IPU_DI_DISP1_CB2_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x18C))
		299	#define IPU_DI_DISP2_DB0_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x190))
		300	#define IPU_DI_DISP2_DB1_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x194))
		301	#define IPU_DI_DISP2_DB2_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x198))
		302	#define IPU_DI_DISP2_CB0_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x19C))
		303	#define IPU_DI_DISP2_CB1_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1A0))
		304	#define IPU_DI_DISP2_CB2_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1A4))
		305	#define IPU_DI_DISP3_B0_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1A8))
		306	#define IPU_DI_DISP3_B1_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1AC))
		307	#define IPU_DI_DISP3_B2_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1B0))
		308	#define IPU_DI_DISP_ACC_CC (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1B4))
		309	#define IPU_DI_DISP_LLA_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1B8))
		310	#define IPU_DI_DISP_LLA_DATA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1BC))
		311
		312	/* IPU_CONF */
		313	#define IPU_IPU_CONF_PXL_ENDIAN (1 << 8)
		314	#define IPU_IPU_CONF_DU_EN (1 << 7)
		315	#define IPU_IPU_CONF_DI_EN (1 << 6)
		316	#define IPU_IPU_CONF_ADC_EN (1 << 5)
		317	#define IPU_IPU_CONF_SDC_EN (1 << 4)
		318	#define IPU_IPU_CONF_PF_EN (1 << 3)
		319	#define IPU_IPU_CONF_ROT_EN (1 << 2)
		320	#define IPU_IPU_CONF_IC_EN (1 << 1)
		321	#define IPU_IPU_CONF_CSI_EN (1 << 0)
230		322
231	/* ATA */	323	/* ATA */
232	#define ATA_TIME_OFF (*(REG8_PTR_T)(ATA_BASE_ADDR+0x00))	324	#define ATA_TIME_OFF (*(REG8_PTR_T)(ATA_BASE_ADDR+0x00))
@@ -493,7 +585,7 @@
493	#define CSPI_BITCOUNT(n) ((n) << 8)	585	#define CSPI_BITCOUNT(n) ((n) << 8)
494	#define CSPI_CONREG_SSPOL (1 << 7)	586	#define CSPI_CONREG_SSPOL (1 << 7)
495	#define CSPI_CONREG_SSCTL (1 << 6)	587	#define CSPI_CONREG_SSCTL (1 << 6)
496	#define CSPI_CONREG_PHA (1 << 6)	588	#define CSPI_CONREG_PHA (1 << 5)
497	#define CSPI_CONREG_POL (1 << 4)	589	#define CSPI_CONREG_POL (1 << 4)
498	#define CSPI_CONREG_SMC (1 << 3)	590	#define CSPI_CONREG_SMC (1 << 3)
499	#define CSPI_CONREG_XCH (1 << 2)	591	#define CSPI_CONREG_XCH (1 << 2)