diff options
Diffstat (limited to 'firmware/export/imx31l.h')
-rwxr-xr-x | firmware/export/imx31l.h | 100 |
1 files changed, 55 insertions, 45 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index 6780a5a43f..5a964b8e2e 100755 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
@@ -202,26 +202,33 @@ | |||
202 | #define SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3 IOMUXC_(0x14C) | 202 | #define SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3 IOMUXC_(0x14C) |
203 | #define SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO IOMUXC_(0x150) | 203 | #define SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO IOMUXC_(0x150) |
204 | 204 | ||
205 | #define SW_MUX_OUT_EN_GPIO_DR 0x0 | 205 | #define SW_MUX_OUT (0x7 << 4) |
206 | #define SW_MUX_OUT_FUNCTIONAL 0x1 | 206 | #define SW_MUX_OUT_GPIO_DR (0x0 << 4) |
207 | #define SW_MUX_OUT_ALTERNATE_1 0x2 | 207 | #define SW_MUX_OUT_FUNCTIONAL (0x1 << 4) |
208 | #define SW_MUX_OUT_ALTERNATE_2 0x3 | 208 | #define SW_MUX_OUT_ALT1 (0x2 << 4) |
209 | #define SW_MUX_OUT_ALTERNATE_3 0x4 | 209 | #define SW_MUX_OUT_ALT2 (0x3 << 4) |
210 | #define SW_MUX_OUT_ALTERNATE_4 0x5 | 210 | #define SW_MUX_OUT_ALT3 (0x4 << 4) |
211 | #define SW_MUX_OUT_ALTERNATE_5 0x6 | 211 | #define SW_MUX_OUT_ALT4 (0x5 << 4) |
212 | #define SW_MUX_OUT_ALTERNATE_6 0x7 | 212 | #define SW_MUX_OUT_ALT5 (0x6 << 4) |
213 | 213 | #define SW_MUX_OUT_ALT6 (0x7 << 4) | |
214 | #define SW_MUX_IN_NO_INPUTS 0x0 | 214 | |
215 | #define SW_MUX_IN_GPIO_PSR_ISR 0x1 | 215 | #define SW_MUX_IN (0xf << 0) |
216 | #define SW_MUX_IN_FUNCTIONAL 0x2 | 216 | #define SW_MUX_IN_NO_INPUTS (0x0 << 0) |
217 | #define SW_MUX_IN_ALTERNATE_1 0x3 | 217 | #define SW_MUX_IN_GPIO_PSR_ISR (0x1 << 0) |
218 | #define SW_MUX_IN_ALTERNATE_2 0x4 | 218 | #define SW_MUX_IN_FUNCTIONAL (0x2 << 0) |
219 | 219 | #define SW_MUX_IN_ALT1 (0x4 << 0) | |
220 | #define SW_MUX_IN_ALT2 (0x8 << 0) | ||
221 | |||
222 | /* Masks for each signal field */ | ||
223 | #define SW_MUX_CTL_SIG1 (0x7f << 0) | ||
224 | #define SW_MUX_CTL_SIG2 (0x7f << 8) | ||
225 | #define SW_MUX_CTL_SIG3 (0x7f << 16) | ||
226 | #define SW_MUX_CTL_SIG4 (0x7f << 24) | ||
220 | /* Shift above flags into one of the four fields in each register */ | 227 | /* Shift above flags into one of the four fields in each register */ |
221 | #define SW_MUX_CTL_FLD_0(x) ((x) << 0) | 228 | #define SW_MUX_CTL_SIG1w(x) (((x) << 0) & SW_MUX_CTL_SIG1) |
222 | #define SW_MUX_CTL_FLD_1(x) ((x) << 8) | 229 | #define SW_MUX_CTL_SIG2w(x) (((x) << 8) & SW_MUX_CTL_SIG2) |
223 | #define SW_MUX_CTL_FLD_2(x) ((x) << 16) | 230 | #define SW_MUX_CTL_SIG3w(x) (((x) << 16) & SW_MUX_CTL_SIG3) |
224 | #define SW_MUX_CTL_FLD_3(x) ((x) << 24) | 231 | #define SW_MUX_CTL_SIG4w(x) (((x) << 24) & SW_MUX_CTL_SIG4) |
225 | 232 | ||
226 | /* SW_PAD_CTL */ | 233 | /* SW_PAD_CTL */ |
227 | #define SW_PAD_CTL_TTM_PAD__X__X IOMUXC_(0x154) | 234 | #define SW_PAD_CTL_TTM_PAD__X__X IOMUXC_(0x154) |
@@ -336,36 +343,39 @@ | |||
336 | #define SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST IOMUXC_(0x308) | 343 | #define SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST IOMUXC_(0x308) |
337 | 344 | ||
338 | /* SW_PAD_CTL flags */ | 345 | /* SW_PAD_CTL flags */ |
339 | #define SW_PAD_CTL_LOOPBACK (1 << 9) | 346 | #define SW_PAD_CTL_LOOPBACK (0x1 << 9) /* Route output to input */ |
340 | #define SW_PAD_CTL_DISABLE_PULL_UP_DOWN_AND_KEEPER (0 << 7) | 347 | /* Pullup, pulldown and keeper enable */ |
341 | #if 0 /* Same as 0 */ | 348 | #define SW_PAD_CTL_PUE_PKE (0x3 << 7) |
342 | #define SW_PAD_CTL_DISABLE_PULL_UP_DOWN_AND_KEEPER (1 << 7) | 349 | #define SW_PAD_CTL_PUE_PKE_DISABLE (0x0 << 7) |
343 | #endif | 350 | #define SW_PAD_CTL_PUE_PKE_DISABLE_2 (0x1 << 7) /* Same as 0x0 */ |
344 | #define SW_PAD_CTL_ENABLE_KEEPER (2 << 7) | 351 | #define SW_PAD_CTL_PUE_PKE_KEEPER (0x2 << 7) |
345 | #define SW_PAD_CTL_ENABLE_PULL_UP_OR_PULL_DOWN (3 << 7) | 352 | #define SW_PAD_CTL_PUE_PKE_PULLUPDOWN (0x3 << 7) /* Enb. Pull up or down */ |
346 | #define SW_PAD_CTL_100K_PULL_DOWN (0 << 5) | 353 | /* Pullup/down resistance */ |
347 | #define SW_PAD_CTL_100K_PULL_UP (1 << 5) | 354 | #define SW_PAD_CTL_PUS (0x3 << 5) |
355 | #define SW_PAD_CTL_PUS_DOWN_100K (0x0 << 5) | ||
356 | #define SW_PAD_CTL_PUS_UP_100K (0x1 << 5) | ||
348 | #if 0 /* Completeness */ | 357 | #if 0 /* Completeness */ |
349 | #define SW_PAD_CTL_47K_PULL_UP (2 << 5) /* Not in IMX31/L */ | 358 | #define SW_PAD_CTL_PUS_UP_47K (0x2 << 5) /* Not in IMX31/L */ |
350 | #define SW_PAD_CTL_22K_PULL_UP (3 << 5) /* Not in IMX31/L */ | 359 | #define SW_PAD_CTL_PUS_UP_22K (0x3 << 5) /* Not in IMX31/L */ |
351 | #endif | ||
352 | #define SW_PAD_CTL_IPP_HYS_STD (0 << 4) | ||
353 | #define SW_PAD_CTL_IPP_HYS_SCHIMDT (1 << 4) | ||
354 | #define SW_PAD_CTL_IPP_ODE_CMOS (0 << 3) | ||
355 | #define SW_PAD_CTL_IPP_ODE_OPEN (1 << 3) | ||
356 | #define SW_PAD_CTL_IPP_DSE_STD (0 << 1) | ||
357 | #define SW_PAD_CTL_IPP_DSE_HIGH (1 << 1) | ||
358 | #define SW_PAD_CTL_IPP_DSE_MAX (2 << 1) | ||
359 | #if 0 /* Same as 2 */ | ||
360 | #define SW_PAD_CTL_IPP_DSE_MAX (3 << 1) | ||
361 | #endif | 360 | #endif |
362 | #define SW_PAD_CTL_IPP_SRE_SLOW (0 << 0) | 361 | #define SW_PAD_CTL_HYS (0x1 << 4) /* Schmitt trigger input */ |
363 | #define SW_PAD_CTL_IPP_SRE_FAST (1 << 0) | 362 | #define SW_PAD_CTL_ODE (0x1 << 3) /* Open drain output 0=CMOS pushpull*/ |
363 | #define SW_PAD_CTL_DSE (0x3 << 1) | ||
364 | #define SW_PAD_CTL_DSE_STD (0x0 << 1) /* Drive strength */ | ||
365 | #define SW_PAD_CTL_DSE_HIGH (0x1 << 1) | ||
366 | #define SW_PAD_CTL_DSE_MAX (0x2 << 1) | ||
367 | #define SW_PAD_CTL_DSE_MAX_2 (0x3 << 1) /* Same as 0x2 */ | ||
368 | #define SW_PAD_CTL_SRE (0x1 << 0) /* Slew rate, 1=fast */ | ||
369 | |||
370 | /* Masks for each IO field */ | ||
371 | #define SW_PAD_CTL_IO1 (0x3ff << 0) | ||
372 | #define SW_PAD_CTL_IO2 (0x3ff << 10) | ||
373 | #define SW_PAD_CTL_IO3 (0x3ff << 20) | ||
364 | 374 | ||
365 | /* Shift above flags into one of the three fields in each register */ | 375 | /* Shift above flags into one of the three fields in each register */ |
366 | #define SW_PAD_CTL_FLD_0(x) ((x) << 0) | 376 | #define SW_PAD_CTL_IO1w(x) (((x) << 0) & SW_PAD_CTL_IO1) |
367 | #define SW_PAD_CTL_FLD_1(x) ((x) << 10) | 377 | #define SW_PAD_CTL_IO2w(x) (((x) << 10) & SW_PAD_CTL_IO2) |
368 | #define SW_PAD_CTL_FLD_2(x) ((x) << 20) | 378 | #define SW_PAD_CTL_IO3w(x) (((x) << 20) & SW_PAD_CTL_IO3) |
369 | 379 | ||
370 | /* RNGA */ | 380 | /* RNGA */ |
371 | #define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00)) | 381 | #define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00)) |