diff options
Diffstat (limited to 'firmware/export/imx233.h')
-rw-r--r-- | firmware/export/imx233.h | 145 |
1 files changed, 127 insertions, 18 deletions
diff --git a/firmware/export/imx233.h b/firmware/export/imx233.h index a18b584d8e..251f4c6b55 100644 --- a/firmware/export/imx233.h +++ b/firmware/export/imx233.h | |||
@@ -21,8 +21,16 @@ | |||
21 | #ifndef __IMX233_H__ | 21 | #ifndef __IMX233_H__ |
22 | #define __IMX233_H__ | 22 | #define __IMX233_H__ |
23 | 23 | ||
24 | #ifndef IMX233_SUBTARGET | ||
25 | #error You must define IMX233_SUBTARGET to select the chip family | ||
26 | #endif | ||
27 | |||
28 | #ifndef IMX233_PACKAGE | ||
29 | #error You must IMX233_PACKAGE to select the chip package | ||
30 | #endif | ||
31 | |||
24 | /* | 32 | /* |
25 | * Chip Memory Map: | 33 | * Chip Memory Map (stmp3700,imx233): |
26 | * 0x00000000 - 0x00007fff: on chip ram | 34 | * 0x00000000 - 0x00007fff: on chip ram |
27 | * 0x40000000 - 0x5fffffff: dram (512Mb max) | 35 | * 0x40000000 - 0x5fffffff: dram (512Mb max) |
28 | * 0x80000000 - 0x80100000: memory mapped registers | 36 | * 0x80000000 - 0x80100000: memory mapped registers |
@@ -31,25 +39,55 @@ | |||
31 | * 0x90000000 - 0xafffffff: dram (buffered) | 39 | * 0x90000000 - 0xafffffff: dram (buffered) |
32 | * everything else : identity mapped (uncached) | 40 | * everything else : identity mapped (uncached) |
33 | * | 41 | * |
42 | * Chip Memory Map (stmp3600): | ||
43 | * 0x00000000 - 0x00007fff: on chip ram | ||
44 | * 0x60000000 - 0x7fffffff: dram (512Mb max) | ||
45 | * 0x80000000 - 0x80100000: memory mapped registers | ||
46 | * We use the following map: | ||
47 | * 0x40000000 - 0x5fffffff: dram (cached) | ||
48 | * 0x90000000 - 0xafffffff: dram (buffered) | ||
49 | * everything else : identity mapped (uncached) | ||
50 | * | ||
34 | * As a side note it's important to notice that uncached dram is identity mapped | 51 | * As a side note it's important to notice that uncached dram is identity mapped |
35 | */ | 52 | */ |
36 | 53 | ||
37 | #define IRAM_ORIG 0 | 54 | #define IRAM_ORIG 0 |
38 | #define IRAM_SIZE 0x8000 | 55 | #if IMX233_SUBTARGET >= 3780 |
56 | #define IRAM_SIZE (32 * 1024) | ||
57 | #elif IMX233_SUBTARGET >= 3770 | ||
58 | #define IRAM_SIZE (512 * 1024) | ||
59 | #else | ||
60 | #define IRAM_SIZE (256 * 1024) | ||
61 | #endif | ||
62 | |||
63 | #if IMX233_SUBTARGET >= 3700 | ||
39 | #define DRAM_ORIG 0x40000000 | 64 | #define DRAM_ORIG 0x40000000 |
65 | #else | ||
66 | #define DRAM_ORIG 0x60000000 | ||
67 | #endif | ||
40 | #define DRAM_SIZE (MEMORYSIZE * 0x100000) | 68 | #define DRAM_SIZE (MEMORYSIZE * 0x100000) |
41 | 69 | ||
70 | #if IMX233_SUBTARGET >= 3700 | ||
42 | #define UNCACHED_DRAM_ADDR 0x40000000 | 71 | #define UNCACHED_DRAM_ADDR 0x40000000 |
43 | #define CACHED_DRAM_ADDR 0x60000000 | 72 | #define CACHED_DRAM_ADDR 0x60000000 |
44 | #define BUFFERED_DRAM_ADDR 0x90000000 | 73 | #define BUFFERED_DRAM_ADDR 0x90000000 |
74 | #else | ||
75 | #define UNCACHED_DRAM_ADDR 0x60000000 | ||
76 | #define CACHED_DRAM_ADDR 0x40000000 | ||
77 | #define BUFFERED_DRAM_ADDR 0x90000000 | ||
78 | #endif | ||
79 | |||
80 | /* 32 bytes per cache line */ | ||
45 | #define CACHEALIGN_SIZE 32 | 81 | #define CACHEALIGN_SIZE 32 |
82 | #define CACHEALIGN_BITS 5 | ||
46 | 83 | ||
47 | #define NOCACHE_BASE (UNCACHED_DRAM_ADDR - CACHED_DRAM_ADDR) | 84 | #define NOCACHE_BASE (UNCACHED_DRAM_ADDR - CACHED_DRAM_ADDR) |
48 | 85 | ||
86 | #define __IN_RANGE(type, a) (type##_DRAM_ADDR <= (a) && (a) < (type##_DRAM_ADDR + DRAM_SIZE)) | ||
49 | #define PHYSICAL_ADDR(a) \ | 87 | #define PHYSICAL_ADDR(a) \ |
50 | ((typeof(a))((uintptr_t)(a) >= BUFFERED_DRAM_ADDR ? \ | 88 | ((typeof(a))(__IN_RANGE(BUFFERED, (uintptr_t)(a)) ? \ |
51 | ((uintptr_t)(a) - BUFFERED_DRAM_ADDR + UNCACHED_DRAM_ADDR) \ | 89 | ((uintptr_t)(a) - BUFFERED_DRAM_ADDR + UNCACHED_DRAM_ADDR) \ |
52 | :(uintptr_t)(a) >= CACHED_DRAM_ADDR ? \ | 90 | :__IN_RANGE(CACHED, (uintptr_t)(a)) ? \ |
53 | ((uintptr_t)(a) - CACHED_DRAM_ADDR + UNCACHED_DRAM_ADDR) \ | 91 | ((uintptr_t)(a) - CACHED_DRAM_ADDR + UNCACHED_DRAM_ADDR) \ |
54 | :(uintptr_t)(a))) | 92 | :(uintptr_t)(a))) |
55 | #define UNCACHED_ADDR(a) PHYSICAL_ADDR(a) | 93 | #define UNCACHED_ADDR(a) PHYSICAL_ADDR(a) |
@@ -57,7 +95,11 @@ | |||
57 | #define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE) | 95 | #define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE) |
58 | #define TTB_SIZE 0x4000 | 96 | #define TTB_SIZE 0x4000 |
59 | #define TTB_BASE ((unsigned long *)TTB_BASE_ADDR) | 97 | #define TTB_BASE ((unsigned long *)TTB_BASE_ADDR) |
60 | #define FRAME_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_DEPTH / 8) | 98 | /* align to cache line */ |
99 | #ifndef IMX233_FRAMEBUFFER_SIZE | ||
100 | #define IMX233_FRAMEBUFFER_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_DEPTH / 8) | ||
101 | #endif | ||
102 | #define FRAME_SIZE ((IMX233_FRAMEBUFFER_SIZE + CACHEALIGN_SIZE - 1) & ~(CACHEALIGN_SIZE - 1)) | ||
61 | #define FRAME_PHYS_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE - FRAME_SIZE) | 103 | #define FRAME_PHYS_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE - FRAME_SIZE) |
62 | #define FRAME ((void *)(FRAME_PHYS_ADDR - UNCACHED_DRAM_ADDR + BUFFERED_DRAM_ADDR)) | 104 | #define FRAME ((void *)(FRAME_PHYS_ADDR - UNCACHED_DRAM_ADDR + BUFFERED_DRAM_ADDR)) |
63 | 105 | ||
@@ -67,12 +109,19 @@ | |||
67 | /* USBOTG */ | 109 | /* USBOTG */ |
68 | #define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048))) | 110 | #define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048))) |
69 | #define USB_NUM_ENDPOINTS 5 | 111 | #define USB_NUM_ENDPOINTS 5 |
112 | /* STMP3600 doesn't have the bandwidth to put buffer in SDRAM */ | ||
113 | #if IMX233_SUBTARGET < 3700 | ||
114 | #define USB_DEVBSS_ATTR IBSS_ATTR | ||
115 | #else | ||
70 | #define USB_DEVBSS_ATTR NOCACHEBSS_ATTR | 116 | #define USB_DEVBSS_ATTR NOCACHEBSS_ATTR |
117 | #endif | ||
71 | #define USB_BASE 0x80080000 | 118 | #define USB_BASE 0x80080000 |
72 | /* | 119 | |
73 | #define QHARRAY_SIZE ((64*USB_NUM_ENDPOINTS*2 + 2047) & (0xffffffff - 2047)) | 120 | #define ___ENSURE_ZERO(line, x) static uint8_t __ensure_zero_##line[-(x)] __attribute__((unused)); |
74 | #define QHARRAY_PHYS_ADDR ((FRAME_PHYS_ADDR - QHARRAY_SIZE) & (0xffffffff - 2047)) | 121 | #define __ENSURE_ZERO(x) ___ENSURE_ZERO(__LINE__, x) |
75 | */ | 122 | #define __ENSURE_MULTIPLE(x, y) __ENSURE_ZERO((x) % (y)) |
123 | #define __ENSURE_CACHELINE_MULTIPLE(x) __ENSURE_MULTIPLE(x, 1 << CACHEALIGN_BITS) | ||
124 | #define __ENSURE_STRUCT_CACHE_FRIENDLY(name) __ENSURE_CACHELINE_MULTIPLE(sizeof(name)) | ||
76 | 125 | ||
77 | #define __REG_SET(reg) (*((volatile uint32_t *)(® + 1))) | 126 | #define __REG_SET(reg) (*((volatile uint32_t *)(® + 1))) |
78 | #define __REG_CLR(reg) (*((volatile uint32_t *)(® + 2))) | 127 | #define __REG_CLR(reg) (*((volatile uint32_t *)(® + 2))) |
@@ -83,18 +132,78 @@ | |||
83 | #define __BLOCK_SFTRST (1 << 31) | 132 | #define __BLOCK_SFTRST (1 << 31) |
84 | #define __BLOCK_CLKGATE (1 << 30) | 133 | #define __BLOCK_CLKGATE (1 << 30) |
85 | 134 | ||
86 | /* 32 bytes per cache line */ | ||
87 | #define CACHEALIGN_BITS 5 | ||
88 | |||
89 | #define ___ENSURE_ZERO(line, x) static uint8_t __ensure_zero_##line[-(x)] __attribute__((unused)); | ||
90 | #define __ENSURE_ZERO(x) ___ENSURE_ZERO(__LINE__, x) | ||
91 | #define __ENSURE_MULTIPLE(x, y) __ENSURE_ZERO((x) % (y)) | ||
92 | #define __ENSURE_CACHELINE_MULTIPLE(x) __ENSURE_MULTIPLE(x, 1 << CACHEALIGN_BITS) | ||
93 | #define __ENSURE_STRUCT_CACHE_FRIENDLY(name) __ENSURE_CACHELINE_MULTIPLE(sizeof(name)) | ||
94 | |||
95 | #define __XTRACT(reg, field) ((reg & reg##__##field##_BM) >> reg##__##field##_BP) | 135 | #define __XTRACT(reg, field) ((reg & reg##__##field##_BM) >> reg##__##field##_BP) |
96 | #define __XTRACT_EX(val, field) (((val) & field##_BM) >> field##_BP) | 136 | #define __XTRACT_EX(val, field) (((val) & field##_BM) >> field##_BP) |
97 | #define __FIELD_SET(reg, field, val) reg = (reg & ~reg##__##field##_BM) | (val << reg##__##field##_BP) | 137 | #define __FIELD_SET(reg, field, val) reg = (reg & ~reg##__##field##_BM) | (val << reg##__##field##_BP) |
98 | #define __FIELD_SET_CLR(reg, field, set) __REG_SET_CLR(reg, set) = reg##__##field | 138 | #define __FIELD_SET_CLR(reg, field, set) __REG_SET_CLR(reg, set) = reg##__##field |
99 | 139 | ||
140 | /** | ||
141 | * Register Naming Scheme | ||
142 | * | ||
143 | * => Devices | ||
144 | * | ||
145 | * Each device <dev> has its base address defined as REGS_<dev>_base: | ||
146 | * | ||
147 | * Example: | ||
148 | * #define REGS_APBHBASE (0x80004000) | ||
149 | * #define REGS_SSPBASE(i) ((i) == 1 ? 0x80010000 : 0x80034000) | ||
150 | * | ||
151 | * => Registers | ||
152 | * | ||
153 | * Each register <reg> in device <dev> has its address(es) defined as | ||
154 | * HW_<dev>_<reg>[_{SET,CLR,TOG}] | ||
155 | * | ||
156 | * Examples: | ||
157 | * #define HW_APBH_CTRL1 (*(volatile unsigned long *)(REGS_APBHBASE + 0x10 + 0)) | ||
158 | * #define HW_APBH_CHn_CURCMDAR(n) (*(volatile unsigned long *)(REGS_APBHBASE + 0x40+(n)*0x70)) | ||
159 | * #define HW_SSP_CTRL0_SET(d) (*(volatile unsigned long *)(REGS_SSPBASE(d) + 0 + 0x4)) | ||
160 | * | ||
161 | * => Fields | ||
162 | * | ||
163 | * Each field <field> in register <reg> in device <dev> has its bit position | ||
164 | * and bitmask defined as {BP,BM}_<dev>_<reg>_<field> | ||
165 | * | ||
166 | * Examples: | ||
167 | * | ||
168 | * | ||
169 | * | ||
170 | */ | ||
171 | |||
172 | /** | ||
173 | * Register macros: | ||
174 | * | ||
175 | * BF_SET(reg, field): equivalent to HW_reg_SET = BM_reg_field; | ||
176 | * BF_CLR(reg, field): same with CLR | ||
177 | * BF_TOG(reg, field): same with TOG | ||
178 | * | ||
179 | * BF_SETV(reg, field, v): equivalent to HW_reg_SET = BF_reg_field(v) | ||
180 | * BF_CLRV(reg, field, v): same with CLR | ||
181 | * BF_TOGV(reg, fielf, v): same with TOG | ||
182 | * | ||
183 | * BF_RD(reg, field): equivalent to (HW_reg & BM_reg_field) >> BP_reg_field | ||
184 | * BF_WR(reg, field, v): equivalent to HW_reg = (HW_reg & ~BM_reg_field) | (((v << BP_reg_field) & BM_reg_field) | ||
185 | * BF_WR_V(reg, field, sym): BF_WR(reg, field, BV_reg_field__sym) | ||
186 | * | ||
187 | * BF_{SET,CLR,TOG}[V]n(reg, n, field): same for multi registers | ||
188 | * | ||
189 | * The BF_RDX(val, reg, field) reads from the value provided instead of the register | ||
190 | * Similarly for BF_WRX | ||
191 | * | ||
192 | */ | ||
193 | |||
194 | /** | ||
195 | * Handy macros for mutliple operations at once | ||
196 | * | ||
197 | * BF_ORp(reg, f1,, ..., fp) is equivalent to | ||
198 | * BF_reg_f1 | ... | BF_reg_fp | ||
199 | * | ||
200 | * BM_ORp is similar with BM_ | ||
201 | * | ||
202 | * There exist some variadic variants which do not need to write the number | ||
203 | * of parameters, if supported by the compiler: | ||
204 | * | ||
205 | * BF_OR(reg, f1, ..., fn) | ||
206 | * BM_OR(reg, f1, ..., fn) | ||
207 | */ | ||
208 | |||
100 | #endif /* __IMX233_H__ */ | 209 | #endif /* __IMX233_H__ */ |