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Diffstat (limited to 'firmware/export/at91sam9260.h')
-rw-r--r-- | firmware/export/at91sam9260.h | 678 |
1 files changed, 678 insertions, 0 deletions
diff --git a/firmware/export/at91sam9260.h b/firmware/export/at91sam9260.h new file mode 100644 index 0000000000..fa0b9d2d4f --- /dev/null +++ b/firmware/export/at91sam9260.h | |||
@@ -0,0 +1,678 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * | ||
9 | * | ||
10 | * Copyright (C) 2009 by Jorge Pinto | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | /* MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register */ | ||
23 | #define AT91C_MATRIX_RCA926I (0x1 << 0) /* (MATRIX) Remap Command for | ||
24 | ARM926EJ-S Instruction Master */ | ||
25 | #define AT91C_MATRIX_RCA926D (0x1 << 1) /* (MATRIX) Remap Command for | ||
26 | ARM926EJ-S Data Master */ | ||
27 | |||
28 | /* Register definition for MATRIX peripheral */ | ||
29 | #define AT91C_MATRIX_MCFG0 (*(volatile unsigned long*) 0xFFFFEE00) /*(MATRIX) | ||
30 | Master Configuration Register 0 (ram96k) */ | ||
31 | #define AT91C_MATRIX_MCFG7 (*(volatile unsigned long*) 0xFFFFEE1C) /*(MATRIX) | ||
32 | Master Configuration Register 7 (teak_prog) */ | ||
33 | #define AT91C_MATRIX_SCFG1 (*(volatile unsigned long*) 0xFFFFEE44) /*(MATRIX) | ||
34 | Slave Configuration Register 1 (rom) */ | ||
35 | #define AT91C_MATRIX_MCFG4 (*(volatile unsigned long*) 0xFFFFEE10) /*(MATRIX) | ||
36 | Master Configuration Register 4 (bridge) */ | ||
37 | #define AT91C_MATRIX_VERSION (*(volatile unsigned long*) 0xFFFFEFFC) /*(MATRIX) | ||
38 | Version Register */ | ||
39 | #define AT91C_MATRIX_MCFG2 (*(volatile unsigned long*) 0xFFFFEE08) /*(MATRIX) | ||
40 | Master Configuration Register 2 (hperiphs) */ | ||
41 | #define AT91C_MATRIX_PRBS0 (*(volatile unsigned long*) 0xFFFFEE84) /*(MATRIX) | ||
42 | PRBS0 (ram0) */ | ||
43 | #define AT91C_MATRIX_SCFG3 (*(volatile unsigned long*) 0xFFFFEE4C) /*(MATRIX) | ||
44 | Slave Configuration Register 3 (ebi) */ | ||
45 | #define AT91C_MATRIX_MCFG6 (*(volatile unsigned long*) 0xFFFFEE18) /*(MATRIX) | ||
46 | Master Configuration Register 6 (ram16k) */ | ||
47 | #define AT91C_MATRIX_EBI (*(volatile unsigned long*) 0xFFFFEF1C) /*(MATRIX) | ||
48 | Slave 3 (ebi) Special Function Register */ | ||
49 | #define AT91C_MATRIX_SCFG0 (*(volatile unsigned long*) 0xFFFFEE40) /*(MATRIX) | ||
50 | Slave Configuration Register 0 (ram96k) */ | ||
51 | #define AT91C_MATRIX_PRAS0 (*(volatile unsigned long*) 0xFFFFEE80) /*(MATRIX) | ||
52 | PRAS0 (ram0) */ | ||
53 | #define AT91C_MATRIX_MCFG3 (*(volatile unsigned long*) 0xFFFFEE0C) /*(MATRIX) | ||
54 | Master Configuration Register 3 (ebi) */ | ||
55 | #define AT91C_MATRIX_PRAS1 (*(volatile unsigned long*) 0xFFFFEE88) /*(MATRIX) | ||
56 | PRAS1 (ram1) */ | ||
57 | #define AT91C_MATRIX_PRAS2 (*(volatile unsigned long*) 0xFFFFEE90) /*(MATRIX) | ||
58 | PRAS2 (ram2) */ | ||
59 | #define AT91C_MATRIX_SCFG2 (*(volatile unsigned long*) 0xFFFFEE48) /*(MATRIX) | ||
60 | Slave Configuration Register 2 (hperiphs) */ | ||
61 | #define AT91C_MATRIX_MCFG5 (*(volatile unsigned long*) 0xFFFFEE14) /*(MATRIX) | ||
62 | Master Configuration Register 5 (mailbox) */ | ||
63 | #define AT91C_MATRIX_MCFG1 (*(volatile unsigned long*) 0xFFFFEE04) /*(MATRIX) | ||
64 | Master Configuration Register 1 (rom) */ | ||
65 | #define AT91C_MATRIX_MRCR (*(volatile unsigned long*) 0xFFFFEF00) /*(MATRIX) | ||
66 | Master Remp Control Register */ | ||
67 | #define AT91C_MATRIX_PRBS2 (*(volatile unsigned long*) 0xFFFFEE94) /*(MATRIX) | ||
68 | PRBS2 (ram2) */ | ||
69 | #define AT91C_MATRIX_SCFG4 (*(volatile unsigned long*) 0xFFFFEE50) /*(MATRIX) | ||
70 | Slave Configuration Register 4 (bridge) */ | ||
71 | #define AT91C_MATRIX_TEAKCFG (*(volatile unsigned long*) 0xFFFFEF2C) /*(MATRIX) | ||
72 | Slave 7 (teak_prog) Special Function Register */ | ||
73 | #define AT91C_MATRIX_PRBS1 (*(volatile unsigned long*) 0xFFFFEE8C) /*(MATRIX) | ||
74 | PRBS1 (ram1) */ | ||
75 | |||
76 | /* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ | ||
77 | /* - WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register ---- */ | ||
78 | #define AT91C_WDTC_WDRSTT (0x1 << 0) /* (WDTC) Watchdog Restart */ | ||
79 | #define AT91C_WDTC_KEY (0xFF << 24) /* (WDTC) Watchdog KEY Password */ | ||
80 | /* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ | ||
81 | #define AT91C_WDTC_WDV (0xFFF << 0) /* (WDTC) Watchdog Timer Restart */ | ||
82 | #define AT91C_WDTC_WDFIEN (0x1 << 12) /* (WDTC) Watchdog Fault Interrupt | ||
83 | Enable */ | ||
84 | #define AT91C_WDTC_WDRSTEN (0x1 << 13) /* (WDTC) Watchdog Reset Enable */ | ||
85 | #define AT91C_WDTC_WDRPROC (0x1 << 14) /* (WDTC) Watchdog Timer Restart */ | ||
86 | #define AT91C_WDTC_WDDIS (0x1 << 15) /* (WDTC) Watchdog Disable */ | ||
87 | #define AT91C_WDTC_WDD (0xFFF << 16) /* (WDTC) Watchdog Delta Value */ | ||
88 | #define AT91C_WDTC_WDDBGHLT (0x1 << 28) /* (WDTC) Watchdog Debug Halt */ | ||
89 | #define AT91C_WDTC_WDIDLEHLT (0x1 << 29) /* (WDTC) Watchdog Idle Halt */ | ||
90 | /* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register ----- */ | ||
91 | #define AT91C_WDTC_WDUNF (0x1 << 0) /* (WDTC) Watchdog Underflow */ | ||
92 | #define AT91C_WDTC_WDERR (0x1 << 1) /* (WDTC) Watchdog Error */ | ||
93 | |||
94 | /* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ | ||
95 | /* - WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register ---- */ | ||
96 | #define AT91C_WDTC_WDRSTT (0x1 << 0) /* (WDTC) Watchdog Restart */ | ||
97 | #define AT91C_WDTC_KEY (0xFF << 24) /* (WDTC) Watchdog KEY Password */ | ||
98 | /* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ | ||
99 | #define AT91C_WDTC_WDV (0xFFF << 0) /* (WDTC) Watchdog Timer Restart */ | ||
100 | #define AT91C_WDTC_WDFIEN (0x1 << 12) /* (WDTC) Watchdog Fault Interrupt | ||
101 | Enable */ | ||
102 | #define AT91C_WDTC_WDRSTEN (0x1 << 13) /* (WDTC) Watchdog Reset Enable */ | ||
103 | #define AT91C_WDTC_WDRPROC (0x1 << 14) /* (WDTC) Watchdog Timer Restart */ | ||
104 | #define AT91C_WDTC_WDDIS (0x1 << 15) /* (WDTC) Watchdog Disable */ | ||
105 | #define AT91C_WDTC_WDD (0xFFF << 16) /* (WDTC) Watchdog Delta Value */ | ||
106 | #define AT91C_WDTC_WDDBGHLT (0x1 << 28) /* (WDTC) Watchdog Debug Halt */ | ||
107 | #define AT91C_WDTC_WDIDLEHLT (0x1 << 29) /* (WDTC) Watchdog Idle Halt */ | ||
108 | /* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register ----- */ | ||
109 | #define AT91C_WDTC_WDUNF (0x1 << 0) /* (WDTC) Watchdog Underflow */ | ||
110 | #define AT91C_WDTC_WDERR (0x1 << 1) /* (WDTC) Watchdog Error */ | ||
111 | |||
112 | /* Register definition for WDTC peripheral */ | ||
113 | #define AT91C_WDTC_WDCR (*(volatile unsigned long*) 0xFFFFFD40) /* (WDTC) | ||
114 | Watchdog Control Register */ | ||
115 | #define AT91C_WDTC_WDSR (*(volatile unsigned long*) 0xFFFFFD48) /* (WDTC) | ||
116 | Watchdog Status Register */ | ||
117 | #define AT91C_WDTC_WDMR (*(volatile unsigned long*) 0xFFFFFD44) /* (WDTC) | ||
118 | Watchdog Mode Register */ | ||
119 | |||
120 | /* CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register */ | ||
121 | #define AT91C_CKGR_MOSCEN (0x1 << 0) /* (CKGR) Main Oscillator Enable */ | ||
122 | #define AT91C_CKGR_OSCBYPASS (0x1 << 1) /* (CKGR) Main Oscillator Bypass */ | ||
123 | #define AT91C_CKGR_OSCOUNT (0xFF << 8) /* (CKGR) Main Oscillator Start | ||
124 | -up Time */ | ||
125 | /* CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register */ | ||
126 | #define AT91C_CKGR_MAINF (0xFFFF << 0) /* (CKGR) Main Clock Frequency */ | ||
127 | #define AT91C_CKGR_MAINRDY (0x1 << 16) /* (CKGR) Main Clock Ready */ | ||
128 | /* CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register */ | ||
129 | #define AT91C_CKGR_DIVA (0xFF << 0) /* (CKGR) Divider A Selected */ | ||
130 | #define AT91C_CKGR_DIVA_0 (0x0) /* (CKGR) Divider A output is 0 */ | ||
131 | #define AT91C_CKGR_DIVA_BYPASS (0x1) /* (CKGR) Divider A is bypassed */ | ||
132 | #define AT91C_CKGR_PLLACOUNT (0x3F << 8) /* (CKGR) PLL A Counter */ | ||
133 | #define AT91C_CKGR_OUTA (0x3 << 14) /* (CKGR) PLL A Output Frequency Range */ | ||
134 | #define AT91C_CKGR_OUTA_0 (0x0 << 14) /* (CKGR) Please | ||
135 | refer to the PLLA datasheet */ | ||
136 | #define AT91C_CKGR_OUTA_1 (0x1 << 14) /* (CKGR) Please | ||
137 | refer to the PLLA datasheet */ | ||
138 | #define AT91C_CKGR_OUTA_2 (0x2 << 14) /* (CKGR) Please | ||
139 | refer to the PLLA datasheet */ | ||
140 | #define AT91C_CKGR_OUTA_3 (0x3 << 14) /* (CKGR) Please | ||
141 | refer to the PLLA datasheet */ | ||
142 | #define AT91C_CKGR_MULA (0x7FF << 16) /* (CKGR) PLL A Multiplier */ | ||
143 | #define AT91C_CKGR_SRCA (0x1 << 29) /* (CKGR) */ | ||
144 | /* CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register */ | ||
145 | #define AT91C_CKGR_DIVB (0xFF << 0) /* (CKGR) Divider B Selected */ | ||
146 | #define AT91C_CKGR_DIVB_0 (0x0) /* (CKGR) Divider B output is 0 */ | ||
147 | #define AT91C_CKGR_DIVB_BYPASS (0x1) /* (CKGR) Divider B is bypassed */ | ||
148 | #define AT91C_CKGR_PLLBCOUNT (0x3F << 8) /* (CKGR) PLL B Counter */ | ||
149 | #define AT91C_CKGR_OUTB (0x3 << 14) /* (CKGR) PLL B Output Frequency Range */ | ||
150 | #define AT91C_CKGR_OUTB_0 (0x0 << 14) /* (CKGR) Please | ||
151 | refer to the PLLB datasheet */ | ||
152 | #define AT91C_CKGR_OUTB_1 (0x1 << 14) /* (CKGR) Please | ||
153 | refer to the PLLB datasheet */ | ||
154 | #define AT91C_CKGR_OUTB_2 (0x2 << 14) /* (CKGR) Please | ||
155 | refer to the PLLB datasheet */ | ||
156 | #define AT91C_CKGR_OUTB_3 (0x3 << 14) /* (CKGR) Please | ||
157 | refer to the PLLB datasheet */ | ||
158 | #define AT91C_CKGR_MULB (0x7FF << 16) /* (CKGR) PLL B Multiplier */ | ||
159 | #define AT91C_CKGR_USBDIV (0x3 << 28) /* (CKGR) Divider for USB Clocks */ | ||
160 | #define AT91C_CKGR_USBDIV_0 (0x0 << 28) /* (CKGR) | ||
161 | Divider output is PLL clock output */ | ||
162 | #define AT91C_CKGR_USBDIV_1 (0x1 << 28) /* (CKGR) | ||
163 | Divider output is PLL clock output divided by 2 */ | ||
164 | #define AT91C_CKGR_USBDIV_2 (0x2 << 28) /* (CKGR) | ||
165 | Divider output is PLL clock output divided by 4 */ | ||
166 | |||
167 | /* SOFTWARE API DEFINITION FOR Power Management Controler */ | ||
168 | /* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register ----- */ | ||
169 | #define AT91C_PMC_PCK (0x1 << 0) /* (PMC) Processor Clock */ | ||
170 | #define AT91C_PMC_UHP (0x1 << 6) /* (PMC) USB Host Port Clock */ | ||
171 | #define AT91C_PMC_UDP (0x1 << 7) /* (PMC) USB Device Port Clock */ | ||
172 | #define AT91C_PMC_PCK0 (0x1 << 8) /* (PMC) Programmable Clock Output */ | ||
173 | #define AT91C_PMC_PCK1 (0x1 << 9) /* (PMC) Programmable Clock Output */ | ||
174 | #define AT91C_PMC_HCK0 (0x1 << 16) /* (PMC) AHB UHP Clock Output */ | ||
175 | #define AT91C_PMC_HCK1 (0x1 << 17) /* (PMC) AHB LCDC Clock Output */ | ||
176 | /* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ----- */ | ||
177 | /* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register ----- */ | ||
178 | /* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ | ||
179 | /* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register--- */ | ||
180 | /* -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- */ | ||
181 | /* -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- */ | ||
182 | /* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ | ||
183 | #define AT91C_PMC_CSS (0x3 << 0) /* (PMC) Programmable Clock Selection */ | ||
184 | #define AT91C_PMC_CSS_SLOW_CLK (0x0) /* (PMC) Slow Clock is selected */ | ||
185 | #define AT91C_PMC_CSS_MAIN_CLK (0x1) /* (PMC) Main Clock is selected */ | ||
186 | #define AT91C_PMC_CSS_PLLA_CLK (0x2) /* (PMC) Clock from PLL A is selected */ | ||
187 | #define AT91C_PMC_CSS_PLLB_CLK (0x3) /* (PMC) Clock from PLL B is selected */ | ||
188 | #define AT91C_PMC_PRES (0x7 << 2) /* (PMC) Programmable Clock Prescaler */ | ||
189 | #define AT91C_PMC_PRES_CLK (0x0 << 2) /* (PMC) Selected clock */ | ||
190 | #define AT91C_PMC_PRES_CLK_2 (0x1 << 2) /* (PMC) Selected clock | ||
191 | divided by 2 */ | ||
192 | #define AT91C_PMC_PRES_CLK_4 (0x2 << 2) /* (PMC) Selected clock | ||
193 | divided by 4 */ | ||
194 | #define AT91C_PMC_PRES_CLK_8 (0x3 << 2) /* (PMC) Selected clock | ||
195 | divided by 8 */ | ||
196 | #define AT91C_PMC_PRES_CLK_16 (0x4 << 2) /* (PMC) Selected clock | ||
197 | divided by 16 */ | ||
198 | #define AT91C_PMC_PRES_CLK_32 (0x5 << 2) /* (PMC) Selected clock | ||
199 | divided by 32 */ | ||
200 | #define AT91C_PMC_PRES_CLK_64 (0x6 << 2) /* (PMC) Selected clock | ||
201 | divided by 64 */ | ||
202 | #define AT91C_PMC_MDIV (0x3 << 8) /* (PMC) Master Clock Divisionv */ | ||
203 | #define AT91C_PMC_MDIV_1 (0x0 << 8) /* (PMC) The master clock and the | ||
204 | processor clock are the same */ | ||
205 | #define AT91C_PMC_MDIV_2 (0x1 << 8) /* (PMC) The processor clock is twice | ||
206 | as fast as the master clock */ | ||
207 | #define AT91C_PMC_MDIV_3 (0x2 << 8) /* (PMC) The processor clock is four | ||
208 | times faster than the master clock */ | ||
209 | /* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register ----- */ | ||
210 | /* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register ---- */ | ||
211 | #define AT91C_PMC_MOSCS (0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask*/ | ||
212 | #define AT91C_PMC_LOCKA (0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/ | ||
213 | Mask */ | ||
214 | #define AT91C_PMC_LOCKB (0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/ | ||
215 | Mask */ | ||
216 | #define AT91C_PMC_MCKRDY (0x1 << 3) /* (PMC) Master Clock Status/Enable/ | ||
217 | Disable/Mask */ | ||
218 | #define AT91C_PMC_PCK0RDY (0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/ | ||
219 | Disable/Mask */ | ||
220 | #define AT91C_PMC_PCK1RDY (0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/ | ||
221 | Disable/Mask */ | ||
222 | /* ---PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ | ||
223 | /* ------ PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ | ||
224 | #define AT91C_PMC_OSCSEL (0x1 << 7) /* (PMC) 32kHz Oscillator | ||
225 | selection status */ | ||
226 | /* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register ---- */ | ||
227 | |||
228 | /* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ | ||
229 | /* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ | ||
230 | #define AT91C_AIC_PRIOR (0x7 << 0) /* (AIC) Priority Level */ | ||
231 | #define AT91C_AIC_PRIOR_LOWEST (0x0) /* (AIC) Lowest priority | ||
232 | level */ | ||
233 | #define AT91C_AIC_PRIOR_HIGHEST (0x7) /* (AIC) Highest | ||
234 | priority level */ | ||
235 | #define AT91C_AIC_SRCTYPE (0x3 << 5) /* (AIC) Interrupt Source Type */ | ||
236 | #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) /* (AIC) | ||
237 | Internal Sources Code Label Level Sensitive */ | ||
238 | #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) /* (AIC) | ||
239 | Internal Sources Code Label Edge triggered */ | ||
240 | #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) /* (AIC) | ||
241 | External Sources Code Label High-level Sensitive */ | ||
242 | #define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) /* (AIC) | ||
243 | External Sources Code Label Positive Edge triggered */ | ||
244 | /* - AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register ----- */ | ||
245 | #define AT91C_AIC_NFIQ (0x1 << 0) /* (AIC) NFIQ Status */ | ||
246 | #define AT91C_AIC_NIRQ (0x1 << 1) /* (AIC) NIRQ Status */ | ||
247 | /* - AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) ---- */ | ||
248 | #define AT91C_AIC_DCR_PROT (0x1 << 0) /* (AIC) Protection Mode */ | ||
249 | #define AT91C_AIC_DCR_GMSK (0x1 << 1) /* (AIC) General Mask */ | ||
250 | |||
251 | /* Register definition for AIC peripheral */ | ||
252 | #define AT91C_AIC_IVR (*(volatile unsigned long*) 0xFFFFF100) /* (AIC) IRQ | ||
253 | Vector Register */ | ||
254 | #define AIC_IVR 0x00000100 | ||
255 | /* (AIC) Source Mode Register */ | ||
256 | #define AT91C_AIC_SMR(a) (*(volatile unsigned long*) (0xFFFFF000 + 4*(a))) | ||
257 | #define AT91C_AIC_FVR (*(volatile unsigned long*) 0xFFFFF104) /* (AIC) FIQ | ||
258 | Vector Register */ | ||
259 | #define AT91C_AIC_DCR (*(volatile unsigned long*) 0xFFFFF138) /* (AIC) Debug | ||
260 | Control Register (Protect) */ | ||
261 | #define AT91C_AIC_EOICR (*(volatile unsigned long*) 0xFFFFF130) /* (AIC) End | ||
262 | of Interrupt Command Register */ | ||
263 | #define AIC_EOICR 0x00000130 | ||
264 | /* (AIC) Source Vector Register */ | ||
265 | #define AT91C_AIC_SVR(a) (*(volatile unsigned long*) (0xFFFFF080 + 4*(a))) | ||
266 | #define AT91C_AIC_FFSR (*(volatile unsigned long*) 0xFFFFF148) /* (AIC) Fast | ||
267 | Forcing Status Register */ | ||
268 | #define AT91C_AIC_ICCR (*(volatile unsigned long*) 0xFFFFF128) /* (AIC) | ||
269 | Interrupt Clear Command Register */ | ||
270 | #define AT91C_AIC_ISR (*(volatile unsigned long*) 0xFFFFF108) /* (AIC) | ||
271 | Interrupt Status Register */ | ||
272 | #define AT91C_AIC_IMR (*(volatile unsigned long*) 0xFFFFF110) /* (AIC) | ||
273 | Interrupt Mask Register */ | ||
274 | #define AT91C_AIC_IPR (*(volatile unsigned long*) 0xFFFFF10C) /* (AIC) | ||
275 | Interrupt Pending Register */ | ||
276 | #define AT91C_AIC_FFER (*(volatile unsigned long*) 0xFFFFF140) /* (AIC) | ||
277 | Fast Forcing Enable Register */ | ||
278 | #define AT91C_AIC_IECR (*(volatile unsigned long*) 0xFFFFF120) /* (AIC) | ||
279 | Interrupt Enable Command Register */ | ||
280 | #define AT91C_AIC_ISCR (*(volatile unsigned long*) 0xFFFFF12C) /* (AIC) | ||
281 | Interrupt Set Command Register */ | ||
282 | #define AT91C_AIC_FFDR (*(volatile unsigned long*) 0xFFFFF144) /* (AIC) | ||
283 | Fast Forcing Disable Register */ | ||
284 | #define AT91C_AIC_CISR (*(volatile unsigned long*) 0xFFFFF114) /* (AIC) | ||
285 | Core Interrupt Status Register */ | ||
286 | #define AT91C_AIC_IDCR (*(volatile unsigned long*) 0xFFFFF124) /* (AIC) | ||
287 | Interrupt Disable Command Register */ | ||
288 | #define AT91C_AIC_SPU (*(volatile unsigned long*) 0xFFFFF134) /* (AIC) | ||
289 | Spurious Vector Register */ | ||
290 | |||
291 | /* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ | ||
292 | /* PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ | ||
293 | #define AT91C_PITC_PIV (0xFFFFF << 0) /* (PITC) Periodic Interval | ||
294 | Value */ | ||
295 | #define AT91C_PITC_PITEN (0x1 << 24) /* (PITC) Periodic Interval Timer | ||
296 | Enabled */ | ||
297 | #define AT91C_PITC_PITIEN (0x1 << 25) /* (PITC) Periodic Interval Timer | ||
298 | Interrupt Enable */ | ||
299 | /* --- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register - */ | ||
300 | #define AT91C_PITC_PITS (0x1 << 0) /* (PITC) Periodic Interval Timer | ||
301 | Status */ | ||
302 | /* - PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register ---- */ | ||
303 | #define AT91C_PITC_CPIV (0xFFFFF << 0) /* (PITC) Current Periodic | ||
304 | Interval Value */ | ||
305 | #define AT91C_PITC_PICNT (0xFFF << 20) /* (PITC) Periodic Interval Counter */ | ||
306 | /* PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register ---- */ | ||
307 | |||
308 | /* Register definition for AIC peripheral */ | ||
309 | #define AT91C_AIC_IVR (*(volatile unsigned long*) 0xFFFFF100) /* (AIC) IRQ | ||
310 | Vector Register */ | ||
311 | #define AIC_IVR 0x00000100 | ||
312 | #define AT91C_AIC_EOICR (*(volatile unsigned long*) 0xFFFFF130) /* (AIC) End | ||
313 | of Interrupt Command Register */ | ||
314 | #define AIC_EOICR 0x00000130 | ||
315 | |||
316 | /* Register definition for PIOA peripheral */ | ||
317 | #define AT91C_PIOA_ODR (*(volatile unsigned long*) 0xFFFFF414) /* (PIOA) | ||
318 | Output Disable Registerr */ | ||
319 | #define AT91C_PIOA_SODR (*(volatile unsigned long*) 0xFFFFF430) /* (PIOA) | ||
320 | Set Output Data Register */ | ||
321 | #define AT91C_PIOA_ISR (*(volatile unsigned long*) 0xFFFFF44C) /* (PIOA) | ||
322 | Interrupt Status Register */ | ||
323 | #define AT91C_PIOA_ABSR (*(volatile unsigned long*) 0xFFFFF478) /* (PIOA) | ||
324 | AB Select Status Register */ | ||
325 | #define AT91C_PIOA_IER (*(volatile unsigned long*) 0xFFFFF440) /* (PIOA) | ||
326 | Interrupt Enable Register */ | ||
327 | #define AT91C_PIOA_PPUDR (*(volatile unsigned long*) 0xFFFFF460) /* (PIOA) | ||
328 | Pull-up Disable Register */ | ||
329 | #define AT91C_PIOA_IMR (*(volatile unsigned long*) 0xFFFFF448) /* (PIOA) | ||
330 | Interrupt Mask Register */ | ||
331 | #define AT91C_PIOA_PER (*(volatile unsigned long*) 0xFFFFF400) /* (PIOA) | ||
332 | PIO Enable Register */ | ||
333 | #define AT91C_PIOA_IFDR (*(volatile unsigned long*) 0xFFFFF424) /* (PIOA) | ||
334 | Input Filter Disable Register */ | ||
335 | #define AT91C_PIOA_OWDR (*(volatile unsigned long*) 0xFFFFF4A4) /* (PIOA) | ||
336 | Output Write Disable Register */ | ||
337 | #define AT91C_PIOA_MDSR (*(volatile unsigned long*) 0xFFFFF458) /* (PIOA) | ||
338 | Multi-driver Status Register */ | ||
339 | #define AT91C_PIOA_IDR (*(volatile unsigned long*) 0xFFFFF444) /* (PIOA) | ||
340 | Interrupt Disable Register */ | ||
341 | #define AT91C_PIOA_ODSR (*(volatile unsigned long*) 0xFFFFF438) /* (PIOA) | ||
342 | Output Data Status Register */ | ||
343 | #define AT91C_PIOA_PPUSR (*(volatile unsigned long*) 0xFFFFF468) /* (PIOA) | ||
344 | Pull-up Status Register */ | ||
345 | #define AT91C_PIOA_OWSR (*(volatile unsigned long*) 0xFFFFF4A8) /* (PIOA) | ||
346 | Output Write Status Register */ | ||
347 | #define AT91C_PIOA_BSR (*(volatile unsigned long*) 0xFFFFF474) /* (PIOA) | ||
348 | Select B Register */ | ||
349 | #define AT91C_PIOA_OWER (*(volatile unsigned long*) 0xFFFFF4A0) /* (PIOA) | ||
350 | Output Write Enable Register */ | ||
351 | #define AT91C_PIOA_IFER (*(volatile unsigned long*) 0xFFFFF420) /* (PIOA) | ||
352 | Input Filter Enable Register */ | ||
353 | #define AT91C_PIOA_PDSR (*(volatile unsigned long*) 0xFFFFF43C) /* (PIOA) | ||
354 | Pin Data Status Register */ | ||
355 | #define AT91C_PIOA_PPUER (*(volatile unsigned long*) 0xFFFFF464) /* (PIOA) | ||
356 | Pull-up Enable Register */ | ||
357 | #define AT91C_PIOA_OSR (*(volatile unsigned long*) 0xFFFFF418) /* (PIOA) | ||
358 | Output Status Register */ | ||
359 | #define AT91C_PIOA_ASR (*(volatile unsigned long*) 0xFFFFF470) /* (PIOA) | ||
360 | Select A Register */ | ||
361 | #define AT91C_PIOA_MDDR (*(volatile unsigned long*) 0xFFFFF454) /* (PIOA) | ||
362 | Multi-driver Disable Register */ | ||
363 | #define AT91C_PIOA_CODR (*(volatile unsigned long*) 0xFFFFF434) /* (PIOA) | ||
364 | Clear Output Data Register */ | ||
365 | #define AT91C_PIOA_MDER (*(volatile unsigned long*) 0xFFFFF450) /* (PIOA) | ||
366 | Multi-driver Enable Register */ | ||
367 | #define AT91C_PIOA_PDR (*(volatile unsigned long*) 0xFFFFF404) /* (PIOA) | ||
368 | PIO Disable Register */ | ||
369 | #define AT91C_PIOA_IFSR (*(volatile unsigned long*) 0xFFFFF428) /* (PIOA) | ||
370 | Input Filter Status Register */ | ||
371 | #define AT91C_PIOA_OER (*(volatile unsigned long*) 0xFFFFF410) /* (PIOA) | ||
372 | Output Enable Register */ | ||
373 | #define AT91C_PIOA_PSR (*(volatile unsigned long*) 0xFFFFF408) /* (PIOA) | ||
374 | PIO Status Register */ | ||
375 | |||
376 | /* Register definition for PIOB peripheral */ | ||
377 | #define AT91C_PIOB_OWDR (*(volatile unsigned long*) 0xFFFFF6A4) /* (PIOB) | ||
378 | Output Write Disable Register */ | ||
379 | #define AT91C_PIOB_MDER (*(volatile unsigned long*) 0xFFFFF650) /* (PIOB) | ||
380 | Multi-driver Enable Register */ | ||
381 | #define AT91C_PIOB_PPUSR (*(volatile unsigned long*) 0xFFFFF668) /* (PIOB) | ||
382 | Pull-up Status Register */ | ||
383 | #define AT91C_PIOB_IMR (*(volatile unsigned long*) 0xFFFFF648) /* (PIOB) | ||
384 | Interrupt Mask Register */ | ||
385 | #define AT91C_PIOB_ASR (*(volatile unsigned long*) 0xFFFFF670) /* (PIOB) | ||
386 | Select A Register */ | ||
387 | #define AT91C_PIOB_PPUDR (*(volatile unsigned long*) 0xFFFFF660) /* (PIOB) | ||
388 | Pull-up Disable Register */ | ||
389 | #define AT91C_PIOB_PSR (*(volatile unsigned long*) 0xFFFFF608) /* (PIOB) | ||
390 | PIO Status Register */ | ||
391 | #define AT91C_PIOB_IER (*(volatile unsigned long*) 0xFFFFF640) /* (PIOB) | ||
392 | Interrupt Enable Register */ | ||
393 | #define AT91C_PIOB_CODR (*(volatile unsigned long*) 0xFFFFF634) /* (PIOB) | ||
394 | Clear Output Data Register */ | ||
395 | #define AT91C_PIOB_OWER (*(volatile unsigned long*) 0xFFFFF6A0) /* (PIOB) | ||
396 | Output Write Enable Register */ | ||
397 | #define AT91C_PIOB_ABSR (*(volatile unsigned long*) 0xFFFFF678) /* (PIOB) | ||
398 | AB Select Status Register */ | ||
399 | #define AT91C_PIOB_IFDR (*(volatile unsigned long*) 0xFFFFF624) /* (PIOB) | ||
400 | Input Filter Disable Register */ | ||
401 | #define AT91C_PIOB_PDSR (*(volatile unsigned long*) 0xFFFFF63C) /* (PIOB) | ||
402 | Pin Data Status Register */ | ||
403 | #define AT91C_PIOB_IDR (*(volatile unsigned long*) 0xFFFFF644) /* (PIOB) | ||
404 | Interrupt Disable Register */ | ||
405 | #define AT91C_PIOB_OWSR (*(volatile unsigned long*) 0xFFFFF6A8) /* (PIOB) | ||
406 | Output Write Status Register */ | ||
407 | #define AT91C_PIOB_PDR (*(volatile unsigned long*) 0xFFFFF604) /* (PIOB) | ||
408 | PIO Disable Register */ | ||
409 | #define AT91C_PIOB_ODR (*(volatile unsigned long*) 0xFFFFF614) /* (PIOB) | ||
410 | Output Disable Registerr */ | ||
411 | #define AT91C_PIOB_IFSR (*(volatile unsigned long*) 0xFFFFF628) /* (PIOB) | ||
412 | Input Filter Status Register */ | ||
413 | #define AT91C_PIOB_PPUER (*(volatile unsigned long*) 0xFFFFF664) /* (PIOB) | ||
414 | Pull-up Enable Register */ | ||
415 | #define AT91C_PIOB_SODR (*(volatile unsigned long*) 0xFFFFF630) /* (PIOB) | ||
416 | Set Output Data Register */ | ||
417 | #define AT91C_PIOB_ISR (*(volatile unsigned long*) 0xFFFFF64C) /* (PIOB) | ||
418 | Interrupt Status Register */ | ||
419 | #define AT91C_PIOB_ODSR (*(volatile unsigned long*) 0xFFFFF638) /* (PIOB) | ||
420 | Output Data Status Register */ | ||
421 | #define AT91C_PIOB_OSR (*(volatile unsigned long*) 0xFFFFF618) /* (PIOB) | ||
422 | Output Status Register */ | ||
423 | #define AT91C_PIOB_MDSR (*(volatile unsigned long*) 0xFFFFF658) /* (PIOB) | ||
424 | Multi-driver Status Register */ | ||
425 | #define AT91C_PIOB_IFER (*(volatile unsigned long*) 0xFFFFF620) /* (PIOB) | ||
426 | Input Filter Enable Register */ | ||
427 | #define AT91C_PIOB_BSR (*(volatile unsigned long*) 0xFFFFF674) /* (PIOB) | ||
428 | Select B Register */ | ||
429 | #define AT91C_PIOB_MDDR (*(volatile unsigned long*) 0xFFFFF654) /* (PIOB) | ||
430 | Multi-driver Disable Register */ | ||
431 | #define AT91C_PIOB_OER (*(volatile unsigned long*) 0xFFFFF610) /* (PIOB) | ||
432 | Output Enable Register */ | ||
433 | #define AT91C_PIOB_PER (*(volatile unsigned long*) 0xFFFFF600) /* (PIOB) | ||
434 | PIO Enable Register */ | ||
435 | |||
436 | /* Register definition for PIOC peripheral */ | ||
437 | #define AT91C_PIOC_OWDR (*(volatile unsigned long*) 0xFFFFF8A4) /* (PIOC) | ||
438 | Output Write Disable Register */ | ||
439 | #define AT91C_PIOC_SODR (*(volatile unsigned long*) 0xFFFFF830) /* (PIOC) | ||
440 | Set Output Data Register */ | ||
441 | #define AT91C_PIOC_PPUER (*(volatile unsigned long*) 0xFFFFF864) /* (PIOC) | ||
442 | Pull-up Enable Register */ | ||
443 | #define AT91C_PIOC_CODR (*(volatile unsigned long*) 0xFFFFF834) /* (PIOC) | ||
444 | Clear Output Data Register */ | ||
445 | #define AT91C_PIOC_PSR (*(volatile unsigned long*) 0xFFFFF808) /* (PIOC) | ||
446 | PIO Status Register */ | ||
447 | #define AT91C_PIOC_PDR (*(volatile unsigned long*) 0xFFFFF804) /* (PIOC) | ||
448 | PIO Disable Register */ | ||
449 | #define AT91C_PIOC_ODR (*(volatile unsigned long*) 0xFFFFF814) /* (PIOC) | ||
450 | Output Disable Register */ | ||
451 | #define AT91C_PIOC_PPUSR (*(volatile unsigned long*) 0xFFFFF868) /* (PIOC) | ||
452 | Pull-up Status Register */ | ||
453 | #define AT91C_PIOC_ABSR (*(volatile unsigned long*) 0xFFFFF878) /* (PIOC) | ||
454 | AB Select Status Register */ | ||
455 | #define AT91C_PIOC_IFSR (*(volatile unsigned long*) 0xFFFFF828) /* (PIOC) | ||
456 | Input Filter Status Register */ | ||
457 | #define AT91C_PIOC_OER (*(volatile unsigned long*) 0xFFFFF810) /* (PIOC) | ||
458 | Output Enable Register */ | ||
459 | #define AT91C_PIOC_IMR (*(volatile unsigned long*) 0xFFFFF848) /* (PIOC) | ||
460 | Interrupt Mask Register */ | ||
461 | #define AT91C_PIOC_ASR (*(volatile unsigned long*) 0xFFFFF870) /* (PIOC) | ||
462 | Select A Register */ | ||
463 | #define AT91C_PIOC_MDDR (*(volatile unsigned long*) 0xFFFFF854) /* (PIOC) | ||
464 | Multi-driver Disable Register */ | ||
465 | #define AT91C_PIOC_OWSR (*(volatile unsigned long*) 0xFFFFF8A8) /* (PIOC) | ||
466 | Output Write Status Register */ | ||
467 | #define AT91C_PIOC_PER (*(volatile unsigned long*) 0xFFFFF800) /* (PIOC) | ||
468 | PIO Enable Register */ | ||
469 | #define AT91C_PIOC_IDR (*(volatile unsigned long*) 0xFFFFF844) /* (PIOC) | ||
470 | Interrupt Disable Register */ | ||
471 | #define AT91C_PIOC_MDER (*(volatile unsigned long*) 0xFFFFF850) /* (PIOC) | ||
472 | Multi-driver Enable Register */ | ||
473 | #define AT91C_PIOC_PDSR (*(volatile unsigned long*) 0xFFFFF83C) /* (PIOC) | ||
474 | Pin Data Status Register */ | ||
475 | #define AT91C_PIOC_MDSR (*(volatile unsigned long*) 0xFFFFF858) /* (PIOC) | ||
476 | Multi-driver Status Register */ | ||
477 | #define AT91C_PIOC_OWER (*(volatile unsigned long*) 0xFFFFF8A0) /* (PIOC) | ||
478 | Output Write Enable Register */ | ||
479 | #define AT91C_PIOC_BSR (*(volatile unsigned long*) 0xFFFFF874) /* (PIOC) | ||
480 | Select B Register */ | ||
481 | #define AT91C_PIOC_PPUDR (*(volatile unsigned long*) 0xFFFFF860) /* (PIOC) | ||
482 | Pull-up Disable Register */ | ||
483 | #define AT91C_PIOC_IFDR (*(volatile unsigned long*) 0xFFFFF824) /* (PIOC) | ||
484 | Input Filter Disable Register */ | ||
485 | #define AT91C_PIOC_IER (*(volatile unsigned long*) 0xFFFFF840) /* (PIOC) | ||
486 | Interrupt Enable Register */ | ||
487 | #define AT91C_PIOC_OSR (*(volatile unsigned long*) 0xFFFFF818) /* (PIOC) | ||
488 | Output Status Register */ | ||
489 | #define AT91C_PIOC_ODSR (*(volatile unsigned long*) 0xFFFFF838) /* (PIOC) | ||
490 | Output Data Status Register */ | ||
491 | #define AT91C_PIOC_ISR (*(volatile unsigned long*) 0xFFFFF84C) /* (PIOC) | ||
492 | Interrupt Status Register */ | ||
493 | #define AT91C_PIOC_IFER (*(volatile unsigned long*) 0xFFFFF820) /* (PIOC) | ||
494 | Input Filter Enable Register */ | ||
495 | |||
496 | /* Register definition for PMC peripheral */ | ||
497 | #define AT91C_PMC_PCER (*(volatile unsigned long*) 0xFFFFFC10) /* (PMC) | ||
498 | Peripheral Clock Enable Register */ | ||
499 | #define AT91C_PMC_PCKR (*(volatile unsigned long*) 0xFFFFFC40) /* (PMC) | ||
500 | Programmable Clock Register */ | ||
501 | #define AT91C_PMC_MCKR (*(volatile unsigned long*) 0xFFFFFC30) /* (PMC) | ||
502 | Master Clock Register */ | ||
503 | #define AT91C_PMC_PLLAR (*(volatile unsigned long*) 0xFFFFFC28) /* (PMC) | ||
504 | PLL A Register */ | ||
505 | #define AT91C_PMC_PCDR (*(volatile unsigned long*) 0xFFFFFC14) /* (PMC) | ||
506 | Peripheral Clock Disable Register */ | ||
507 | #define AT91C_PMC_SCSR (*(volatile unsigned long*) 0xFFFFFC08) /* (PMC) | ||
508 | System Clock Status Register */ | ||
509 | #define AT91C_PMC_MCFR (*(volatile unsigned long*) 0xFFFFFC24) /* (PMC) | ||
510 | Main Clock Frequency Register */ | ||
511 | #define AT91C_PMC_IMR (*(volatile unsigned long*) 0xFFFFFC6C) /* (PMC) | ||
512 | Interrupt Mask Register */ | ||
513 | #define AT91C_PMC_IER (*(volatile unsigned long*) 0xFFFFFC60) /* (PMC) | ||
514 | Interrupt Enable Register */ | ||
515 | #define AT91C_PMC_MOR (*(volatile unsigned long *) 0xFFFFFC20) /* (PMC) | ||
516 | Main Oscillator Register */ | ||
517 | #define AT91C_PMC_IDR (*(volatile unsigned long *) 0xFFFFFC64) /* (PMC) | ||
518 | Interrupt Disable Register */ | ||
519 | #define AT91C_PMC_PLLBR (*(volatile unsigned long*) 0xFFFFFC2C) /* (PMC) | ||
520 | PLL B Register */ | ||
521 | #define AT91C_PMC_SCDR (*(volatile unsigned long*) 0xFFFFFC04) /* (PMC) | ||
522 | System Clock Disable Register */ | ||
523 | #define AT91C_PMC_PCSR (*(volatile unsigned long*) 0xFFFFFC18) /* (PMC) | ||
524 | Peripheral Clock Status Register */ | ||
525 | #define AT91C_PMC_SCER (*(volatile unsigned long*) 0xFFFFFC00) /* (PMC) | ||
526 | System Clock Enable Register */ | ||
527 | #define AT91C_PMC_SR (*(volatile unsigned long*) 0xFFFFFC68) /* (PMC) | ||
528 | Status Register */ | ||
529 | |||
530 | /* Register definition for PITC peripheral */ | ||
531 | #define AT91C_PITC_PIVR (*(volatile unsigned long*) 0xFFFFFD38) /* (PITC) | ||
532 | Period Interval Value Register */ | ||
533 | #define AT91C_PITC_PISR (*(volatile unsigned long*) 0xFFFFFD34) /* (PITC) | ||
534 | Period Interval Status Register */ | ||
535 | #define AT91C_PITC_PIIR (*(volatile unsigned long*) 0xFFFFFD3C) /* (PITC) | ||
536 | Period Interval Image Register */ | ||
537 | #define AT91C_PITC_PIMR (*(volatile unsigned long*) 0xFFFFFD30) /* (PITC) | ||
538 | Period Interval Mode Register */ | ||
539 | |||
540 | /* PIO DEFINITIONS FOR AT91SAM9260 */ | ||
541 | #define AT91C_PIO_PA0 (1 << 0) /* Pin Controlled by PA0 */ | ||
542 | #define AT91C_PIO_PA1 (1 << 1) /* Pin Controlled by PA1 */ | ||
543 | #define AT91C_PIO_PA10 (1 << 10) /* Pin Controlled by PA10 */ | ||
544 | #define AT91C_PIO_PA11 (1 << 11) /* Pin Controlled by PA11 */ | ||
545 | #define AT91C_PIO_PA12 (1 << 12) /* Pin Controlled by PA12 */ | ||
546 | #define AT91C_PIO_PA13 (1 << 13) /* Pin Controlled by PA13 */ | ||
547 | #define AT91C_PIO_PA14 (1 << 14) /* Pin Controlled by PA14 */ | ||
548 | #define AT91C_PIO_PA15 (1 << 15) /* Pin Controlled by PA15 */ | ||
549 | #define AT91C_PIO_PA16 (1 << 16) /* Pin Controlled by PA16 */ | ||
550 | #define AT91C_PIO_PA17 (1 << 17) /* Pin Controlled by PA17 */ | ||
551 | #define AT91C_PIO_PA18 (1 << 18) /* Pin Controlled by PA18 */ | ||
552 | #define AT91C_PIO_PA19 (1 << 19) /* Pin Controlled by PA19 */ | ||
553 | #define AT91C_PIO_PA2 (1 << 2) /* Pin Controlled by PA2 */ | ||
554 | #define AT91C_PIO_PA20 (1 << 20) /* Pin Controlled by PA20 */ | ||
555 | #define AT91C_PIO_PA21 (1 << 21) /* Pin Controlled by PA21 */ | ||
556 | #define AT91C_PIO_PA22 (1 << 22) /* Pin Controlled by PA22 */ | ||
557 | #define AT91C_PIO_PA23 (1 << 23) /* Pin Controlled by PA23 */ | ||
558 | #define AT91C_PIO_PA24 (1 << 24) /* Pin Controlled by PA24 */ | ||
559 | #define AT91C_PIO_PA25 (1 << 25) /* Pin Controlled by PA25 */ | ||
560 | #define AT91C_PIO_PA26 (1 << 26) /* Pin Controlled by PA26 */ | ||
561 | #define AT91C_PIO_PA27 (1 << 27) /* Pin Controlled by PA27 */ | ||
562 | #define AT91C_PIO_PA28 (1 << 28) /* Pin Controlled by PA28 */ | ||
563 | #define AT91C_PIO_PA29 (1 << 29) /* Pin Controlled by PA29 */ | ||
564 | #define AT91C_PIO_PA3 (1 << 3) /* Pin Controlled by PA3 */ | ||
565 | #define AT91C_PIO_PA30 (1 << 30) /* Pin Controlled by PA30 */ | ||
566 | #define AT91C_PIO_PA31 (1 << 31) /* Pin Controlled by PA31 */ | ||
567 | #define AT91C_PIO_PA4 (1 << 4) /* Pin Controlled by PA4 */ | ||
568 | #define AT91C_PIO_PA5 (1 << 5) /* Pin Controlled by PA5 */ | ||
569 | #define AT91C_PIO_PA6 (1 << 6) /* Pin Controlled by PA6 */ | ||
570 | #define AT91C_PIO_PA7 (1 << 7) /* Pin Controlled by PA7 */ | ||
571 | #define AT91C_PIO_PA8 (1 << 8) /* Pin Controlled by PA8 */ | ||
572 | #define AT91C_PIO_PA9 (1 << 9) /* Pin Controlled by PA9 */ | ||
573 | #define AT91C_PIO_PB0 (1 << 0) /* Pin Controlled by PB0 */ | ||
574 | #define AT91C_PIO_PB1 (1 << 1) /* Pin Controlled by PB1 */ | ||
575 | #define AT91C_PIO_PB10 (1 << 10) /* Pin Controlled by PB10 */ | ||
576 | #define AT91C_PIO_PB11 (1 << 11) /* Pin Controlled by PB11 */ | ||
577 | #define AT91C_PIO_PB12 (1 << 12) /* Pin Controlled by PB12 */ | ||
578 | #define AT91C_PIO_PB13 (1 << 13) /* Pin Controlled by PB13 */ | ||
579 | #define AT91C_PIO_PB14 (1 << 14) /* Pin Controlled by PB14 */ | ||
580 | #define AT91C_PIO_PB15 (1 << 15) /* Pin Controlled by PB15 */ | ||
581 | #define AT91C_PIO_PB16 (1 << 16) /* Pin Controlled by PB16 */ | ||
582 | #define AT91C_PIO_PB17 (1 << 17) /* Pin Controlled by PB17 */ | ||
583 | #define AT91C_PIO_PB18 (1 << 18) /* Pin Controlled by PB18 */ | ||
584 | #define AT91C_PIO_PB19 (1 << 19) /* Pin Controlled by PB19 */ | ||
585 | #define AT91C_PIO_PB2 (1 << 2) /* Pin Controlled by PB2 */ | ||
586 | #define AT91C_PIO_PB20 (1 << 20) /* Pin Controlled by PB20 */ | ||
587 | #define AT91C_PIO_PB21 (1 << 21) /* Pin Controlled by PB21 */ | ||
588 | #define AT91C_PIO_PB22 (1 << 22) /* Pin Controlled by PB22 */ | ||
589 | #define AT91C_PIO_PB23 (1 << 23) /* Pin Controlled by PB23 */ | ||
590 | #define AT91C_PIO_PB24 (1 << 24) /* Pin Controlled by PB24 */ | ||
591 | #define AT91C_PIO_PB25 (1 << 25) /* Pin Controlled by PB25 */ | ||
592 | #define AT91C_PIO_PB26 (1 << 26) /* Pin Controlled by PB26 */ | ||
593 | #define AT91C_PIO_PB27 (1 << 27) /* Pin Controlled by PB27 */ | ||
594 | #define AT91C_PIO_PB28 (1 << 28) /* Pin Controlled by PB28 */ | ||
595 | #define AT91C_PIO_PB29 (1 << 29) /* Pin Controlled by PB29 */ | ||
596 | #define AT91C_PIO_PB3 (1 << 3) /* Pin Controlled by PB3 */ | ||
597 | #define AT91C_PIO_PB30 (1 << 30) /* Pin Controlled by PB30 */ | ||
598 | #define AT91C_PIO_PB31 (1 << 31) /* Pin Controlled by PB31 */ | ||
599 | #define AT91C_PIO_PB4 (1 << 4) /* Pin Controlled by PB4 */ | ||
600 | #define AT91C_PIO_PB5 (1 << 5) /* Pin Controlled by PB5 */ | ||
601 | #define AT91C_PIO_PB6 (1 << 6) /* Pin Controlled by PB6 */ | ||
602 | #define AT91C_PIO_PB7 (1 << 7) /* Pin Controlled by PB7 */ | ||
603 | #define AT91C_PIO_PB8 (1 << 8) /* Pin Controlled by PB8 */ | ||
604 | #define AT91C_PIO_PB9 (1 << 9) /* Pin Controlled by PB9 */ | ||
605 | #define AT91C_PIO_PC0 (1 << 0) /* Pin Controlled by PC0 */ | ||
606 | #define AT91C_PIO_PC1 (1 << 1) /* Pin Controlled by PC1 */ | ||
607 | #define AT91C_PIO_PC10 (1 << 10) /* Pin Controlled by PC10 */ | ||
608 | #define AT91C_PIO_PC11 (1 << 11) /* Pin Controlled by PC11 */ | ||
609 | #define AT91C_PIO_PC12 (1 << 12) /* Pin Controlled by PC12 */ | ||
610 | #define AT91C_PIO_PC13 (1 << 13) /* Pin Controlled by PC13 */ | ||
611 | #define AT91C_PIO_PC14 (1 << 14) /* Pin Controlled by PC14 */ | ||
612 | #define AT91C_PIO_PC15 (1 << 15) /* Pin Controlled by PC15 */ | ||
613 | #define AT91C_PIO_PC16 (1 << 16) /* Pin Controlled by PC16 */ | ||
614 | #define AT91C_PIO_PC17 (1 << 17) /* Pin Controlled by PC17 */ | ||
615 | #define AT91C_PIO_PC18 (1 << 18) /* Pin Controlled by PC18 */ | ||
616 | #define AT91C_PIO_PC19 (1 << 19) /* Pin Controlled by PC19 */ | ||
617 | #define AT91C_PIO_PC2 (1 << 2) /* Pin Controlled by PC2 */ | ||
618 | #define AT91C_PIO_PC20 (1 << 20) /* Pin Controlled by PC20 */ | ||
619 | #define AT91C_PIO_PC21 (1 << 21) /* Pin Controlled by PC21 */ | ||
620 | #define AT91C_PIO_PC22 (1 << 22) /* Pin Controlled by PC22 */ | ||
621 | #define AT91C_PIO_PC23 (1 << 23) /* Pin Controlled by PC23 */ | ||
622 | #define AT91C_PIO_PC24 (1 << 24) /* Pin Controlled by PC24 */ | ||
623 | #define AT91C_PIO_PC25 (1 << 25) /* Pin Controlled by PC25 */ | ||
624 | #define AT91C_PIO_PC26 (1 << 26) /* Pin Controlled by PC26 */ | ||
625 | #define AT91C_PIO_PC27 (1 << 27) /* Pin Controlled by PC27 */ | ||
626 | #define AT91C_PIO_PC28 (1 << 28) /* Pin Controlled by PC28 */ | ||
627 | #define AT91C_PIO_PC29 (1 << 29) /* Pin Controlled by PC29 */ | ||
628 | #define AT91C_PIO_PC3 (1 << 3) /* Pin Controlled by PC3 */ | ||
629 | #define AT91C_PIO_PC30 (1 << 30) /* Pin Controlled by PC30 */ | ||
630 | #define AT91C_PIO_PC31 (1 << 31) /* Pin Controlled by PC31 */ | ||
631 | #define AT91C_PIO_PC4 (1 << 4) /* Pin Controlled by PC4 */ | ||
632 | #define AT91C_PIO_PC5 (1 << 5) /* Pin Controlled by PC5 */ | ||
633 | #define AT91C_PIO_PC6 (1 << 6) /* Pin Controlled by PC6 */ | ||
634 | #define AT91C_PIO_PC7 (1 << 7) /* Pin Controlled by PC7 */ | ||
635 | #define AT91C_PIO_PC8 (1 << 8) /* Pin Controlled by PC8 */ | ||
636 | #define AT91C_PIO_PC9 (1 << 9) /* Pin Controlled by PC9 */ | ||
637 | |||
638 | /* PERIPHERAL ID DEFINITIONS FOR AT91SAM9260 */ | ||
639 | #define AT91C_ID_FIQ ( 0) /* Advanced Interrupt Controller (FIQ) */ | ||
640 | #define AT91C_ID_SYS ( 1) /* System Controller */ | ||
641 | #define AT91C_ID_PIOA ( 2) /* Parallel IO Controller A */ | ||
642 | #define AT91C_ID_PIOB ( 3) /* Parallel IO Controller B */ | ||
643 | #define AT91C_ID_PIOC ( 4) /* Parallel IO Controller C */ | ||
644 | #define AT91C_ID_ADC ( 5) /* ADC */ | ||
645 | #define AT91C_ID_US0 ( 6) /* USART 0 */ | ||
646 | #define AT91C_ID_US1 ( 7) /* USART 1 */ | ||
647 | #define AT91C_ID_US2 ( 8) /* USART 2 */ | ||
648 | #define AT91C_ID_MCI ( 9) /* Multimedia Card Interface 0 */ | ||
649 | #define AT91C_ID_UDP (10) /* USB Device Port */ | ||
650 | #define AT91C_ID_TWI (11) /* Two-Wire Interface */ | ||
651 | #define AT91C_ID_SPI0 (12) /* Serial Peripheral Interface 0 */ | ||
652 | #define AT91C_ID_SPI1 (13) /* Serial Peripheral Interface 1 */ | ||
653 | #define AT91C_ID_SSC0 (14) /* Serial Synchronous Controller 0 */ | ||
654 | #define AT91C_ID_TC0 (17) /* Timer Counter 0 */ | ||
655 | #define AT91C_ID_TC1 (18) /* Timer Counter 1 */ | ||
656 | #define AT91C_ID_TC2 (19) /* Timer Counter 2 */ | ||
657 | #define AT91C_ID_UHP (20) /* USB Host Port */ | ||
658 | #define AT91C_ID_EMAC (21) /* Ethernet Mac */ | ||
659 | #define AT91C_ID_HISI (22) /* Image Sensor Interface */ | ||
660 | #define AT91C_ID_US3 (23) /* USART 3 */ | ||
661 | #define AT91C_ID_US4 (24) /* USART 4 */ | ||
662 | #define AT91C_ID_US5 (25) /* USART 5 */ | ||
663 | #define AT91C_ID_TC3 (26) /* Timer Counter 3 */ | ||
664 | #define AT91C_ID_TC4 (27) /* Timer Counter 4 */ | ||
665 | #define AT91C_ID_TC5 (28) /* Timer Counter 5 */ | ||
666 | #define AT91C_ID_IRQ0 (29) /* Advanced Interrupt Controller (IRQ0) */ | ||
667 | #define AT91C_ID_IRQ1 (30) /* Advanced Interrupt Controller (IRQ1) */ | ||
668 | #define AT91C_ID_IRQ2 (31) /* Advanced Interrupt Controller (IRQ2) */ | ||
669 | #define AT91C_ALL_INT (0xFFFE7FFF) /* ALL VALID INTERRUPTS */ | ||
670 | |||
671 | /* MEMORY MAPPING DEFINITIONS FOR AT91SAM9260 */ | ||
672 | #define AT91C_IRAM_1 (0x00200000) /* Maximum IRAM_1 Area : 4Kbyte | ||
673 | base address */ | ||
674 | #define AT91C_IRAM_1_SIZE (0x00001000) /* Maximum IRAM_1 Area : 4Kbyte size | ||
675 | in byte (4 Kbytes) */ | ||
676 | #define AT91C_EBI_SDRAM_32BIT (0x20000000) /* SDRAM on EBI Chip Select 1 | ||
677 | base address */ | ||
678 | #define AT91C_BASE_AIC 0xFFFFF000 /* (AIC) Base Address */ | ||