1 files changed, 336 insertions, 0 deletions
diff --git a/firmware/drivers/sh7034.h b/firmware/drivers/sh7034.h
new file mode 100644
index 0000000000..6d6fb6d714
--- /dev/null
+++ b/firmware/drivers/sh7034.h
@@ -0,0 +1,336 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2002 by Alan Korr
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SH7034_H__
+#define __SH7034_H__
+#define GBR           0x00000000
+/* register address macros: */
+#define SMR0_ADDR       0x05FFFEC0
+#define BRR0_ADDR       0x05FFFEC1
+#define SCR0_ADDR       0x05FFFEC2
+#define TDR0_ADDR       0x05FFFEC3
+#define SSR0_ADDR       0x05FFFEC4
+#define RDR0_ADDR       0x05FFFEC5
+#define SMR1_ADDR       0x05FFFEC8
+#define BRR1_ADDR       0x05FFFEC9
+#define SCR1_ADDR       0x05FFFECA
+#define TDR1_ADDR       0x05FFFECB
+#define SSR1_ADDR       0x05FFFECC
+#define RDR1_ADDR       0x05FFFECD
+#define ADDRAH_ADDR     0x05FFFEE0
+#define ADDRAL_ADDR     0x05FFFEE1
+#define ADDRBH_ADDR     0x05FFFEE2
+#define ADDRBL_ADDR     0x05FFFEE3
+#define ADDRCH_ADDR     0x05FFFEE4
+#define ADDRCL_ADDR     0x05FFFEE5
+#define ADDRDH_ADDR     0x05FFFEE6
+#define ADDRDL_ADDR     0x05FFFEE7
+#define ADCSR_ADDR      0x05FFFEE8
+#define ADCR_ADDR       0x05FFFEE9
+#define TSTR_ADDR       0x05FFFF00
+#define TSNC_ADDR       0x05FFFF01
+#define TMDR_ADDR       0x05FFFF02
+#define TFCR_ADDR       0x05FFFF03
+#define TCR0_ADDR       0x05FFFF04
+#define TIOR0_ADDR      0x05FFFF05
+#define TIER0_ADDR      0x05FFFF06
+#define TSR0_ADDR       0x05FFFF07
+#define TCNT0_ADDR      0x05FFFF08
+#define GRA0_ADDR       0x05FFFF0A
+#define GRB0_ADDR       0x05FFFF0C
+#define TCR1_ADDR       0x05FFFF0E
+#define TIOR1_ADDR      0x05FFFF0F
+#define TIER1_ADDR      0x05FFFF10
+#define TSR1_ADDR       0x05FFFF11
+#define TCNT1_ADDR      0x05FFFF12
+#define GRA_ADDR1       0x05FFFF14
+#define GRB1_ADDR       0x05FFFF16
+#define TCR2_ADDR       0x05FFFF18
+#define TIOR2_ADDR      0x05FFFF19
+#define TIER2_ADDR      0x05FFFF1A
+#define TSR2_ADDR       0x05FFFF1B
+#define TCNT2_ADDR      0x05FFFF1C
+#define GRA2_ADDR       0x05FFFF1E
+#define GRB2_ADDR       0x05FFFF20
+#define TCR3_ADDR       0x05FFFF22
+#define TIOR3_ADDR      0x05FFFF23
+#define TIER3_ADDR      0x05FFFF24
+#define TSR3_ADDR       0x05FFFF25
+#define TCNT3_ADDR      0x05FFFF26
+#define GRA3_ADDR       0x05FFFF28
+#define GRB3_ADDR       0x05FFFF2A
+#define BRA3_ADDR       0x05FFFF2C
+#define BRB3_ADDR       0x05FFFF2E
+#define TOCR_ADDR       0x05FFFF31
+#define TCR4_ADDR       0x05FFFF32
+#define TIOR4_ADDR      0x05FFFF33
+#define TIER4_ADDR      0x05FFFF34
+#define TSR4_ADDR       0x05FFFF35
+#define TCNT4_ADDR      0x05FFFF36
+#define GRA4_ADDR       0x05FFFF38
+#define GRB4_ADDR       0x05FFFF3A
+#define BRA4_ADDR       0x05FFFF3C
+#define BRB4_ADDR       0x05FFFF3E
+#define SAR0_ADDR       0x05FFFF40
+#define DAR0_ADDR       0x05FFFF44
+#define OR_ADDR         0x05FFFF48
+#define DTCR0_ADDR       0x05FFFF4A
+#define CHCR0_ADDR      0x05FFFF4E
+#define SAR1_ADDR       0x05FFFF50
+#define DAR1_ADDR       0x05FFFF54
+#define DTCR1_ADDR       0x05FFFF5A
+#define CHCR1_ADDR      0x05FFFF5E
+#define SAR2_ADDR       0x05FFFF60
+#define DAR2_ADDR       0x05FFFF64
+#define DTCR2_ADDR       0x05FFFF6A
+#define CHCR2_ADDR      0x05FFFF6E
+#define SAR3_ADDR       0x05FFFF70
+#define DAR3_ADDR       0x05FFFF74
+#define DTCR3_ADDR       0x05FFFF7A
+#define CHCR3_ADDR      0x05FFFF7E
+#define IPRA_ADDR       0x05FFFF84
+#define IPRB_ADDR       0x05FFFF86
+#define IPRC_ADDR       0x05FFFF88
+#define IPRD_ADDR       0x05FFFF8A
+#define IPRE_ADDR       0x05FFFF8C
+#define ICR_ADDR        0x05FFFF8E
+#define BARH_ADDR       0x05FFFF90
+#define BARL_ADDR       0x05FFFF92
+#define BAMRH_ADDR      0x05FFFF94
+#define BAMRL_ADDR      0x05FFFF96
+#define BBR_ADDR        0x05FFFF98
+#define BCR_ADDR        0x05FFFFA0
+#define WCR1_ADDR       0x05FFFFA2
+#define WCR2_ADDR       0x05FFFFA4
+#define WCR3_ADDR       0x05FFFFA6
+#define DCR_ADDR        0x05FFFFA8
+#define PCR_ADDR        0x05FFFFAA
+#define RCR_ADDR        0x05FFFFAC
+#define RTCSR_ADDR      0x05FFFFAE
+#define RTCNT_ADDR      0x05FFFFB0
+#define RTCOR_ADDR      0x05FFFFB2
+#define TCSR_ADDR       0x05FFFFB8
+#define TCNT_ADDR       0x05FFFFB9
+#define RSTCSR_ADDR     0x05FFFFBB
+#define SBYCR_ADDR      0x05FFFFBC
+                        
+#define PADR_ADDR       0x05FFFFC0
+#define PBDR_ADDR       0x05FFFFC2
+#define PAIOR_ADDR      0x05FFFFC4
+#define PBIOR_ADDR      0x05FFFFC6
+#define PACR1_ADDR      0x05FFFFC8
+#define PACR2_ADDR      0x05FFFFCA
+#define PBCR1_ADDR      0x05FFFFCC
+#define PBCR2_ADDR      0x05FFFFCE
+#define PCDR_ADDR       0x05FFFFD0
+                        
+#define CASCR_ADDR      0x05FFFFEE
+/* register macros for direct access: */
+#define SMR0       (*((volatile unsigned char*)SMR0_ADDR))   
+#define BRR0       (*((volatile unsigned char*)BRR0_ADDR))   
+#define SCR0       (*((volatile unsigned char*)SCR0_ADDR))   
+#define TDR0       (*((volatile unsigned char*)TDR0_ADDR))   
+#define SSR0       (*((volatile unsigned char*)SSR0_ADDR))   
+#define RDR0       (*((volatile unsigned char*)RDR0_ADDR))   
+#define SMR1       (*((volatile unsigned char*)SMR1_ADDR))   
+#define BRR1       (*((volatile unsigned char*)BRR1_ADDR))   
+#define SCR1       (*((volatile unsigned char*)SCR1_ADDR))   
+#define TDR1       (*((volatile unsigned char*)TDR1_ADDR))   
+#define SSR1       (*((volatile unsigned char*)SSR1_ADDR))   
+#define RDR1       (*((volatile unsigned char*)RDR1_ADDR))   
+#define ADDRA      (*((volatile unsigned short*)ADDRAH_ADDR)) /* combined */
+#define ADDRAH     (*((volatile unsigned char*)ADDRAH_ADDR)) 
+#define ADDRAL     (*((volatile unsigned char*)ADDRAL_ADDR)) 
+#define ADDRB      (*((volatile unsigned short*)ADDRBH_ADDR)) /* combined */
+#define ADDRBH     (*((volatile unsigned char*)ADDRBH_ADDR)) 
+#define ADDRBL     (*((volatile unsigned char*)ADDRBL_ADDR)) 
+#define ADDRC      (*((volatile unsigned short*)ADDRCJ_ADDR)) /* combined */
+#define ADDRCH     (*((volatile unsigned char*)ADDRCH_ADDR)) 
+#define ADDRCL     (*((volatile unsigned char*)ADDRCL_ADDR)) 
+#define ADDRD      (*((volatile unsigned short*)ADDRDH_ADDR)) /* combined */
+#define ADDRDH     (*((volatile unsigned char*)ADDRDH_ADDR)) 
+#define ADDRDL     (*((volatile unsigned char*)ADDRDL_ADDR)) 
+#define ADCSR      (*((volatile unsigned char*)ADCSR_ADDR))  
+#define ADCR       (*((volatile unsigned char*)ADCR_ADDR))   
+#define TSTR       (*((volatile unsigned char*)TSTR_ADDR))   
+#define TSNC       (*((volatile unsigned char*)TSNC_ADDR))   
+#define TMDR       (*((volatile unsigned char*)TMDR_ADDR))   
+#define TFCR       (*((volatile unsigned char*)TFCR_ADDR))   
+#define TCR0       (*((volatile unsigned char*)TCR0_ADDR))   
+#define TIOR0      (*((volatile unsigned char*)TIOR0_ADDR))  
+#define TIER0      (*((volatile unsigned char*)TIER0_ADDR))  
+#define TSR0       (*((volatile unsigned char*)TSR0_ADDR))   
+#define TCNT0      (*((volatile unsigned short*)TCNT0_ADDR)) 
+#define GRA0       (*((volatile unsigned short*)GRA0_ADDR))  
+#define GRB0       (*((volatile unsigned short*)GRB0_ADDR))  
+#define TCR1       (*((volatile unsigned char*)TCR1_ADDR))   
+#define TIOR1      (*((volatile unsigned char*)TIOR1_ADDR))  
+#define TIER1      (*((volatile unsigned char*)TIER1_ADDR))  
+#define TSR1       (*((volatile unsigned char*)TSR1_ADDR))   
+#define TCNT1      (*((volatile unsigned short*)TCNT1_ADDR)) 
+#define GRA1       (*((volatile unsigned short*)GRA_ADDR))1  
+#define GRB1       (*((volatile unsigned short*)GRB1_ADDR))  
+#define TCR2       (*((volatile unsigned char*)TCR2_ADDR))   
+#define TIOR2      (*((volatile unsigned char*)TIOR2_ADDR))  
+#define TIER2      (*((volatile unsigned char*)TIER2_ADDR))  
+#define TSR2       (*((volatile unsigned char*)TSR2_ADDR))   
+#define TCNT2      (*((volatile unsigned short*)TCNT2_ADDR)) 
+#define GRA2       (*((volatile unsigned short*)GRA2_ADDR))  
+#define GRB2       (*((volatile unsigned short*)GRB2_ADDR))  
+#define TCR3       (*((volatile unsigned char*)TCR3_ADDR))   
+#define TIOR3      (*((volatile unsigned char*)TIOR3_ADDR))  
+#define TIER3      (*((volatile unsigned char*)TIER3_ADDR))  
+#define TSR3       (*((volatile unsigned char*)TSR3_ADDR))   
+#define TCNT3      (*((volatile unsigned short*)TCNT3_ADDR)) 
+#define GRA3       (*((volatile unsigned short*)GRA3_ADDR))  
+#define GRB3       (*((volatile unsigned short*)GRB3_ADDR))  
+#define BRA3       (*((volatile unsigned short*)BRA3_ADDR))  
+#define BRB3       (*((volatile unsigned short*)BRB3_ADDR))  
+#define TOCR       (*((volatile unsigned char*)TOCR_ADDR))   
+#define TCR4       (*((volatile unsigned char*)TCR4_ADDR))   
+#define TIOR4      (*((volatile unsigned char*)TIOR4_ADDR))  
+#define TIER4      (*((volatile unsigned char*)TIER4_ADDR))  
+#define TSR4       (*((volatile unsigned char*)TSR4_ADDR))   
+#define TCNT4      (*((volatile unsigned short*)TCNT4_ADDR)) 
+#define GRA4       (*((volatile unsigned short*)GRA4_ADDR))  
+#define GRB4       (*((volatile unsigned short*)GRB4_ADDR))  
+#define BRA4       (*((volatile unsigned short*)BRA4_ADDR))  
+#define BRB4       (*((volatile unsigned short*)BRB4_ADDR))  
+#define SAR0       (*((volatile unsigned long*)SAR0_ADDR))   
+#define DAR0       (*((volatile unsigned long*)DAR0_ADDR))   
+#define DMAOR      (*((volatile unsigned long*)DMAOR_ADDR))  
+#define DTCR0       (*((volatile unsigned long*)DTCR0_ADDR))   
+#define CHCR0      (*((volatile unsigned short*)CHCR0_ADDR)) 
+#define SAR1       (*((volatile unsigned long*)SAR1_ADDR))   
+#define DAR1       (*((volatile unsigned long*)DAR1_ADDR))   
+#define DTCR1       (*((volatile unsigned long*)DTCR1_ADDR))   
+#define CHCR1      (*((volatile unsigned short*)CHCR1_ADDR)) 
+#define SAR2       (*((volatile unsigned long*)SAR2_ADDR))   
+#define DAR2       (*((volatile unsigned long*)DAR2_ADDR))   
+#define DTCR2       (*((volatile unsigned long*)DTCR2_ADDR))   
+#define HCR2       (*((volatile unsigned short*)CHCR2_ADDR)) 
+#define SAR3       (*((volatile unsigned long*)SAR3_ADDR))   
+#define DAR3       (*((volatile unsigned long*)DAR3_ADDR))   
+#define DTCR3       (*((volatile unsigned long*)DTCR3_ADDR))   
+#define CHCR3      (*((volatile unsigned short*)CHCR3_ADDR)) 
+#define IPRA       (*((volatile unsigned short*)IPRA_ADDR))  
+#define IPRB       (*((volatile unsigned short*)IPRB_ADDR))  
+#define IPRC       (*((volatile unsigned short*)IPRC_ADDR))  
+#define IPRD       (*((volatile unsigned short*)IPRD_ADDR))  
+#define IPRE       (*((volatile unsigned short*)IPRE_ADDR))  
+#define ICR        (*((volatile unsigned short*)ICR_ADDR))   
+#define BAR        (*((volatile unsigned long*)BARH_ADDR))  /* combined */
+#define BARH       (*((volatile unsigned short*)BARH_ADDR))  
+#define BARL       (*((volatile unsigned short*)BARL_ADDR))  
+#define BAMR       (*((volatile unsigned long*)BAMRH_ADDR)) /* combined */
+#define BAMRH      (*((volatile unsigned short*)BAMRH_ADDR)) 
+#define BAMRL      (*((volatile unsigned short*)BAMRL_ADDR)) 
+#define BBR        (*((volatile unsigned short*)BBR_ADDR))   
+#define BCR        (*((volatile unsigned short*)BCR_ADDR))   
+#define WCR1       (*((volatile unsigned short*)WCR1_ADDR))  
+#define WCR2       (*((volatile unsigned short*)WCR2_ADDR))  
+#define WCR3       (*((volatile unsigned short*)WCR3_ADDR))  
+#define DCR        (*((volatile unsigned short*)DCR_ADDR))   
+#define PCR        (*((volatile unsigned short*)PCR_ADDR))   
+#define RCR        (*((volatile unsigned short*)RCR_ADDR))   
+#define RTCSR      (*((volatile unsigned short*)RTCSR_ADDR)) 
+#define RTCNT      (*((volatile unsigned short*)RTCNT_ADDR)) 
+#define RTCOR      (*((volatile unsigned short*)RTCOR_ADDR)) 
+#define TCSR       (*((volatile unsigned char*)TCSR_ADDR))   
+#define TCNT       (*((volatile unsigned char*)TCNT_ADDR))   
+#define RSTCSR     (*((volatile unsigned char*)RSTCSR_ADDR)) 
+#define SBYCR      (*((volatile unsigned char*)SBYCR_ADDR))  
+#define PADR       (*((volatile unsigned short*)PADR_ADDR))  
+#define PBDR       (*((volatile unsigned short*)PBDR_ADDR))  
+#define PAIOR      (*((volatile unsigned short*)PAIOR_ADDR)) 
+#define PBIOR      (*((volatile unsigned short*)PBIOR_ADDR)) 
+#define PACR1      (*((volatile unsigned short*)PACR1_ADDR)) 
+#define PACR2      (*((volatile unsigned short*)PACR2_ADDR)) 
+#define PBCR1      (*((volatile unsigned short*)PBCR1_ADDR)) 
+#define PBCR2      (*((volatile unsigned short*)PBCR2_ADDR)) 
+#define PCDR       (*((volatile unsigned short*)PCDR_ADDR))
+#define CASCR      (*((volatile unsigned char*)CASCR_ADDR))  
+/***************************************************************************
+ * Register bit definitions
+ **************************************************************************/
+/*
+ * Serial mode register bits
+ */
+#define SYNC_MODE             0x80
+#define SEVEN_BIT_DATA        0x40
+#define PARITY_ON             0x20
+#define ODD_PARITY            0x10
+#define STOP_BITS_2           0x08
+#define ENABLE_MULTIP         0x04
+#define PHI_64                0x03
+#define PHI_16                0x02
+#define PHI_4                 0x01
+/*
+ * Serial control register bits
+ */
+#define SCI_TIE               0x80        /* Transmit interrupt enable */
+#define SCI_RIE               0x40        /* Receive interrupt enable */
+#define SCI_TE                0x20        /* Transmit enable */
+#define SCI_RE                0x10        /* Receive enable */
+#define SCI_MPIE              0x08        /* Multiprocessor interrupt enable */
+#define SCI_TEIE              0x04        /* Transmit end interrupt enable */
+#define SCI_CKE1              0x02        /* Clock enable 1 */
+#define SCI_CKE0              0x01        /* Clock enable 0 */
+/*
+ * Serial status register bits
+ */
+#define SCI_TDRE              0x80        /* Transmit data register empty */
+#define SCI_RDRF              0x40        /* Receive data register full */
+#define SCI_ORER              0x20        /* Overrun error */
+#define SCI_FER               0x10        /* Framing error */
+#define SCI_PER               0x08        /* Parity error */
+#define SCI_TEND              0x04        /* Transmit end */
+#define SCI_MPB               0x02        /* Multiprocessor bit */
+#define SCI_MPBT              0x01        /* Multiprocessor bit transfer */
+#endif

diff --git a/firmware/drivers/sh7034.h b/firmware/drivers/sh7034.h new file mode 100644 index 0000000000..6d6fb6d714 --- /dev/null +++ b/firmware/drivers/sh7034.h
@@ -0,0 +1,336 @@
	1	/***************************************************************************
	2	* __________ __ ___.
	3	* Open \______ \ ____ ____ \| \| _\_ \|__ _______ ___
	4	* Source \| _// _ \_/ ___\\| \|/ /\| __ \ / _ \ \/ /
	5	* Jukebox \| \| ( <_> ) \___\| < \| \_\ ( <_> > < <
	6	* Firmware \|____\|_ /\____/ \___ >__\|_ \\|___ /\____/__/\_ \
	7	* \/ \/ \/ \/ \/
	8	* $Id$
	9	*
	10	* Copyright (C) 2002 by Alan Korr
	11	*
	12	* All files in this archive are subject to the GNU General Public License.
	13	* See the file COPYING in the source tree root for full license agreement.
	14	*
	15	* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
	16	* KIND, either express or implied.
	17	*
	18	****************************************************************************/
	19
	20	#ifndef __SH7034_H__
	21	#define __SH7034_H__
	22
	23	#define GBR 0x00000000
	24
	25	/* register address macros: */
	26
	27	#define SMR0_ADDR 0x05FFFEC0
	28	#define BRR0_ADDR 0x05FFFEC1
	29	#define SCR0_ADDR 0x05FFFEC2
	30	#define TDR0_ADDR 0x05FFFEC3
	31	#define SSR0_ADDR 0x05FFFEC4
	32	#define RDR0_ADDR 0x05FFFEC5
	33	#define SMR1_ADDR 0x05FFFEC8
	34	#define BRR1_ADDR 0x05FFFEC9
	35	#define SCR1_ADDR 0x05FFFECA
	36	#define TDR1_ADDR 0x05FFFECB
	37	#define SSR1_ADDR 0x05FFFECC
	38	#define RDR1_ADDR 0x05FFFECD
	39
	40	#define ADDRAH_ADDR 0x05FFFEE0
	41	#define ADDRAL_ADDR 0x05FFFEE1
	42	#define ADDRBH_ADDR 0x05FFFEE2
	43	#define ADDRBL_ADDR 0x05FFFEE3
	44	#define ADDRCH_ADDR 0x05FFFEE4
	45	#define ADDRCL_ADDR 0x05FFFEE5
	46	#define ADDRDH_ADDR 0x05FFFEE6
	47	#define ADDRDL_ADDR 0x05FFFEE7
	48	#define ADCSR_ADDR 0x05FFFEE8
	49	#define ADCR_ADDR 0x05FFFEE9
	50
	51	#define TSTR_ADDR 0x05FFFF00
	52	#define TSNC_ADDR 0x05FFFF01
	53	#define TMDR_ADDR 0x05FFFF02
	54	#define TFCR_ADDR 0x05FFFF03
	55	#define TCR0_ADDR 0x05FFFF04
	56	#define TIOR0_ADDR 0x05FFFF05
	57	#define TIER0_ADDR 0x05FFFF06
	58	#define TSR0_ADDR 0x05FFFF07
	59	#define TCNT0_ADDR 0x05FFFF08
	60	#define GRA0_ADDR 0x05FFFF0A
	61	#define GRB0_ADDR 0x05FFFF0C
	62	#define TCR1_ADDR 0x05FFFF0E
	63	#define TIOR1_ADDR 0x05FFFF0F
	64	#define TIER1_ADDR 0x05FFFF10
	65	#define TSR1_ADDR 0x05FFFF11
	66	#define TCNT1_ADDR 0x05FFFF12
	67	#define GRA_ADDR1 0x05FFFF14
	68	#define GRB1_ADDR 0x05FFFF16
	69	#define TCR2_ADDR 0x05FFFF18
	70	#define TIOR2_ADDR 0x05FFFF19
	71	#define TIER2_ADDR 0x05FFFF1A
	72	#define TSR2_ADDR 0x05FFFF1B
	73	#define TCNT2_ADDR 0x05FFFF1C
	74	#define GRA2_ADDR 0x05FFFF1E
	75	#define GRB2_ADDR 0x05FFFF20
	76	#define TCR3_ADDR 0x05FFFF22
	77	#define TIOR3_ADDR 0x05FFFF23
	78	#define TIER3_ADDR 0x05FFFF24
	79	#define TSR3_ADDR 0x05FFFF25
	80	#define TCNT3_ADDR 0x05FFFF26
	81	#define GRA3_ADDR 0x05FFFF28
	82	#define GRB3_ADDR 0x05FFFF2A
	83	#define BRA3_ADDR 0x05FFFF2C
	84	#define BRB3_ADDR 0x05FFFF2E
	85	#define TOCR_ADDR 0x05FFFF31
	86	#define TCR4_ADDR 0x05FFFF32
	87	#define TIOR4_ADDR 0x05FFFF33
	88	#define TIER4_ADDR 0x05FFFF34
	89	#define TSR4_ADDR 0x05FFFF35
	90	#define TCNT4_ADDR 0x05FFFF36
	91	#define GRA4_ADDR 0x05FFFF38
	92	#define GRB4_ADDR 0x05FFFF3A
	93	#define BRA4_ADDR 0x05FFFF3C
	94	#define BRB4_ADDR 0x05FFFF3E
	95
	96	#define SAR0_ADDR 0x05FFFF40
	97	#define DAR0_ADDR 0x05FFFF44
	98	#define OR_ADDR 0x05FFFF48
	99	#define DTCR0_ADDR 0x05FFFF4A
	100	#define CHCR0_ADDR 0x05FFFF4E
	101	#define SAR1_ADDR 0x05FFFF50
	102	#define DAR1_ADDR 0x05FFFF54
	103	#define DTCR1_ADDR 0x05FFFF5A
	104	#define CHCR1_ADDR 0x05FFFF5E
	105	#define SAR2_ADDR 0x05FFFF60
	106	#define DAR2_ADDR 0x05FFFF64
	107	#define DTCR2_ADDR 0x05FFFF6A
	108	#define CHCR2_ADDR 0x05FFFF6E
	109	#define SAR3_ADDR 0x05FFFF70
	110	#define DAR3_ADDR 0x05FFFF74
	111	#define DTCR3_ADDR 0x05FFFF7A
	112	#define CHCR3_ADDR 0x05FFFF7E
	113
	114	#define IPRA_ADDR 0x05FFFF84
	115	#define IPRB_ADDR 0x05FFFF86
	116	#define IPRC_ADDR 0x05FFFF88
	117	#define IPRD_ADDR 0x05FFFF8A
	118	#define IPRE_ADDR 0x05FFFF8C
	119	#define ICR_ADDR 0x05FFFF8E
	120
	121	#define BARH_ADDR 0x05FFFF90
	122	#define BARL_ADDR 0x05FFFF92
	123	#define BAMRH_ADDR 0x05FFFF94
	124	#define BAMRL_ADDR 0x05FFFF96
	125	#define BBR_ADDR 0x05FFFF98
	126
	127	#define BCR_ADDR 0x05FFFFA0
	128	#define WCR1_ADDR 0x05FFFFA2
	129	#define WCR2_ADDR 0x05FFFFA4
	130	#define WCR3_ADDR 0x05FFFFA6
	131	#define DCR_ADDR 0x05FFFFA8
	132	#define PCR_ADDR 0x05FFFFAA
	133	#define RCR_ADDR 0x05FFFFAC
	134	#define RTCSR_ADDR 0x05FFFFAE
	135	#define RTCNT_ADDR 0x05FFFFB0
	136	#define RTCOR_ADDR 0x05FFFFB2
	137
	138	#define TCSR_ADDR 0x05FFFFB8
	139	#define TCNT_ADDR 0x05FFFFB9
	140	#define RSTCSR_ADDR 0x05FFFFBB
	141
	142	#define SBYCR_ADDR 0x05FFFFBC
	143
	144	#define PADR_ADDR 0x05FFFFC0
	145	#define PBDR_ADDR 0x05FFFFC2
	146	#define PAIOR_ADDR 0x05FFFFC4
	147	#define PBIOR_ADDR 0x05FFFFC6
	148	#define PACR1_ADDR 0x05FFFFC8
	149	#define PACR2_ADDR 0x05FFFFCA
	150	#define PBCR1_ADDR 0x05FFFFCC
	151	#define PBCR2_ADDR 0x05FFFFCE
	152	#define PCDR_ADDR 0x05FFFFD0
	153
	154	#define CASCR_ADDR 0x05FFFFEE
	155
	156
	157	/* register macros for direct access: */
	158
	159	#define SMR0 (((volatile unsigned char)SMR0_ADDR))
	160	#define BRR0 (((volatile unsigned char)BRR0_ADDR))
	161	#define SCR0 (((volatile unsigned char)SCR0_ADDR))
	162	#define TDR0 (((volatile unsigned char)TDR0_ADDR))
	163	#define SSR0 (((volatile unsigned char)SSR0_ADDR))
	164	#define RDR0 (((volatile unsigned char)RDR0_ADDR))
	165	#define SMR1 (((volatile unsigned char)SMR1_ADDR))
	166	#define BRR1 (((volatile unsigned char)BRR1_ADDR))
	167	#define SCR1 (((volatile unsigned char)SCR1_ADDR))
	168	#define TDR1 (((volatile unsigned char)TDR1_ADDR))
	169	#define SSR1 (((volatile unsigned char)SSR1_ADDR))
	170	#define RDR1 (((volatile unsigned char)RDR1_ADDR))
	171
	172	#define ADDRA (((volatile unsigned short)ADDRAH_ADDR)) /* combined */
	173	#define ADDRAH (((volatile unsigned char)ADDRAH_ADDR))
	174	#define ADDRAL (((volatile unsigned char)ADDRAL_ADDR))
	175	#define ADDRB (((volatile unsigned short)ADDRBH_ADDR)) /* combined */
	176	#define ADDRBH (((volatile unsigned char)ADDRBH_ADDR))
	177	#define ADDRBL (((volatile unsigned char)ADDRBL_ADDR))
	178	#define ADDRC (((volatile unsigned short)ADDRCJ_ADDR)) /* combined */
	179	#define ADDRCH (((volatile unsigned char)ADDRCH_ADDR))
	180	#define ADDRCL (((volatile unsigned char)ADDRCL_ADDR))
	181	#define ADDRD (((volatile unsigned short)ADDRDH_ADDR)) /* combined */
	182	#define ADDRDH (((volatile unsigned char)ADDRDH_ADDR))
	183	#define ADDRDL (((volatile unsigned char)ADDRDL_ADDR))
	184	#define ADCSR (((volatile unsigned char)ADCSR_ADDR))
	185	#define ADCR (((volatile unsigned char)ADCR_ADDR))
	186
	187	#define TSTR (((volatile unsigned char)TSTR_ADDR))
	188	#define TSNC (((volatile unsigned char)TSNC_ADDR))
	189	#define TMDR (((volatile unsigned char)TMDR_ADDR))
	190	#define TFCR (((volatile unsigned char)TFCR_ADDR))
	191	#define TCR0 (((volatile unsigned char)TCR0_ADDR))
	192	#define TIOR0 (((volatile unsigned char)TIOR0_ADDR))
	193	#define TIER0 (((volatile unsigned char)TIER0_ADDR))
	194	#define TSR0 (((volatile unsigned char)TSR0_ADDR))
	195	#define TCNT0 (((volatile unsigned short)TCNT0_ADDR))
	196	#define GRA0 (((volatile unsigned short)GRA0_ADDR))
	197	#define GRB0 (((volatile unsigned short)GRB0_ADDR))
	198	#define TCR1 (((volatile unsigned char)TCR1_ADDR))
	199	#define TIOR1 (((volatile unsigned char)TIOR1_ADDR))
	200	#define TIER1 (((volatile unsigned char)TIER1_ADDR))
	201	#define TSR1 (((volatile unsigned char)TSR1_ADDR))
	202	#define TCNT1 (((volatile unsigned short)TCNT1_ADDR))
	203	#define GRA1 (((volatile unsigned short)GRA_ADDR))1
	204	#define GRB1 (((volatile unsigned short)GRB1_ADDR))
	205	#define TCR2 (((volatile unsigned char)TCR2_ADDR))
	206	#define TIOR2 (((volatile unsigned char)TIOR2_ADDR))
	207	#define TIER2 (((volatile unsigned char)TIER2_ADDR))
	208	#define TSR2 (((volatile unsigned char)TSR2_ADDR))
	209	#define TCNT2 (((volatile unsigned short)TCNT2_ADDR))
	210	#define GRA2 (((volatile unsigned short)GRA2_ADDR))
	211	#define GRB2 (((volatile unsigned short)GRB2_ADDR))
	212	#define TCR3 (((volatile unsigned char)TCR3_ADDR))
	213	#define TIOR3 (((volatile unsigned char)TIOR3_ADDR))
	214	#define TIER3 (((volatile unsigned char)TIER3_ADDR))
	215	#define TSR3 (((volatile unsigned char)TSR3_ADDR))
	216	#define TCNT3 (((volatile unsigned short)TCNT3_ADDR))
	217	#define GRA3 (((volatile unsigned short)GRA3_ADDR))
	218	#define GRB3 (((volatile unsigned short)GRB3_ADDR))
	219	#define BRA3 (((volatile unsigned short)BRA3_ADDR))
	220	#define BRB3 (((volatile unsigned short)BRB3_ADDR))
	221	#define TOCR (((volatile unsigned char)TOCR_ADDR))
	222	#define TCR4 (((volatile unsigned char)TCR4_ADDR))
	223	#define TIOR4 (((volatile unsigned char)TIOR4_ADDR))
	224	#define TIER4 (((volatile unsigned char)TIER4_ADDR))
	225	#define TSR4 (((volatile unsigned char)TSR4_ADDR))
	226	#define TCNT4 (((volatile unsigned short)TCNT4_ADDR))
	227	#define GRA4 (((volatile unsigned short)GRA4_ADDR))
	228	#define GRB4 (((volatile unsigned short)GRB4_ADDR))
	229	#define BRA4 (((volatile unsigned short)BRA4_ADDR))
	230	#define BRB4 (((volatile unsigned short)BRB4_ADDR))
	231
	232	#define SAR0 (((volatile unsigned long)SAR0_ADDR))
	233	#define DAR0 (((volatile unsigned long)DAR0_ADDR))
	234	#define DMAOR (((volatile unsigned long)DMAOR_ADDR))
	235	#define DTCR0 (((volatile unsigned long)DTCR0_ADDR))
	236	#define CHCR0 (((volatile unsigned short)CHCR0_ADDR))
	237	#define SAR1 (((volatile unsigned long)SAR1_ADDR))
	238	#define DAR1 (((volatile unsigned long)DAR1_ADDR))
	239	#define DTCR1 (((volatile unsigned long)DTCR1_ADDR))
	240	#define CHCR1 (((volatile unsigned short)CHCR1_ADDR))
	241	#define SAR2 (((volatile unsigned long)SAR2_ADDR))
	242	#define DAR2 (((volatile unsigned long)DAR2_ADDR))
	243	#define DTCR2 (((volatile unsigned long)DTCR2_ADDR))
	244	#define HCR2 (((volatile unsigned short)CHCR2_ADDR))
	245	#define SAR3 (((volatile unsigned long)SAR3_ADDR))
	246	#define DAR3 (((volatile unsigned long)DAR3_ADDR))
	247	#define DTCR3 (((volatile unsigned long)DTCR3_ADDR))
	248	#define CHCR3 (((volatile unsigned short)CHCR3_ADDR))
	249
	250	#define IPRA (((volatile unsigned short)IPRA_ADDR))
	251	#define IPRB (((volatile unsigned short)IPRB_ADDR))
	252	#define IPRC (((volatile unsigned short)IPRC_ADDR))
	253	#define IPRD (((volatile unsigned short)IPRD_ADDR))
	254	#define IPRE (((volatile unsigned short)IPRE_ADDR))
	255	#define ICR (((volatile unsigned short)ICR_ADDR))
	256
	257	#define BAR (((volatile unsigned long)BARH_ADDR)) /* combined */
	258	#define BARH (((volatile unsigned short)BARH_ADDR))
	259	#define BARL (((volatile unsigned short)BARL_ADDR))
	260	#define BAMR (((volatile unsigned long)BAMRH_ADDR)) /* combined */
	261	#define BAMRH (((volatile unsigned short)BAMRH_ADDR))
	262	#define BAMRL (((volatile unsigned short)BAMRL_ADDR))
	263	#define BBR (((volatile unsigned short)BBR_ADDR))
	264
	265	#define BCR (((volatile unsigned short)BCR_ADDR))
	266	#define WCR1 (((volatile unsigned short)WCR1_ADDR))
	267	#define WCR2 (((volatile unsigned short)WCR2_ADDR))
	268	#define WCR3 (((volatile unsigned short)WCR3_ADDR))
	269	#define DCR (((volatile unsigned short)DCR_ADDR))
	270	#define PCR (((volatile unsigned short)PCR_ADDR))
	271	#define RCR (((volatile unsigned short)RCR_ADDR))
	272	#define RTCSR (((volatile unsigned short)RTCSR_ADDR))
	273	#define RTCNT (((volatile unsigned short)RTCNT_ADDR))
	274	#define RTCOR (((volatile unsigned short)RTCOR_ADDR))
	275
	276	#define TCSR (((volatile unsigned char)TCSR_ADDR))
	277	#define TCNT (((volatile unsigned char)TCNT_ADDR))
	278	#define RSTCSR (((volatile unsigned char)RSTCSR_ADDR))
	279
	280	#define SBYCR (((volatile unsigned char)SBYCR_ADDR))
	281
	282	#define PADR (((volatile unsigned short)PADR_ADDR))
	283	#define PBDR (((volatile unsigned short)PBDR_ADDR))
	284	#define PAIOR (((volatile unsigned short)PAIOR_ADDR))
	285	#define PBIOR (((volatile unsigned short)PBIOR_ADDR))
	286	#define PACR1 (((volatile unsigned short)PACR1_ADDR))
	287	#define PACR2 (((volatile unsigned short)PACR2_ADDR))
	288	#define PBCR1 (((volatile unsigned short)PBCR1_ADDR))
	289	#define PBCR2 (((volatile unsigned short)PBCR2_ADDR))
	290	#define PCDR (((volatile unsigned short)PCDR_ADDR))
	291
	292	#define CASCR (((volatile unsigned char)CASCR_ADDR))
	293
	294	/***************************************************************************
	295	* Register bit definitions
	296	**************************************************************************/
	297
	298	/*
	299	* Serial mode register bits
	300	*/
	301
	302	#define SYNC_MODE 0x80
	303	#define SEVEN_BIT_DATA 0x40
	304	#define PARITY_ON 0x20
	305	#define ODD_PARITY 0x10
	306	#define STOP_BITS_2 0x08
	307	#define ENABLE_MULTIP 0x04
	308	#define PHI_64 0x03
	309	#define PHI_16 0x02
	310	#define PHI_4 0x01
	311
	312	/*
	313	* Serial control register bits
	314	*/
	315	#define SCI_TIE 0x80 /* Transmit interrupt enable */
	316	#define SCI_RIE 0x40 /* Receive interrupt enable */
	317	#define SCI_TE 0x20 /* Transmit enable */
	318	#define SCI_RE 0x10 /* Receive enable */
	319	#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */
	320	#define SCI_TEIE 0x04 /* Transmit end interrupt enable */
	321	#define SCI_CKE1 0x02 /* Clock enable 1 */
	322	#define SCI_CKE0 0x01 /* Clock enable 0 */
	323
	324	/*
	325	* Serial status register bits
	326	*/
	327	#define SCI_TDRE 0x80 /* Transmit data register empty */
	328	#define SCI_RDRF 0x40 /* Receive data register full */
	329	#define SCI_ORER 0x20 /* Overrun error */
	330	#define SCI_FER 0x10 /* Framing error */
	331	#define SCI_PER 0x08 /* Parity error */
	332	#define SCI_TEND 0x04 /* Transmit end */
	333	#define SCI_MPB 0x02 /* Multiprocessor bit */
	334	#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */
	335
	336	#endif