diff options
Diffstat (limited to 'firmware/drivers/i2c-async.c')
-rw-r--r-- | firmware/drivers/i2c-async.c | 398 |
1 files changed, 398 insertions, 0 deletions
diff --git a/firmware/drivers/i2c-async.c b/firmware/drivers/i2c-async.c new file mode 100644 index 0000000000..f18bea565f --- /dev/null +++ b/firmware/drivers/i2c-async.c | |||
@@ -0,0 +1,398 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "i2c-async.h" | ||
23 | #include "config.h" | ||
24 | #include "system.h" | ||
25 | #include "kernel.h" | ||
26 | |||
27 | /* To decide on the queue size, typically you should use the formula: | ||
28 | * | ||
29 | * queue size = max { D_1, ..., D_n } * max { T_1, ..., T_m } | ||
30 | * | ||
31 | * where | ||
32 | * | ||
33 | * n = number of busses | ||
34 | * m = number of devices across all busses | ||
35 | * D_i = number of devices on bus i | ||
36 | * T_j = number of queued transactions needed for device j | ||
37 | * | ||
38 | * The idea is to ensure nobody waits for a queue slot, but keep the queue | ||
39 | * size to a minimum so that queue management features don't take too long. | ||
40 | * (They have to iterate over the entire queue with IRQs disabled, so...) | ||
41 | * | ||
42 | * If you don't use the asychronous features then waiting for a queue slot | ||
43 | * is a moot point since you'll be blocking until completion anyway; in that | ||
44 | * case feel free to use single-entry queues. | ||
45 | * | ||
46 | * Note that each bus gets the same sized queue. If this isn't good for | ||
47 | * your target for whatever reason, it might be worth implementing per-bus | ||
48 | * queue sizes here. | ||
49 | */ | ||
50 | #if !defined(I2C_ASYNC_BUS_COUNT) || !defined(I2C_ASYNC_QUEUE_SIZE) | ||
51 | # error "Need to add #defines for i2c-async frontend" | ||
52 | #endif | ||
53 | |||
54 | #if I2C_ASYNC_QUEUE_SIZE < 1 | ||
55 | # error "i2c-async queue size must be >= 1" | ||
56 | #endif | ||
57 | |||
58 | /* Singly-linked list for queuing up transactions */ | ||
59 | typedef struct i2c_async_txn { | ||
60 | struct i2c_async_txn* next; | ||
61 | i2c_descriptor* desc; | ||
62 | int cookie; | ||
63 | } i2c_async_txn; | ||
64 | |||
65 | typedef struct i2c_async_bus { | ||
66 | /* Head/tail of transaction queue. The head always points to the | ||
67 | * currently running transaction, or NULL if the bus is idle. | ||
68 | */ | ||
69 | i2c_async_txn* head; | ||
70 | i2c_async_txn* tail; | ||
71 | |||
72 | /* Head of a free list used to allocate nodes. */ | ||
73 | i2c_async_txn* free; | ||
74 | |||
75 | /* Next unallocated cookie value */ | ||
76 | int nextcookie; | ||
77 | |||
78 | /* Semaphore for reserving a node in the free list. Nodes can only be | ||
79 | * allocated after a successful semaphore_wait(), and after being freed | ||
80 | * semaphore_release() must be called. | ||
81 | */ | ||
82 | struct semaphore sema; | ||
83 | |||
84 | #ifdef HAVE_CORELOCK_OBJECT | ||
85 | /* Corelock is required for multi-core CPUs */ | ||
86 | struct corelock cl; | ||
87 | #endif | ||
88 | } i2c_async_bus; | ||
89 | |||
90 | static i2c_async_txn i2c_async_txns[I2C_ASYNC_BUS_COUNT][I2C_ASYNC_QUEUE_SIZE]; | ||
91 | static i2c_async_bus i2c_async_busses[I2C_ASYNC_BUS_COUNT]; | ||
92 | |||
93 | static i2c_async_txn* i2c_async_popfree(i2c_async_txn** head) | ||
94 | { | ||
95 | i2c_async_txn* node = *head; | ||
96 | *head = node->next; | ||
97 | return node; | ||
98 | } | ||
99 | |||
100 | static void i2c_async_pushfree(i2c_async_txn** head, i2c_async_txn* node) | ||
101 | { | ||
102 | node->next = *head; | ||
103 | *head = node; | ||
104 | } | ||
105 | |||
106 | static i2c_async_txn* i2c_async_pool_init(i2c_async_txn* array, int count) | ||
107 | { | ||
108 | /* Populate forward pointers */ | ||
109 | for(int i = 0; i < count - 1; ++i) | ||
110 | array[i].next = &array[i+1]; | ||
111 | |||
112 | /* Last pointer is NULL */ | ||
113 | array[count - 1].next = NULL; | ||
114 | |||
115 | /* Return head of pool */ | ||
116 | return &array[0]; | ||
117 | } | ||
118 | |||
119 | static void i2c_async_bus_init(int busnr) | ||
120 | { | ||
121 | const int q_size = I2C_ASYNC_QUEUE_SIZE; | ||
122 | |||
123 | i2c_async_bus* bus = &i2c_async_busses[busnr]; | ||
124 | bus->head = bus->tail = NULL; | ||
125 | bus->free = i2c_async_pool_init(i2c_async_txns[busnr], q_size); | ||
126 | bus->nextcookie = 1; | ||
127 | semaphore_init(&bus->sema, q_size, q_size); | ||
128 | corelock_init(&bus->cl); | ||
129 | } | ||
130 | |||
131 | /* Add a node to the end of the transaction queue */ | ||
132 | static void i2c_async_bus_enqueue(i2c_async_bus* bus, i2c_async_txn* node) | ||
133 | { | ||
134 | node->next = NULL; | ||
135 | if(bus->head == NULL) | ||
136 | bus->head = bus->tail = node; | ||
137 | else { | ||
138 | bus->tail->next = node; | ||
139 | bus->tail = node; | ||
140 | } | ||
141 | } | ||
142 | |||
143 | /* Helper function called to run descriptor completion tasks */ | ||
144 | static void i2c_async_bus_complete_desc(i2c_async_bus* bus, int status) | ||
145 | { | ||
146 | i2c_descriptor* d = bus->head->desc; | ||
147 | if(d->callback) | ||
148 | d->callback(status, d); | ||
149 | |||
150 | bus->head->desc = d->next; | ||
151 | } | ||
152 | |||
153 | void __i2c_async_complete_callback(int busnr, int status) | ||
154 | { | ||
155 | i2c_async_bus* bus = &i2c_async_busses[busnr]; | ||
156 | corelock_lock(&bus->cl); | ||
157 | |||
158 | i2c_async_bus_complete_desc(bus, status); | ||
159 | if(status != I2C_STATUS_OK) { | ||
160 | /* Skip remainder of transaction after an error */ | ||
161 | while(bus->head->desc) | ||
162 | i2c_async_bus_complete_desc(bus, I2C_STATUS_SKIPPED); | ||
163 | } | ||
164 | |||
165 | /* Dequeue next transaction if we finished the current one */ | ||
166 | if(!bus->head->desc) { | ||
167 | i2c_async_txn* node = bus->head; | ||
168 | bus->head = node->next; | ||
169 | i2c_async_pushfree(&bus->free, node); | ||
170 | semaphore_release(&bus->sema); | ||
171 | } | ||
172 | |||
173 | if(bus->head) { | ||
174 | /* Submit the next descriptor */ | ||
175 | __i2c_async_submit(busnr, bus->head->desc); | ||
176 | } else { | ||
177 | /* Fixup tail after last transaction */ | ||
178 | bus->tail = NULL; | ||
179 | } | ||
180 | |||
181 | corelock_unlock(&bus->cl); | ||
182 | } | ||
183 | |||
184 | void __i2c_async_init(void) | ||
185 | { | ||
186 | for(int i = 0; i < I2C_ASYNC_BUS_COUNT; ++i) | ||
187 | i2c_async_bus_init(i); | ||
188 | } | ||
189 | |||
190 | int i2c_async_queue(int busnr, int timeout, int q_mode, | ||
191 | int cookie, i2c_descriptor* desc) | ||
192 | { | ||
193 | i2c_async_txn* node; | ||
194 | i2c_async_bus* bus = &i2c_async_busses[busnr]; | ||
195 | int rc = I2C_RC_OK; | ||
196 | |||
197 | int irq = disable_irq_save(); | ||
198 | corelock_lock(&bus->cl); | ||
199 | |||
200 | /* Scan the queue unless q_mode is a simple ADD */ | ||
201 | if(q_mode != I2C_Q_ADD) { | ||
202 | for(node = bus->head; node != NULL; node = node->next) { | ||
203 | if(node->cookie == cookie) { | ||
204 | if(q_mode == I2C_Q_REPLACE && node != bus->head) | ||
205 | node->desc = desc; | ||
206 | else | ||
207 | rc = I2C_RC_NOTADDED; | ||
208 | goto _exit; | ||
209 | } | ||
210 | } | ||
211 | } | ||
212 | |||
213 | /* Try to claim a queue node without blocking if we can */ | ||
214 | if(semaphore_wait(&bus->sema, TIMEOUT_NOBLOCK) != OBJ_WAIT_SUCCEEDED) { | ||
215 | /* Bail out now if caller doesn't want to wait */ | ||
216 | if(timeout == TIMEOUT_NOBLOCK) { | ||
217 | rc = I2C_RC_BUSY; | ||
218 | goto _exit; | ||
219 | } | ||
220 | |||
221 | /* Wait on the semaphore */ | ||
222 | corelock_unlock(&bus->cl); | ||
223 | restore_irq(irq); | ||
224 | if(semaphore_wait(&bus->sema, timeout) == OBJ_WAIT_TIMEDOUT) | ||
225 | return I2C_RC_BUSY; | ||
226 | |||
227 | /* Got a node; re-lock */ | ||
228 | irq = disable_irq_save(); | ||
229 | corelock_lock(&bus->cl); | ||
230 | } | ||
231 | |||
232 | /* Alloc the node and push it to queue */ | ||
233 | node = i2c_async_popfree(&bus->free); | ||
234 | node->desc = desc; | ||
235 | node->cookie = cookie; | ||
236 | i2c_async_bus_enqueue(bus, node); | ||
237 | |||
238 | /* Start the first descriptor if the bus is idle */ | ||
239 | if(node == bus->head) | ||
240 | __i2c_async_submit(busnr, desc); | ||
241 | |||
242 | _exit: | ||
243 | corelock_unlock(&bus->cl); | ||
244 | restore_irq(irq); | ||
245 | return rc; | ||
246 | } | ||
247 | |||
248 | int i2c_async_cancel(int busnr, int cookie) | ||
249 | { | ||
250 | i2c_async_bus* bus = &i2c_async_busses[busnr]; | ||
251 | int rc = I2C_RC_NOTFOUND; | ||
252 | |||
253 | int irq = disable_irq_save(); | ||
254 | corelock_lock(&bus->cl); | ||
255 | |||
256 | /* Bail if queue is empty */ | ||
257 | if(!bus->head) | ||
258 | goto _exit; | ||
259 | |||
260 | /* Check the running transaction for a match */ | ||
261 | if(bus->head->cookie == cookie) { | ||
262 | rc = I2C_RC_BUSY; | ||
263 | goto _exit; | ||
264 | } | ||
265 | |||
266 | /* Walk the queue, starting after the head */ | ||
267 | i2c_async_txn* prev = bus->head; | ||
268 | i2c_async_txn* node = prev->next; | ||
269 | while(node) { | ||
270 | if(node->cookie == cookie) { | ||
271 | prev->next = node->next; | ||
272 | rc = I2C_RC_OK; | ||
273 | goto _exit; | ||
274 | } | ||
275 | |||
276 | prev = node; | ||
277 | node = node->next; | ||
278 | } | ||
279 | |||
280 | _exit: | ||
281 | corelock_unlock(&bus->cl); | ||
282 | restore_irq(irq); | ||
283 | return rc; | ||
284 | } | ||
285 | |||
286 | int i2c_async_reserve_cookies(int busnr, int count) | ||
287 | { | ||
288 | i2c_async_bus* bus = &i2c_async_busses[busnr]; | ||
289 | int ret = bus->nextcookie; | ||
290 | bus->nextcookie += count; | ||
291 | return ret; | ||
292 | } | ||
293 | |||
294 | static void i2c_sync_callback(int status, i2c_descriptor* d) | ||
295 | { | ||
296 | struct semaphore* sem = (struct semaphore*)d->arg; | ||
297 | d->arg = status; | ||
298 | semaphore_release(sem); | ||
299 | } | ||
300 | |||
301 | static void i2c_reg_modify1_callback(int status, i2c_descriptor* d) | ||
302 | { | ||
303 | if(status == I2C_STATUS_OK) { | ||
304 | uint8_t* buf = (uint8_t*)d->buffer[1]; | ||
305 | uint8_t val = *buf; | ||
306 | *buf = (val & ~(d->arg >> 8)) | (d->arg & 0xff); | ||
307 | d->arg = val; | ||
308 | } | ||
309 | } | ||
310 | |||
311 | int i2c_reg_write(int bus, uint8_t addr, uint8_t reg, | ||
312 | int count, const uint8_t* buf) | ||
313 | { | ||
314 | struct semaphore sem; | ||
315 | semaphore_init(&sem, 1, 0); | ||
316 | |||
317 | i2c_descriptor desc; | ||
318 | desc.slave_addr = addr; | ||
319 | desc.bus_cond = I2C_START | I2C_STOP; | ||
320 | desc.tran_mode = I2C_WRITE; | ||
321 | desc.buffer[0] = ® | ||
322 | desc.count[0] = 1; | ||
323 | desc.buffer[1] = (uint8_t*)buf; | ||
324 | desc.count[1] = count; | ||
325 | desc.callback = &i2c_sync_callback; | ||
326 | desc.arg = (intptr_t)&sem; | ||
327 | desc.next = NULL; | ||
328 | |||
329 | i2c_async_queue(bus, TIMEOUT_BLOCK, I2C_Q_ADD, 0, &desc); | ||
330 | semaphore_wait(&sem, TIMEOUT_BLOCK); | ||
331 | |||
332 | return desc.arg; | ||
333 | } | ||
334 | |||
335 | int i2c_reg_read(int bus, uint8_t addr, uint8_t reg, | ||
336 | int count, uint8_t* buf) | ||
337 | { | ||
338 | struct semaphore sem; | ||
339 | semaphore_init(&sem, 1, 0); | ||
340 | |||
341 | i2c_descriptor desc; | ||
342 | desc.slave_addr = addr; | ||
343 | desc.bus_cond = I2C_START | I2C_STOP; | ||
344 | desc.tran_mode = I2C_READ; | ||
345 | desc.buffer[0] = ® | ||
346 | desc.count[0] = 1; | ||
347 | desc.buffer[1] = buf; | ||
348 | desc.count[1] = count; | ||
349 | desc.callback = &i2c_sync_callback; | ||
350 | desc.arg = (intptr_t)&sem; | ||
351 | desc.next = NULL; | ||
352 | |||
353 | i2c_async_queue(bus, TIMEOUT_BLOCK, I2C_Q_ADD, 0, &desc); | ||
354 | semaphore_wait(&sem, TIMEOUT_BLOCK); | ||
355 | |||
356 | return desc.arg; | ||
357 | } | ||
358 | |||
359 | int i2c_reg_modify1(int bus, uint8_t addr, uint8_t reg, | ||
360 | uint8_t clr, uint8_t set, uint8_t* val) | ||
361 | { | ||
362 | struct semaphore sem; | ||
363 | semaphore_init(&sem, 1, 0); | ||
364 | |||
365 | uint8_t buf[2]; | ||
366 | buf[0] = reg; | ||
367 | |||
368 | i2c_descriptor desc[2]; | ||
369 | desc[0].slave_addr = addr; | ||
370 | desc[0].bus_cond = I2C_START | I2C_STOP; | ||
371 | desc[0].tran_mode = I2C_READ; | ||
372 | desc[0].buffer[0] = &buf[0]; | ||
373 | desc[0].count[0] = 1; | ||
374 | desc[0].buffer[1] = &buf[1]; | ||
375 | desc[0].count[1] = 1; | ||
376 | desc[0].callback = &i2c_reg_modify1_callback; | ||
377 | desc[0].arg = (clr << 8) | set; | ||
378 | desc[0].next = &desc[1]; | ||
379 | |||
380 | desc[1].slave_addr = addr; | ||
381 | desc[1].bus_cond = I2C_START | I2C_STOP; | ||
382 | desc[1].tran_mode = I2C_WRITE; | ||
383 | desc[1].buffer[0] = &buf[0]; | ||
384 | desc[1].count[0] = 2; | ||
385 | desc[1].buffer[1] = NULL; | ||
386 | desc[1].count[1] = 0; | ||
387 | desc[1].callback = &i2c_sync_callback; | ||
388 | desc[1].arg = (intptr_t)&sem; | ||
389 | desc[1].next = NULL; | ||
390 | |||
391 | i2c_async_queue(bus, TIMEOUT_BLOCK, I2C_Q_ADD, 0, &desc[0]); | ||
392 | semaphore_wait(&sem, TIMEOUT_BLOCK); | ||
393 | |||
394 | if(val && desc[1].arg == I2C_STATUS_OK) | ||
395 | *val = desc[0].arg; | ||
396 | |||
397 | return desc[1].arg; | ||
398 | } | ||