diff options
Diffstat (limited to 'firmware/crt0.S')
-rw-r--r-- | firmware/crt0.S | 52 |
1 files changed, 36 insertions, 16 deletions
diff --git a/firmware/crt0.S b/firmware/crt0.S index 978510aecb..749039bc37 100644 --- a/firmware/crt0.S +++ b/firmware/crt0.S | |||
@@ -190,28 +190,44 @@ irq_handler: | |||
190 | 190 | ||
191 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz | 191 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz |
192 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ | 192 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ |
193 | move.w #0x8001,%d0 | 193 | #ifdef IRIVER_H100 |
194 | move.w %d0,(0x100,%a0) /* DCR - Synchronous, 32 cycle refresh */ | 194 | move.w #0x8202,%d0 /* DCR - Synchronous, 64 cycle refresh */ |
195 | #else | ||
196 | move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */ | ||
197 | #endif | ||
198 | move.w %d0,(0x100,%a0) | ||
195 | 199 | ||
196 | /* Note: we place the SDRAM on an 0x1000000 (16M) offset because | 200 | /* Note on 32Mbyte models: |
201 | We place the SDRAM on an 0x1000000 (16M) offset because | ||
197 | the 5249 BGA chip has a fault which disables the use of A24. The | 202 | the 5249 BGA chip has a fault which disables the use of A24. The |
198 | suggested workaround by FreeScale is to offset the base address by | 203 | suggested workaround by FreeScale is to offset the base address by |
199 | half the DRAM size and increase the mask to the double. | 204 | half the DRAM size and increase the mask to the double. |
200 | In our case this means that we set the base address 16M ahead and | 205 | In our case this means that we set the base address 16M ahead and |
201 | use a 64M mask. | 206 | use a 64M mask. |
202 | */ | 207 | */ |
203 | move.l #0x31002520,%d0 | 208 | #ifdef IRIVER_H100 |
204 | move.l %d0,(0x108,%a0) /* DACR0 - Base 0x31000000, Banks on 23 and up, | 209 | move.l #0x30002320,%d0 /* DACR0 - Base 0x30000000, Banks on 21 and up, |
210 | CAS latency 1, No refresh yet */ | ||
211 | move.l %d0,(0x108,%a0) | ||
212 | move.l #0x00fc0001,%d0 /* Size: 16M */ | ||
213 | move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */ | ||
214 | #else | ||
215 | move.l #0x31002520,%d0 /* DACR0 - Base 0x31000000, Banks on 23 and up, | ||
205 | CAS latency 1, No refresh yet */ | 216 | CAS latency 1, No refresh yet */ |
217 | move.l %d0,(0x108,%a0) | ||
206 | move.l #0x03fc0001,%d0 /* Size: 64M because of workaround above */ | 218 | move.l #0x03fc0001,%d0 /* Size: 64M because of workaround above */ |
207 | move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */ | 219 | move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */ |
220 | #endif | ||
208 | 221 | ||
209 | /* Precharge */ | 222 | /* Precharge */ |
210 | move.l #0x31002528,%d0 | 223 | move.l #8,%d0 |
211 | move.l %d0,(0x108,%a0) /* DACR0[IP] = 1, next access will issue a | 224 | or.l %d0,(0x108,%a0) /* DACR0[IP] = 1, next access will issue a |
212 | Precharge command */ | 225 | Precharge command */ |
213 | move.l #0xabcd1234,%d0 | 226 | move.l #0xabcd1234,%d0 |
214 | move.l %d0,0x31000000 /* Issue precharge command */ | 227 | move.l %d0,0x30000000 /* Issue precharge command by writing somewhere |
228 | in the SDRAM. (The 0x30000000 address is | ||
229 | mirrored on 32Mbyte devices so it works on | ||
230 | all models.) */ | ||
215 | 231 | ||
216 | /* Let it refresh */ | 232 | /* Let it refresh */ |
217 | move.l #1000,%d0 | 233 | move.l #1000,%d0 |
@@ -220,19 +236,19 @@ irq_handler: | |||
220 | bne .delayloop | 236 | bne .delayloop |
221 | 237 | ||
222 | /* Refresh */ | 238 | /* Refresh */ |
223 | move.l #0x3100a520,%d0 | 239 | move.l #0x8000,%d0 |
224 | move.l %d0,(0x108,%a0) /* Enable refresh */ | 240 | or.l %d0,(0x108,%a0) /* Enable refresh */ |
225 | 241 | ||
226 | /* Mode Register init */ | 242 | /* Mode Register init */ |
227 | move.l #0x3100a560,%d0 /* DACR0[IMRS] = 1, next access will set the | 243 | move.l #0x40,%d0 /* DACR0[IMRS] = 1, next access will set the |
228 | Mode Register */ | 244 | Mode Register */ |
229 | move.l %d0,(0x108,%a0) | 245 | or.l %d0,(0x108,%a0) |
230 | 246 | ||
231 | move.l #0xabcd1234,%d0 | 247 | move.l #0xabcd1234,%d0 |
232 | move.l %d0,0x31000800 /* A12=1 means CASL=1 (a0 is not connected) */ | 248 | move.l %d0,0x30000800 /* A12=1 means CASL=1 (a0 is not connected) */ |
233 | 249 | ||
234 | move.l #0x3100a520,%d0 /* Back to normal, the DRAM is now ready */ | 250 | move.l #0xffffffbf,%d0 |
235 | move.l %d0,(0x108,%a0) | 251 | and.l %d0,(0x108,%a0) /* Back to normal, the DRAM is now ready */ |
236 | #endif | 252 | #endif |
237 | 253 | ||
238 | /* Invalicate cache */ | 254 | /* Invalicate cache */ |
@@ -244,7 +260,11 @@ irq_handler: | |||
244 | movec.l %d0,%cacr | 260 | movec.l %d0,%cacr |
245 | 261 | ||
246 | /* Cache enabled in SDRAM only, buffered writes enabled */ | 262 | /* Cache enabled in SDRAM only, buffered writes enabled */ |
263 | #ifdef IRIVER_H100 | ||
264 | move.l #0x3003c020,%d0 | ||
265 | #else | ||
247 | move.l #0x3103c020,%d0 | 266 | move.l #0x3103c020,%d0 |
267 | #endif | ||
248 | movec.l %d0,%acr0 | 268 | movec.l %d0,%acr0 |
249 | moveq.l #0,%d0 | 269 | moveq.l #0,%d0 |
250 | movec.l %d0,%acr1 | 270 | movec.l %d0,%acr1 |