diff options
Diffstat (limited to 'firmware/crt0.S')
-rw-r--r-- | firmware/crt0.S | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/firmware/crt0.S b/firmware/crt0.S index 9b33f56232..8d014f0a4c 100644 --- a/firmware/crt0.S +++ b/firmware/crt0.S | |||
@@ -18,6 +18,9 @@ | |||
18 | ****************************************************************************/ | 18 | ****************************************************************************/ |
19 | #include "config.h" | 19 | #include "config.h" |
20 | #include "cpu.h" | 20 | #include "cpu.h" |
21 | |||
22 | //#define BOOTLOADER | ||
23 | |||
21 | .section .init.text | 24 | .section .init.text |
22 | .global start | 25 | .global start |
23 | start: | 26 | start: |
@@ -66,14 +69,15 @@ start: | |||
66 | /* Chip select 2 - ATA controller */ | 69 | /* Chip select 2 - ATA controller */ |
67 | move.l #0x20000000,%d0 /* CSAR2 - Base = 0x20000000 */ | 70 | move.l #0x20000000,%d0 /* CSAR2 - Base = 0x20000000 */ |
68 | move.l %d0,(0x098,%a0) | 71 | move.l %d0,(0x098,%a0) |
69 | move.l #0x00000075,%d0 /* CSMR2 - 64K, Only data access */ | 72 | move.l #0x000f0001,%d0 /* CSMR2 - 64K, Only data access */ |
70 | move.l %d0,(0x09c,%a0) | 73 | move.l %d0,(0x09c,%a0) |
71 | move.l #0x00000180,%d0 /* CSCR2 - no wait states, 16 bits, no bursts */ | 74 | move.l #0x00000080,%d0 /* CSCR2 - no wait states, 16 bits, no bursts */ |
72 | move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states. | 75 | move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states. |
73 | We have to be careful with the access times, | 76 | We have to be careful with the access times, |
74 | since IORDY isn't connected to the HDD. */ | 77 | since IORDY isn't connected to the HDD. */ |
75 | 78 | ||
76 | 79 | ||
80 | #ifdef BOOTLOADER | ||
77 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz | 81 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz |
78 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ | 82 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ |
79 | move.l #0x80050000,%d0 | 83 | move.l #0x80050000,%d0 |
@@ -99,6 +103,12 @@ start: | |||
99 | move.l #0xabcd1234,%d0 | 103 | move.l #0xabcd1234,%d0 |
100 | move.l %d0,0x31000000 /* Issue precharge command */ | 104 | move.l %d0,0x31000000 /* Issue precharge command */ |
101 | 105 | ||
106 | /* Let it refresh */ | ||
107 | move.l #1000,%d0 | ||
108 | .delayloop: | ||
109 | subq.l #1,%d0 | ||
110 | bne .delayloop | ||
111 | |||
102 | /* Refresh */ | 112 | /* Refresh */ |
103 | move.l #0x3100a520,%d0 | 113 | move.l #0x3100a520,%d0 |
104 | move.l %d0,(0x108,%a0) /* Enable refresh */ | 114 | move.l %d0,(0x108,%a0) /* Enable refresh */ |
@@ -109,8 +119,12 @@ start: | |||
109 | move.l %d0,(0x108,%a0) | 119 | move.l %d0,(0x108,%a0) |
110 | 120 | ||
111 | move.l #0xabcd1234,%d0 | 121 | move.l #0xabcd1234,%d0 |
112 | move.l %d0,0x31001000 /* A12=1 means CASL=1 */ | 122 | move.l %d0,0x31000800 /* A12=1 means CASL=1 (a0 is not connected) */ |
113 | 123 | ||
124 | move.l #0x3100a520,%d0 /* Back to normal, the DRAM is now ready */ | ||
125 | move.l %d0,(0x108,%a0) | ||
126 | #endif | ||
127 | #if 1 | ||
114 | lea _iramcopy,%a2 | 128 | lea _iramcopy,%a2 |
115 | lea _iramstart,%a3 | 129 | lea _iramstart,%a3 |
116 | lea _iramend,%a4 | 130 | lea _iramend,%a4 |
@@ -121,6 +135,7 @@ start: | |||
121 | bra .iramloop | 135 | bra .iramloop |
122 | .iramloopend: | 136 | .iramloopend: |
123 | 137 | ||
138 | #endif | ||
124 | lea _edata,%a2 | 139 | lea _edata,%a2 |
125 | lea _end,%a4 | 140 | lea _end,%a4 |
126 | clr.l %d0 | 141 | clr.l %d0 |