diff options
Diffstat (limited to 'firmware/crt0.S')
-rw-r--r-- | firmware/crt0.S | 17 |
1 files changed, 5 insertions, 12 deletions
diff --git a/firmware/crt0.S b/firmware/crt0.S index 749039bc37..65577e02b9 100644 --- a/firmware/crt0.S +++ b/firmware/crt0.S | |||
@@ -190,7 +190,7 @@ irq_handler: | |||
190 | 190 | ||
191 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz | 191 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz |
192 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ | 192 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ |
193 | #ifdef IRIVER_H100 | 193 | #if MEM < 32 |
194 | move.w #0x8202,%d0 /* DCR - Synchronous, 64 cycle refresh */ | 194 | move.w #0x8202,%d0 /* DCR - Synchronous, 64 cycle refresh */ |
195 | #else | 195 | #else |
196 | move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */ | 196 | move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */ |
@@ -205,8 +205,8 @@ irq_handler: | |||
205 | In our case this means that we set the base address 16M ahead and | 205 | In our case this means that we set the base address 16M ahead and |
206 | use a 64M mask. | 206 | use a 64M mask. |
207 | */ | 207 | */ |
208 | #ifdef IRIVER_H100 | 208 | #if MEM < 32 |
209 | move.l #0x30002320,%d0 /* DACR0 - Base 0x30000000, Banks on 21 and up, | 209 | move.l #0x31002320,%d0 /* DACR0 - Base 0x31000000, Banks on 21 and up, |
210 | CAS latency 1, No refresh yet */ | 210 | CAS latency 1, No refresh yet */ |
211 | move.l %d0,(0x108,%a0) | 211 | move.l %d0,(0x108,%a0) |
212 | move.l #0x00fc0001,%d0 /* Size: 16M */ | 212 | move.l #0x00fc0001,%d0 /* Size: 16M */ |
@@ -224,10 +224,7 @@ irq_handler: | |||
224 | or.l %d0,(0x108,%a0) /* DACR0[IP] = 1, next access will issue a | 224 | or.l %d0,(0x108,%a0) /* DACR0[IP] = 1, next access will issue a |
225 | Precharge command */ | 225 | Precharge command */ |
226 | move.l #0xabcd1234,%d0 | 226 | move.l #0xabcd1234,%d0 |
227 | move.l %d0,0x30000000 /* Issue precharge command by writing somewhere | 227 | move.l %d0,0x31000000 /* Issue precharge command */ |
228 | in the SDRAM. (The 0x30000000 address is | ||
229 | mirrored on 32Mbyte devices so it works on | ||
230 | all models.) */ | ||
231 | 228 | ||
232 | /* Let it refresh */ | 229 | /* Let it refresh */ |
233 | move.l #1000,%d0 | 230 | move.l #1000,%d0 |
@@ -245,7 +242,7 @@ irq_handler: | |||
245 | or.l %d0,(0x108,%a0) | 242 | or.l %d0,(0x108,%a0) |
246 | 243 | ||
247 | move.l #0xabcd1234,%d0 | 244 | move.l #0xabcd1234,%d0 |
248 | move.l %d0,0x30000800 /* A12=1 means CASL=1 (a0 is not connected) */ | 245 | move.l %d0,0x31000800 /* A12=1 means CASL=1 (a0 is not connected) */ |
249 | 246 | ||
250 | move.l #0xffffffbf,%d0 | 247 | move.l #0xffffffbf,%d0 |
251 | and.l %d0,(0x108,%a0) /* Back to normal, the DRAM is now ready */ | 248 | and.l %d0,(0x108,%a0) /* Back to normal, the DRAM is now ready */ |
@@ -260,11 +257,7 @@ irq_handler: | |||
260 | movec.l %d0,%cacr | 257 | movec.l %d0,%cacr |
261 | 258 | ||
262 | /* Cache enabled in SDRAM only, buffered writes enabled */ | 259 | /* Cache enabled in SDRAM only, buffered writes enabled */ |
263 | #ifdef IRIVER_H100 | ||
264 | move.l #0x3003c020,%d0 | ||
265 | #else | ||
266 | move.l #0x3103c020,%d0 | 260 | move.l #0x3103c020,%d0 |
267 | #endif | ||
268 | movec.l %d0,%acr0 | 261 | movec.l %d0,%acr0 |
269 | moveq.l #0,%d0 | 262 | moveq.l #0,%d0 |
270 | movec.l %d0,%acr1 | 263 | movec.l %d0,%acr1 |