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-rw-r--r--firmware/crt0.S10
1 files changed, 9 insertions, 1 deletions
diff --git a/firmware/crt0.S b/firmware/crt0.S
index b856a8569d..1c52658c7c 100644
--- a/firmware/crt0.S
+++ b/firmware/crt0.S
@@ -594,6 +594,13 @@ irq_handler:
594#endif 594#endif
595 595
596#ifdef BOOTLOADER 596#ifdef BOOTLOADER
597 /* Check if original firmware is still present */
598 lea 0x00001000,%a2
599 move.l (%a2),%d0
600 move.l #0xfbfbfbf1,%d1
601 cmp.l %d0,%d1
602 beq.b .ignorecookie
603
597 /* The cookie is not reset. This must mean that the boot loader 604 /* The cookie is not reset. This must mean that the boot loader
598 has crashed. Let's start the original firmware immediately. */ 605 has crashed. Let's start the original firmware immediately. */
599 lea 0x10017ffc,%a2 606 lea 0x10017ffc,%a2
@@ -604,10 +611,11 @@ irq_handler:
604 /* Clear the cookie again */ 611 /* Clear the cookie again */
605 clr.l (%a2) 612 clr.l (%a2)
606 jmp 8 613 jmp 8
607 614
608.nocookie: 615.nocookie:
609 /* Set the cookie */ 616 /* Set the cookie */
610 move.l %d1,(%a2) 617 move.l %d1,(%a2)
618.ignorecookie:
611 619
612 /* Set up the DRAM controller. The refresh is based on the 11.2896MHz 620 /* Set up the DRAM controller. The refresh is based on the 11.2896MHz
613 clock (5.6448MHz bus frequency). We haven't yet started the PLL */ 621 clock (5.6448MHz bus frequency). We haven't yet started the PLL */