diff options
Diffstat (limited to 'firmware/app.lds')
-rw-r--r-- | firmware/app.lds | 105 |
1 files changed, 93 insertions, 12 deletions
diff --git a/firmware/app.lds b/firmware/app.lds index 3b53c6e46a..e3f6ef2e50 100644 --- a/firmware/app.lds +++ b/firmware/app.lds | |||
@@ -9,8 +9,10 @@ OUTPUT_FORMAT(elf32-littlearm) | |||
9 | OUTPUT_ARCH(arm) | 9 | OUTPUT_ARCH(arm) |
10 | #ifdef CPU_PP | 10 | #ifdef CPU_PP |
11 | INPUT(target/arm/crt0-pp.o) | 11 | INPUT(target/arm/crt0-pp.o) |
12 | #elif defined(OLYMPUS_MROBE_500) | 12 | #elif CONFIG_CPU==DM320 |
13 | INPUT(target/arm/tms320dm320/crt0.o) | 13 | INPUT(target/arm/tms320dm320/crt0.o) |
14 | #elif CONFIG_CPU==S3C2440 | ||
15 | INPUT(target/arm/s3c2440/crt0.o) | ||
14 | #elif CONFIG_CPU == PNX0101 | 16 | #elif CONFIG_CPU == PNX0101 |
15 | INPUT(target/arm/pnx0101/crt0-pnx0101.o) | 17 | INPUT(target/arm/pnx0101/crt0-pnx0101.o) |
16 | #elif defined(CPU_ARM) | 18 | #elif defined(CPU_ARM) |
@@ -61,8 +63,8 @@ INPUT(target/sh/crt0.o) | |||
61 | #elif CONFIG_CPU==S3C2440 | 63 | #elif CONFIG_CPU==S3C2440 |
62 | #define DRAMORIG 0x00000100 + STUBOFFSET | 64 | #define DRAMORIG 0x00000100 + STUBOFFSET |
63 | #define IRAMORIG DRAMORIG | 65 | #define IRAMORIG DRAMORIG |
64 | #define IRAMSIZE 0x1000 | ||
65 | #define IRAM DRAM | 66 | #define IRAM DRAM |
67 | #define IRAMSIZE 0x1000 | ||
66 | #elif CONFIG_CPU==DM320 | 68 | #elif CONFIG_CPU==DM320 |
67 | #define DRAMORIG 0x00900000 + STUBOFFSET | 69 | #define DRAMORIG 0x00900000 + STUBOFFSET |
68 | #define IRAMORIG 0x00000000 | 70 | #define IRAMORIG 0x00000000 |
@@ -182,7 +184,94 @@ SECTIONS | |||
182 | _end = .; | 184 | _end = .; |
183 | } > DRAM | 185 | } > DRAM |
184 | 186 | ||
185 | #else /* End DM320 */ | 187 | #elif CONFIG_CPU==S3C2440 |
188 | .text : | ||
189 | { | ||
190 | loadaddress = .; | ||
191 | _loadaddress = .; | ||
192 | . = ALIGN(0x200); | ||
193 | *(.init.text) | ||
194 | *(.text*) | ||
195 | *(.glue_7) | ||
196 | *(.glue_7t) | ||
197 | . = ALIGN(0x4); | ||
198 | } > DRAM | ||
199 | |||
200 | .rodata : | ||
201 | { | ||
202 | *(.rodata) /* problems without this, dunno why */ | ||
203 | *(.rodata*) | ||
204 | *(.rodata.str1.1) | ||
205 | *(.rodata.str1.4) | ||
206 | . = ALIGN(0x4); | ||
207 | |||
208 | /* Pseudo-allocate the copies of the data sections */ | ||
209 | _datacopy = .; | ||
210 | } > DRAM | ||
211 | |||
212 | /* TRICK ALERT! For RAM execution, we put the .data section at the | ||
213 | same load address as the copy. Thus, we don't waste extra RAM | ||
214 | when we don't actually need the copy. */ | ||
215 | .data : AT ( _datacopy ) | ||
216 | { | ||
217 | _datastart = .; | ||
218 | *(.data*) | ||
219 | . = ALIGN(0x4); | ||
220 | _dataend = .; | ||
221 | } > DRAM | ||
222 | |||
223 | /DISCARD/ : | ||
224 | { | ||
225 | *(.eh_frame) | ||
226 | } | ||
227 | |||
228 | .vectors 0x0 : | ||
229 | { | ||
230 | _vectorsstart = .; | ||
231 | *(.vectors); | ||
232 | _vectorsend = .; | ||
233 | } AT> DRAM | ||
234 | |||
235 | _vectorscopy = LOADADDR(.vectors); | ||
236 | |||
237 | .iram : | ||
238 | { | ||
239 | _iramstart = .; | ||
240 | *(.icode) | ||
241 | *(.irodata) | ||
242 | *(.idata) | ||
243 | _iramend = .; | ||
244 | } > DRAM | ||
245 | |||
246 | _iramcopy = LOADADDR(.iram); | ||
247 | |||
248 | .ibss (NOLOAD) : | ||
249 | { | ||
250 | _iedata = .; | ||
251 | *(.ibss) | ||
252 | . = ALIGN(0x4); | ||
253 | _iend = .; | ||
254 | } > DRAM | ||
255 | |||
256 | .stack : | ||
257 | { | ||
258 | *(.stack) | ||
259 | stackbegin = .; | ||
260 | . += 0x2000; | ||
261 | stackend = .; | ||
262 | } > DRAM | ||
263 | |||
264 | .bss : | ||
265 | { | ||
266 | _edata = .; | ||
267 | *(.bss*) | ||
268 | *(COMMON) | ||
269 | . = ALIGN(0x4); | ||
270 | _end = .; | ||
271 | } > DRAM | ||
272 | |||
273 | #else /* End CONFIG_CPU */ | ||
274 | |||
186 | #if !defined(CPU_ARM) | 275 | #if !defined(CPU_ARM) |
187 | .vectors : | 276 | .vectors : |
188 | { | 277 | { |
@@ -241,11 +330,7 @@ SECTIONS | |||
241 | } | 330 | } |
242 | 331 | ||
243 | #if defined(CPU_ARM) | 332 | #if defined(CPU_ARM) |
244 | #if CONFIG_CPU==DM320 | ||
245 | .vectors IRAMORIG : | ||
246 | #else | ||
247 | .vectors 0x0 : | 333 | .vectors 0x0 : |
248 | #endif | ||
249 | { | 334 | { |
250 | _vectorsstart = .; | 335 | _vectorsstart = .; |
251 | *(.vectors); | 336 | *(.vectors); |
@@ -253,8 +338,6 @@ SECTIONS | |||
253 | #if CONFIG_CPU==PNX0101 | 338 | #if CONFIG_CPU==PNX0101 |
254 | *(.dmabuf) | 339 | *(.dmabuf) |
255 | } >IRAM0 AT> DRAM | 340 | } >IRAM0 AT> DRAM |
256 | #elif CONFIG_CPU==DM320 | ||
257 | } > IRAM AT> DRAM | ||
258 | #else | 341 | #else |
259 | } AT> DRAM | 342 | } AT> DRAM |
260 | #endif | 343 | #endif |
@@ -264,8 +347,6 @@ SECTIONS | |||
264 | 347 | ||
265 | #if CONFIG_CPU==PNX0101 | 348 | #if CONFIG_CPU==PNX0101 |
266 | .iram IRAMORIG + SIZEOF(.vectors) : | 349 | .iram IRAMORIG + SIZEOF(.vectors) : |
267 | #elif CONFIG_CPU==S3C2440 || CONFIG_CPU==DM320 | ||
268 | .iram : | ||
269 | #else | 350 | #else |
270 | .iram IRAMORIG : | 351 | .iram IRAMORIG : |
271 | #endif | 352 | #endif |
@@ -325,7 +406,7 @@ SECTIONS | |||
325 | 406 | ||
326 | #if defined(CPU_COLDFIRE) | 407 | #if defined(CPU_COLDFIRE) |
327 | .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram): | 408 | .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram): |
328 | #elif defined(CPU_ARM) && CONFIG_CPU != S3C2440 | 409 | #elif defined(CPU_ARM) |
329 | .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors): | 410 | .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors): |
330 | #else | 411 | #else |
331 | .bss : | 412 | .bss : |