diff options
Diffstat (limited to 'apps/codecs')
-rw-r--r-- | apps/codecs/nsf.c | 65 |
1 files changed, 40 insertions, 25 deletions
diff --git a/apps/codecs/nsf.c b/apps/codecs/nsf.c index 92d0240200..6f780342fd 100644 --- a/apps/codecs/nsf.c +++ b/apps/codecs/nsf.c | |||
@@ -29,20 +29,35 @@ | |||
29 | 29 | ||
30 | CODEC_HEADER | 30 | CODEC_HEADER |
31 | 31 | ||
32 | /* arm doesn't benefit from IRAM? */ | 32 | #if (CONFIG_CPU == MCF5250) |
33 | #ifdef CPU_ARM | 33 | #define ICODE_INSTEAD_OF_INLINE |
34 | #undef ICODE_ATTR | 34 | /* Enough IRAM to move additional data and code to it. */ |
35 | #define ICODE_ATTR | 35 | #define IBSS_ATTR_NSF_LARGE_IRAM IBSS_ATTR |
36 | #undef IDATA_ATTR | 36 | #define ICONST_ATTR_NSF_LARGE_IRAM ICONST_ATTR |
37 | #define IDATA_ATTR | 37 | |
38 | #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024) | ||
39 | #define ICODE_INSTEAD_OF_INLINE | ||
40 | /* Enough IRAM to move additional data and code to it. */ | ||
41 | #define IBSS_ATTR_NSF_LARGE_IRAM IBSS_ATTR | ||
42 | #define ICONST_ATTR_NSF_LARGE_IRAM ICONST_ATTR | ||
43 | |||
44 | #elif defined(CPU_S5L870X) | ||
45 | #define ICODE_INSTEAD_OF_INLINE | ||
46 | /* Very large IRAM. Move even more data to it. */ | ||
47 | #define IBSS_ATTR_NSF_LARGE_IRAM IBSS_ATTR | ||
48 | #define ICONST_ATTR_NSF_LARGE_IRAM ICONST_ATTR | ||
49 | |||
38 | #else | 50 | #else |
39 | #define ICODE_INSTEAD_OF_INLINE | 51 | #define ICODE_INSTEAD_OF_INLINE |
52 | /* Not enough IRAM available. */ | ||
53 | #define IBSS_ATTR_NSF_LARGE_IRAM | ||
54 | #define ICONST_ATTR_NSF_LARGE_IRAM | ||
40 | #endif | 55 | #endif |
41 | 56 | ||
42 | /* Maximum number of bytes to process in one iteration */ | 57 | /* Maximum number of bytes to process in one iteration */ |
43 | #define WAV_CHUNK_SIZE (1024*2) | 58 | #define WAV_CHUNK_SIZE (1024*2) |
44 | 59 | ||
45 | static int16_t samples[WAV_CHUNK_SIZE] IBSS_ATTR; | 60 | static int16_t samples[WAV_CHUNK_SIZE] IBSS_ATTR MEM_ALIGN_ATTR; |
46 | 61 | ||
47 | #define ZEROMEMORY(addr,size) memset(addr,0,size) | 62 | #define ZEROMEMORY(addr,size) memset(addr,0,size) |
48 | 63 | ||
@@ -172,7 +187,7 @@ union QUAD | |||
172 | 187 | ||
173 | /****************** tables */ | 188 | /****************** tables */ |
174 | static const int32_t ModulationTable[8] ICONST_ATTR = {0,1,2,4,0,-4,-2,-1}; | 189 | static const int32_t ModulationTable[8] ICONST_ATTR = {0,1,2,4,0,-4,-2,-1}; |
175 | const uint16_t DMC_FREQ_TABLE[2][0x10] = { | 190 | const uint16_t DMC_FREQ_TABLE[2][0x10] ICONST_ATTR_NSF_LARGE_IRAM = { |
176 | /* NTSC */ | 191 | /* NTSC */ |
177 | {0x1AC,0x17C,0x154,0x140,0x11E,0x0FE,0x0E2,0x0D6,0x0BE,0x0A0,0x08E,0x080, | 192 | {0x1AC,0x17C,0x154,0x140,0x11E,0x0FE,0x0E2,0x0D6,0x0BE,0x0A0,0x08E,0x080, |
178 | 0x06A,0x054,0x048,0x036}, | 193 | 0x06A,0x054,0x048,0x036}, |
@@ -181,15 +196,15 @@ const uint16_t DMC_FREQ_TABLE[2][0x10] = { | |||
181 | 0x062,0x04E,0x042,0x032} | 196 | 0x062,0x04E,0x042,0x032} |
182 | }; | 197 | }; |
183 | 198 | ||
184 | const uint8_t DUTY_CYCLE_TABLE[4] = {2,4,8,12}; | 199 | const uint8_t DUTY_CYCLE_TABLE[4] ICONST_ATTR_NSF_LARGE_IRAM = {2,4,8,12}; |
185 | 200 | ||
186 | const uint8_t LENGTH_COUNTER_TABLE[0x20] = { | 201 | const uint8_t LENGTH_COUNTER_TABLE[0x20] ICONST_ATTR_NSF_LARGE_IRAM = { |
187 | 0x0A,0xFE,0x14,0x02,0x28,0x04,0x50,0x06,0xA0,0x08,0x3C,0x0A,0x0E,0x0C,0x1A, | 202 | 0x0A,0xFE,0x14,0x02,0x28,0x04,0x50,0x06,0xA0,0x08,0x3C,0x0A,0x0E,0x0C,0x1A, |
188 | 0x0E,0x0C,0x10,0x18,0x12,0x30,0x14,0x60,0x16,0xC0,0x18,0x48,0x1A,0x10,0x1C, | 203 | 0x0E,0x0C,0x10,0x18,0x12,0x30,0x14,0x60,0x16,0xC0,0x18,0x48,0x1A,0x10,0x1C, |
189 | 0x20,0x1E | 204 | 0x20,0x1E |
190 | }; | 205 | }; |
191 | 206 | ||
192 | const uint16_t NOISE_FREQ_TABLE[0x10] = { | 207 | const uint16_t NOISE_FREQ_TABLE[0x10] ICONST_ATTR_NSF_LARGE_IRAM = { |
193 | 0x004,0x008,0x010,0x020,0x040,0x060,0x080,0x0A0,0x0CA,0x0FE,0x17C,0x1FC, | 208 | 0x004,0x008,0x010,0x020,0x040,0x060,0x080,0x0A0,0x0CA,0x0FE,0x17C,0x1FC, |
194 | 0x2FA,0x3F8,0x7F2,0xFE4 | 209 | 0x2FA,0x3F8,0x7F2,0xFE4 |
195 | }; | 210 | }; |
@@ -589,7 +604,7 @@ struct FDSWave | |||
589 | int32_t nPopCount; | 604 | int32_t nPopCount; |
590 | 605 | ||
591 | }; | 606 | }; |
592 | int16_t FDS_nOutputTable_L[4][0x21][0x40]; | 607 | int16_t FDS_nOutputTable_L[4][0x21][0x40] IBSS_ATTR_NSF_LARGE_IRAM MEM_ALIGN_ATTR; |
593 | 608 | ||
594 | struct FME07Wave | 609 | struct FME07Wave |
595 | { | 610 | { |
@@ -610,7 +625,7 @@ struct FME07Wave | |||
610 | int32_t nMixL; | 625 | int32_t nMixL; |
611 | }; | 626 | }; |
612 | 627 | ||
613 | int16_t FME07_nOutputTable_L[0x10] IDATA_ATTR; | 628 | int16_t FME07_nOutputTable_L[0x10] IDATA_ATTR MEM_ALIGN_ATTR; |
614 | 629 | ||
615 | struct N106Wave | 630 | struct N106Wave |
616 | { | 631 | { |
@@ -650,7 +665,7 @@ struct N106Wave | |||
650 | int32_t nMixL[8]; | 665 | int32_t nMixL[8]; |
651 | }; | 666 | }; |
652 | 667 | ||
653 | int16_t N106_nOutputTable_L[0x10][0x10]; | 668 | int16_t N106_nOutputTable_L[0x10][0x10] IBSS_ATTR_NSF_LARGE_IRAM MEM_ALIGN_ATTR; |
654 | 669 | ||
655 | struct VRC6PulseWave | 670 | struct VRC6PulseWave |
656 | { | 671 | { |
@@ -675,7 +690,7 @@ struct VRC6PulseWave | |||
675 | 690 | ||
676 | }; | 691 | }; |
677 | 692 | ||
678 | int16_t VRC6Pulse_nOutputTable_L[0x10] IDATA_ATTR; | 693 | int16_t VRC6Pulse_nOutputTable_L[0x10] IDATA_ATTR MEM_ALIGN_ATTR; |
679 | 694 | ||
680 | struct VRC6SawWave | 695 | struct VRC6SawWave |
681 | { | 696 | { |
@@ -697,7 +712,7 @@ struct VRC6SawWave | |||
697 | 712 | ||
698 | }; | 713 | }; |
699 | 714 | ||
700 | int16_t VRC6Saw_nOutputTable_L[0x20] IDATA_ATTR; | 715 | int16_t VRC6Saw_nOutputTable_L[0x20] IDATA_ATTR MEM_ALIGN_ATTR; |
701 | 716 | ||
702 | struct Wave_Squares | 717 | struct Wave_Squares |
703 | { | 718 | { |
@@ -735,7 +750,7 @@ struct Wave_Squares | |||
735 | int32_t nMixL; | 750 | int32_t nMixL; |
736 | }; | 751 | }; |
737 | 752 | ||
738 | int16_t Squares_nOutputTable_L[0x10][0x10] IDATA_ATTR; | 753 | int16_t Squares_nOutputTable_L[0x10][0x10] IDATA_ATTR MEM_ALIGN_ATTR; |
739 | 754 | ||
740 | struct Wave_TND | 755 | struct Wave_TND |
741 | { | 756 | { |
@@ -1161,16 +1176,16 @@ inline void Wave_TND_ClockMinor() | |||
1161 | * Memory | 1176 | * Memory |
1162 | */ | 1177 | */ |
1163 | /* RAM: 0x0000 - 0x07FF */ | 1178 | /* RAM: 0x0000 - 0x07FF */ |
1164 | uint8_t pRAM[0x800] IDATA_ATTR; | 1179 | uint8_t pRAM[0x800] IBSS_ATTR_NSF_LARGE_IRAM MEM_ALIGN_ATTR; |
1165 | /* SRAM: 0x6000 - 0x7FFF (non-FDS only) */ | 1180 | /* SRAM: 0x6000 - 0x7FFF (non-FDS only) */ |
1166 | uint8_t pSRAM[0x2000]; | 1181 | uint8_t pSRAM[0x2000] IBSS_ATTR_NSF_LARGE_IRAM MEM_ALIGN_ATTR; |
1167 | /* ExRAM: 0x5C00 - 0x5FF5 (MMC5 only) | 1182 | /* ExRAM: 0x5C00 - 0x5FF5 (MMC5 only) |
1168 | * Also holds NSF player code (at 0x5000 - 0x500F) */ | 1183 | * Also holds NSF player code (at 0x5000 - 0x500F) */ |
1169 | uint8_t pExRAM[0x1000]; | 1184 | uint8_t pExRAM[0x1000] IBSS_ATTR_NSF_LARGE_IRAM MEM_ALIGN_ATTR; |
1170 | /* Full ROM buffer */ | 1185 | /* Full ROM buffer */ |
1171 | uint8_t* pROM_Full IDATA_ATTR; | 1186 | uint8_t* pROM_Full IDATA_ATTR; |
1172 | 1187 | ||
1173 | uint16_t main_nOutputTable_L[0x8000]; | 1188 | uint16_t main_nOutputTable_L[0x8000] MEM_ALIGN_ATTR; |
1174 | 1189 | ||
1175 | uint8_t* pROM[10] IDATA_ATTR;/* ROM banks (point to areas in pROM_Full) */ | 1190 | uint8_t* pROM[10] IDATA_ATTR;/* ROM banks (point to areas in pROM_Full) */ |
1176 | /* 0x8000 - 0xFFFF */ | 1191 | /* 0x8000 - 0xFFFF */ |
@@ -1188,8 +1203,8 @@ int32_t nROMMaxSize; /* size of allocated pROM_Full buffer */ | |||
1188 | 1203 | ||
1189 | typedef uint8_t ( *ReadProc)(uint16_t); | 1204 | typedef uint8_t ( *ReadProc)(uint16_t); |
1190 | typedef void ( *WriteProc)(uint16_t,uint8_t); | 1205 | typedef void ( *WriteProc)(uint16_t,uint8_t); |
1191 | ReadProc ReadMemory[0x10] IDATA_ATTR; | 1206 | ReadProc ReadMemory[0x10] IDATA_ATTR MEM_ALIGN_ATTR; |
1192 | WriteProc WriteMemory[0x10] IDATA_ATTR; | 1207 | WriteProc WriteMemory[0x10] IDATA_ATTR MEM_ALIGN_ATTR; |
1193 | 1208 | ||
1194 | /* | 1209 | /* |
1195 | * 6502 Registers / Mode | 1210 | * 6502 Registers / Mode |
@@ -3541,7 +3556,7 @@ int32_t GetSamples(uint8_t* buffer,int32_t buffersize) | |||
3541 | /* Lookup Tables */ | 3556 | /* Lookup Tables */ |
3542 | 3557 | ||
3543 | /* the number of CPU cycles used for each instruction */ | 3558 | /* the number of CPU cycles used for each instruction */ |
3544 | static const uint8_t CPU_Cycles[0x100] = { | 3559 | static const uint8_t CPU_Cycles[0x100] ICONST_ATTR_NSF_LARGE_IRAM = { |
3545 | 7,6,0,8,3,3,5,5,3,2,2,2,4,4,6,6, | 3560 | 7,6,0,8,3,3,5,5,3,2,2,2,4,4,6,6, |
3546 | 2,5,0,8,4,4,6,6,2,4,2,7,4,4,7,7, | 3561 | 2,5,0,8,4,4,6,6,2,4,2,7,4,4,7,7, |
3547 | 6,6,0,8,3,3,5,5,4,2,2,2,4,4,6,6, | 3562 | 6,6,0,8,3,3,5,5,4,2,2,2,4,4,6,6, |
@@ -3560,7 +3575,7 @@ static const uint8_t CPU_Cycles[0x100] = { | |||
3560 | 2,5,0,8,4,4,6,6,2,4,2,7,4,4,7,7 }; | 3575 | 2,5,0,8,4,4,6,6,2,4,2,7,4,4,7,7 }; |
3561 | 3576 | ||
3562 | /* the status of the NZ flags for the given value */ | 3577 | /* the status of the NZ flags for the given value */ |
3563 | static const uint8_t NZTable[0x100] = { | 3578 | static const uint8_t NZTable[0x100] ICONST_ATTR_NSF_LARGE_IRAM = { |
3564 | Z_FLAG,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | 3579 | Z_FLAG,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, |
3565 | 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | 3580 | 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, |
3566 | 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, | 3581 | 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, |